CN104465621B - Dual graphing electrical testing structure and monitoring method - Google Patents
Dual graphing electrical testing structure and monitoring method Download PDFInfo
- Publication number
- CN104465621B CN104465621B CN201410686757.0A CN201410686757A CN104465621B CN 104465621 B CN104465621 B CN 104465621B CN 201410686757 A CN201410686757 A CN 201410686757A CN 104465621 B CN104465621 B CN 104465621B
- Authority
- CN
- China
- Prior art keywords
- metal layer
- electrical test
- splicing
- double
- lower metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims abstract description 38
- 230000009977 dual effect Effects 0.000 title claims abstract description 22
- 238000012544 monitoring process Methods 0.000 title claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 92
- 238000000059 patterning Methods 0.000 claims description 68
- 238000000926 separation method Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 238000005194 fractionation Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 11
- 238000013461 design Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010998 test method Methods 0.000 description 2
- 230000002427 irreversible effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
Abstract
The invention provides a kind of Dual graphing electrical testing structure and monitoring method, it includes：Upper metal level, lower metal layer, and it is connected to the through-hole structure of the upper and lower metal level；Through-hole structure is located at the overlapping region of upper metal level and lower metal layer.There is Dual graphing to split graph layer for upper metal level and/or lower metal layer, and Dual graphing, which splits graph layer, has splicing overlay region；Splicing overlay region is located in the overlapping region of upper metal level and lower metal layer, and is connected with the top of through-hole structure and/or bottom.Electrical testing is carried out to this group of electrical testing structure, the resistance value of corresponding through-hole structure can be obtained, it may thereby determine that the zone of reasonableness of splicing lap, the zone of reasonableness of the splicing lap can instruct the fractionation situation in Dual graphing split process, it is set to establish more rational fractionation rule, so as to monitor the splice region formed in metal level Dual graphing split process to the influence for the through hole resistance being attached thereto.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a double-patterning electrical test structure and a method for monitoring through hole resistance of a double-patterning splicing area.
Background
When the moore's law continues to make the extended steps irreversible, the double patterning technology is undoubtedly the best choice in the industry, and the double patterning technology can effectively fill the gap of the lithography technology with 32 nm or even smaller nodes only by slightly changing the existing lithography infrastructure. The principle of double patterning is to break a set of high density circuit patterns into two separate sets of lower density patterns, which are then fabricated onto a wafer.
In the 32 nm or even smaller pitch lithography process, due to the existence of the optical proximity effect, the line end rounding (line end rounding), the line end shortening (line end short), the corner rounding (corner rounding), the critical dimension deviation (critical dimension offset), the line-to-line bridging (line bridge) and other pattern distortion phenomena occur.
When double patterning is split, some splicing regions are generated. Because of the distortion phenomena, the appearance of the double-patterning splicing area on the actual silicon wafer is different from the designed pattern. Meanwhile, the splicing areas are subjected to two times of photoetching (photoetching-etching process: LLE) and even two times of hard mask layer etching (photoetching-etching-photoetching-etching: LELE), and certain influence is caused on the electrical test result.
Referring to fig. 1a and 1b, fig. 1a and 1b illustrate a distortion phenomenon of a pattern generated by an optical proximity effect in a splicing region after dual patterning splitting; FIG. 1a is a schematic diagram showing that after double patterning splitting, the overlapping amount of the splicing region is zero, and due to the distortion phenomenon that the line end becomes round and the line end becomes short caused by the optical proximity effect, when the splicing overlapping amount of the design pattern 101 is zero, the pattern 102 formed on the silicon wafer appears to be an open circuit after the double patterning process; fig. 1b shows a schematic diagram that the overlapping amount of the splicing region after double patterning splitting is greater than zero, and also due to distortion, the area of the actual splicing overlapping region of the pattern 202 finally formed on the silicon wafer by the design pattern 201 is smaller than that of the design pattern. Therefore, it is not negligible how to avoid the influence of the dual patterning split on the resistance of the via connected to the splicing region.
Disclosure of Invention
In order to overcome the problems, the invention provides a double-patterning electrical test structure and a method for monitoring the through hole resistance of a double-patterning splicing region, so that the reasonable range of splicing overlapping amount can be determined.
In order to achieve the above object, the present invention provides a dual patterned electrical test structure, comprising: the structure comprises an upper metal layer, a lower metal layer and a through hole structure connected with the upper metal layer and the lower metal layer; the through hole structure is positioned in an overlapping area of the upper metal layer and the lower metal layer; wherein,
the upper metal layer and/or the lower metal layer are/is provided with double graphical split graphic layers, and the double graphical split graphic layers are provided with splicing overlapping areas; the splice overlap region is located in the overlap region of the upper and lower metal layers and is connected to a top and/or bottom of the via structure.
Preferably, the overlapping amount of the splicing overlapping area of the dual patterning splitting graphic layer is greater than or equal to zero.
Preferably, the splice overlap region covers the top and/or bottom of the via structure.
Preferably, the stitching overlap region is the same pattern as the top and/or bottom of the via structure.
Preferably, the upper metal layer and/or the lower metal layer are strip-shaped.
The invention also provides a monitoring method of the through hole resistance of the double-graphical splicing region, which is characterized in that the electrical test structure is adopted; the monitoring method comprises the following steps:
step 01: setting a group of different overlapping quantities, and carrying out double-patterning splitting on the patterns of the upper metal layer and/or the lower metal layer according to the different overlapping quantities to obtain a group of electrical test structures with double-patterning splitting pattern layers; wherein, the double graphical split graphic layers in the group of electrical test structures contain splicing overlapping areas with different overlapping amounts; the splice overlap region is located in the overlap region of the upper and lower metal layers and is connected to a top and/or bottom of the via structure;
step 02: carrying out electrical test on the group of electrical test structures to obtain the resistance value of the through hole structure in the corresponding electrical test structure;
step 03: carrying out electrical test on the electrical test structure which is not subjected to double patterning splitting to obtain the resistance value of the corresponding through hole structure;
step 04: and determining a target range of the overlapping amount of the splicing overlapping area according to the resistance value in the step 02 and the resistance value in the step 03.
Preferably, the overlapping amount of the splicing overlapping region in the step 01 is greater than or equal to zero.
Preferably, the splice overlap region covers the top and/or bottom of the via structure.
Preferably, the splice overlap region is the same shape as the top and/or bottom of the via structure.
Preferably, the electrical test is performed in step 02 or in step 03 using a four-terminal test.
The invention relates to a double-patterning electrical test structure and a method for monitoring the through hole resistance of a double-patterning splicing overlapping region, the upper metal layer and/or the lower metal layer are subjected to double patterning splitting by arranging the upper metal layer and the lower metal layer and the through hole structure for connecting the upper metal layer and the lower metal layer to obtain a group of electrical test structures containing double patterning splitting pattern layers with different splicing overlapping amounts, the set of electrical test structures are electrically tested to obtain the resistance value of the corresponding through hole structure, so that a reasonable range of the splicing overlapping amount can be determined, for example, according to the process requirements and the electrical test specification, the reasonable range of the splicing overlapping amount can guide the splitting condition in the double-patterning splitting process, so that a more reasonable splitting rule is established, therefore, the influence of the splicing region formed in the double patterning splitting process of the metal layer on the resistance of the through hole connected with the splicing region is monitored.
Drawings
FIG. 1a is a schematic diagram showing that the overlapping amount of the splicing overlapping region after double patterning splitting is zero
FIG. 1b shows a schematic diagram of a stitching overlap region with an overlap amount greater than zero after double patterning splitting
FIG. 2 is a schematic diagram of the electrical test structure in accordance with a preferred embodiment of the present invention
FIG. 3 is a schematic diagram of an electrical test structure without double patterning splitting according to a preferred embodiment of the present invention
FIG. 4 is a schematic diagram of an electrical test structure without double patterning splitting according to a preferred embodiment of the present invention
5a-5d are diagrams illustrating dual graphical split graphics layers with different amounts of stitching overlap regions in accordance with a preferred embodiment of the present invention
FIG. 6 is a flow chart of a monitoring method for via resistance of a dual-patterned splicing region
Detailed Description
In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The invention designs a double-patterning electrical test structure and a monitoring method for the through hole resistance of the double-patterning splicing overlapping area by utilizing the principle that different splicing overlapping amounts of the double-patterning splicing area have different influences on the through hole resistance.
The invention relates to a double-patterning electrical test structure, which comprises: the structure comprises an upper metal layer, a lower metal layer and a through hole structure connected with the upper metal layer and the lower metal layer; the via structure is located in an overlapping region of the upper metal layer and the lower metal layer. The upper metal layer and/or the lower metal layer are/is provided with double graphical split graphic layers, and the double graphical split graphic layers are provided with splicing overlapping areas; the splice overlap region is located in the overlap region of the upper and lower metal layers and is connected to the top and/or bottom of the via structure.
The dual patterned electrical test structure will be described in further detail below with reference to fig. 2-5 d and a specific embodiment. FIG. 2 illustrates various portions of an electrical test structure in accordance with a preferred embodiment of the present invention; FIG. 3 is a schematic diagram of an electrical test structure without double patterning splitting according to a preferred embodiment of the present invention; FIG. 4 is a schematic diagram of an electrical test structure without double patterning splitting according to a preferred embodiment of the present invention; fig. 5a-5d show schematic diagrams of dual patterned split graphic layers with different amounts of stitching overlap regions according to a preferred embodiment of the present invention. It should be noted that the drawings are in a simplified form and are not to precise scale, and are only used for conveniently and clearly achieving the purpose of assisting in describing the embodiment.
Referring to fig. 2, the dual patterned electrical test structure of the present embodiment includes: the metal layer structure comprises an upper metal layer 1 in a long strip shape, a lower metal layer 2 in a long strip shape, and a square through hole structure 3 connected with the upper metal layer 1 and the lower metal layer 2; the via structure 3 is located in the overlapping area of the upper metal layer 1 and the lower metal layer 2. In this embodiment, the upper metal layer 1 has a double patterning splitting pattern layer: a first split graph 11 and a second split graph 12, wherein a splicing overlapping area is arranged between the first split graph layer 11 and the second split graph layer 12; the splicing overlap region is located in the overlap region of the upper and lower metal layers 1, 2 and is connected with the top of the through hole structure 3. The overlapping amount of the splicing overlapping area of the double patterning split graphic layer is larger than or equal to zero.
Referring to fig. 3, in the case of no double patterning splitting, the via structure 3 is connected to the first splitting pattern layer 11 and the lower metal layer 2, that is, there is no splicing overlap region at the connection position of the via structure 3; referring to fig. 4, without dual patterning splitting, the via structure 3 is connected to the second splitting pattern layer 12 and the lower metal layer 2, that is, the connection position of the via structure 3 has no splicing overlap region; the resistance of the through hole structure in the two electrical test structures can be used as a reference standard of the resistance value of the through hole after double patterning.
Referring to fig. 5a-5d, the cases where the overlap amount of the splicing overlap area of the dual-patterned splitting pattern layer connected to the via structure in the electrical test structure is zero and is greater than zero are shown respectively, in fig. 5a, the overlap amount of the splicing overlap area of the first splitting pattern layer 11 and the second splitting pattern layer 12 is zero, which is the most extreme case in the dual-patterned splitting process, and the via structure 3 is connected to the splicing overlap area of the first splitting pattern layer 11 and the second splitting pattern layer 12 and is located in the overlap area of the upper metal layer 1 and the lower metal layer 2; in fig. 5b, the splicing overlap region of the first splitting pattern layer 11 and the second splitting pattern layer 12 is connected with and covers the top of the through hole structure 3, and the shape of the splicing overlap region is the same as that of the top of the through hole structure 3, but the area of the splicing overlap region is larger than that of the top of the through hole structure 3; in fig. 5c, the overlapping amount of the splicing overlap region of the first splitting graphic layer 11 and the second splitting graphic layer 12 is increased, the splicing overlap region is connected with the through-hole structure 3, and the top of the through-hole structure 3 is covered and exceeds the top area of the through-hole structure 3; in fig. 5d, the overlapping amount of the splicing overlap region of the first splitting pattern layer 11 and the second splitting pattern layer 12 is further increased, and the splicing overlap region is connected to the through hole structure 3 and covers and exceeds the top area of the through hole structure 3.
The electrical test structure can further determine the target range of the overlapping amount of the splicing overlapping area, namely a reasonable range, and is used for guiding the splitting condition in the double patterning splitting process to establish a more reasonable splitting rule, so that the influence of the splicing overlapping area formed in the double patterning splitting process of the metal layer on the resistance of the through hole connected with the splicing overlapping area is monitored.
The invention also provides a method for electrical testing by adopting the test structure, which comprises the following steps:
step 01: setting a group of different overlapping quantities, and carrying out double-patterning splitting on the patterns of the upper metal layer and/or the lower metal layer according to the different overlapping quantities to obtain a group of electrical test structures with double-patterning splitting pattern layers; wherein, the double graphical split graphic layers in the group of electrical test structures contain splicing overlapping areas with different overlapping amounts; the splicing overlapping area is positioned in the overlapping area of the upper metal layer and the lower metal layer and is connected with the top and/or the bottom of the through hole structure;
step 02: performing electrical test on the group of electrical test structures to obtain the resistance value of the through hole structure of the corresponding electrical test structure;
step 03: carrying out electrical test on the electrical test structure which is not subjected to double patterning splitting to obtain the resistance value of the corresponding through hole structure;
step 04: and determining the target range of the overlapping amount of the splicing region according to the resistance value in the step 02 and the resistance value in the step 03.
The method for monitoring the via resistance of the double-patterned splicing region according to the present invention is further described in detail with reference to fig. 6 and an embodiment.
In this embodiment, referring to fig. 6, the monitoring method of the via resistance of the dual-patterned splicing region adopts the electrical test structure; which comprises the following steps:
step 11: setting a group of different overlapping quantities, and carrying out double-patterning splitting on the patterns of the upper metal layer according to the different overlapping quantities to obtain a group of electrical test structures with double-patterning splitting pattern layers; the dual graphical split pattern layers in the group of electrical test structures contain splicing overlapping areas with different overlapping amounts; the splicing overlapping area is positioned in the overlapping area of the upper metal layer and the lower metal layer and is connected with the top of the through hole structure;
specifically, the overlap amount is greater than or equal to zero, and different overlap amounts can be preset; in this embodiment, the pattern of the upper metal layer is subjected to double patterning splitting; referring to fig. 5a-5d, the upper metal layer is strip-shaped, and the overlap amount of the splicing overlap region is set to be zero or more than zero, and then the double patterning splitting is performed according to the set overlap amount. When the splicing overlap amount is greater than zero, the overlap portion of the splicing overlap region covers the top of the through hole structure, and the shape of the splicing overlap region is the same as that of the top of the through hole structure, but the area of the splicing overlap region is greater than that of the top of the through hole structure.
Step 02: performing electrical test on the group of electrical test structures to obtain the resistance value of the through hole structure in the corresponding electrical test structure; here, the electrical test may be performed using, but not limited to, a four-terminal test method.
Step 03: carrying out electrical test on the electrical test structure which is not subjected to double patterning splitting to obtain the resistance value of the corresponding through hole structure; here, electrical testing can be performed using, but is not limited to, a four-terminal test method; the electrical test structure without double patterning separation can be continued with reference to fig. 3 and 4, which are not described herein again.
Step 04: and determining a target range of the overlapping amount of the splicing overlapping area according to the resistance value in the step 02 and the resistance value in the step 03.
Specifically, according to the resistance values in the above steps 02 and 03, the target range of the overlapping amount of the splicing overlapping region, that is, the reasonable range, can be determined by combining the process requirements and the electrical test specifications, and is used for guiding the splitting condition in the double patterning splitting process to establish a more reasonable splitting rule, so that the influence of the splicing region formed in the double patterning splitting process of the metal layer on the resistance of the through hole connected with the splicing region is monitored.
It should be noted that, the above embodiment performs double patterning splitting on the upper metal layer, the present invention is not limited to this, and may also perform double patterning splitting on the lower metal layer, or perform double patterning splitting on the upper and lower metal layers at the same time; the corresponding electrical test structure and monitoring method can refer to the above embodiments, which are not described in detail herein.
The invention relates to a double-patterning electrical test structure and a method for monitoring the through hole resistance of a double-patterning splicing overlapping region, the upper metal layer and/or the lower metal layer are subjected to double patterning splitting by arranging the upper metal layer and the lower metal layer and the through hole structure for connecting the upper metal layer and the lower metal layer to obtain a group of electrical test structures containing double patterning splitting pattern layers with different splicing overlapping amounts, the set of electrical test structures are electrically tested to obtain the resistance value of the corresponding through hole structure, so that a reasonable range of the splicing overlapping amount can be determined, for example, according to the process requirements and the electrical test specification, the reasonable range of the splicing overlapping amount can guide the splitting condition in the double-patterning splitting process, so that a more reasonable splitting rule is established, therefore, the influence of the splicing region formed in the double patterning splitting process of the metal layer on the resistance of the through hole connected with the splicing region is monitored.
Although the present invention has been described with reference to preferred embodiments, which are illustrated for the purpose of illustration only and not for the purpose of limitation, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A dual patterned electrical test structure, comprising: the structure comprises an upper metal layer, a lower metal layer and a through hole structure connected with the upper metal layer and the lower metal layer; the through hole structure is positioned in an overlapping area of the upper metal layer and the lower metal layer; wherein,
the upper metal layer and/or the lower metal layer are/is provided with double graphical split graphic layers, and the double graphical split graphic layers are provided with splicing overlapping areas; the splice overlap region is located in an overlap region of the upper metal layer and the lower metal layer and is connected to a top and/or a bottom of the via structure.
2. The dual patterned electrical test structure of claim 1, wherein an amount of overlap of the stitching overlap region of the dual patterned split pattern layer is greater than or equal to zero.
3. The dual patterned electrical test structure of claim 2, wherein the splice overlap region covers a top and/or bottom of the via structure.
4. The dual patterned electrical test structure of claim 3, wherein the splice overlap region is the same shape as the top and/or bottom of the via structure.
5. The dual patterned electrical test structure of claim 1, wherein the upper metal layer and/or the lower metal layer is elongated.
6. A monitoring method for through hole resistance of a double-patterning splicing region is characterized in that the electrical test structure of claim 1 is adopted; the monitoring method comprises the following steps:
step 01: setting a group of different overlapping quantities, and carrying out double-patterning splitting on the patterns of the upper metal layer and/or the lower metal layer according to the different overlapping quantities to obtain a group of electrical test structures with double-patterning splitting pattern layers; wherein, the double graphical split graphic layers in the group of electrical test structures contain splicing overlapping areas with different overlapping amounts; the splice overlap region is located in an overlap region of the upper metal layer and the lower metal layer and is connected with the top and/or bottom of the via structure;
step 02: carrying out electrical test on the group of electrical test structures to obtain the resistance value of the through hole structure in the corresponding electrical test structure;
step 03: carrying out electrical test on the electrical test structure which is not subjected to double patterning splitting to obtain the resistance value of the corresponding through hole structure; wherein, the electricity test structure without double patterning separation comprises: under the condition of not carrying out double patterning splitting, the upper metal layer and the lower metal layer of the through hole structure are connected, namely, the connecting position of the through hole structure is not provided with a splicing overlapping area;
step 04: and determining a target range of the overlapping amount of the splicing overlapping area according to the resistance value in the step 02 and the resistance value in the step 03.
7. The monitoring method according to claim 6, wherein the overlap amount of the splice overlap region in the step 01 is greater than or equal to zero.
8. The monitoring method according to claim 7, wherein the splice overlap region covers a top and/or a bottom of the via structure.
9. The monitoring method of claim 8, wherein the splice overlap region is the same shape as the top and/or bottom of the via structure.
10. The monitoring method according to claim 6, wherein the electrical test is performed in step 02 or in step 03 using a four-terminal test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410686757.0A CN104465621B (en) | 2014-11-25 | 2014-11-25 | Dual graphing electrical testing structure and monitoring method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410686757.0A CN104465621B (en) | 2014-11-25 | 2014-11-25 | Dual graphing electrical testing structure and monitoring method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104465621A CN104465621A (en) | 2015-03-25 |
| CN104465621B true CN104465621B (en) | 2018-01-26 |
Family
ID=52911425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410686757.0A Active CN104465621B (en) | 2014-11-25 | 2014-11-25 | Dual graphing electrical testing structure and monitoring method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104465621B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3659055A4 (en) * | 2017-07-24 | 2021-04-28 | Cerebras Systems Inc. | Apparatus and method for multi-die interconnection |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101109911A (en) * | 2006-07-21 | 2008-01-23 | 海力士半导体有限公司 | Pattern decomposition method for double exposure |
| CN103311102A (en) * | 2012-03-13 | 2013-09-18 | 格罗方德半导体公司 | Methods of making jogged layout routings double patterning compliant |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008051583A (en) * | 2006-08-23 | 2008-03-06 | Kokusai Gijutsu Kaihatsu Co Ltd | Inspection device |
| US8361335B2 (en) * | 2009-06-08 | 2013-01-29 | GlobalFoundries, Inc. | Methods for fabricating semiconductor devices |
-
2014
- 2014-11-25 CN CN201410686757.0A patent/CN104465621B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101109911A (en) * | 2006-07-21 | 2008-01-23 | 海力士半导体有限公司 | Pattern decomposition method for double exposure |
| CN103311102A (en) * | 2012-03-13 | 2013-09-18 | 格罗方德半导体公司 | Methods of making jogged layout routings double patterning compliant |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104465621A (en) | 2015-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102215664B1 (en) | Multifunctional circuit board detection module and detection method | |
| KR102532200B1 (en) | Test pattern, test method for semiconductor device, and computer-implemented method for designing an integrated circuit layout | |
| CN104465621B (en) | Dual graphing electrical testing structure and monitoring method | |
| JP2008218921A (en) | Pattern for measuring amount of positional misalignment and measuring method, and semiconductor device | |
| CN104716123B (en) | A kind of test method and test structure | |
| US9851398B2 (en) | Via leakage and breakdown testing | |
| CN102645586A (en) | Glass base plate, through hole resistance measuring method and metal wire resistance measuring method | |
| CN103972119B (en) | A kind of method testing device and this test measurement device deviation of the alignment of use | |
| CN205452279U (en) | Semiconductor junction constructs with registration mark | |
| US20120298992A1 (en) | Test layout structure | |
| JPH02224354A (en) | Inspection of deviation of contact hole in semiconductor device | |
| CN104716124B (en) | A kind of method of testing and test structure | |
| CN204216029U (en) | Be formed at and wafer trims unit | |
| KR102124628B1 (en) | Test structures of semiconductor device | |
| CN205452277U (en) | Semiconductor junction constructs with registration mark | |
| CN205452278U (en) | Semi -conductor test structure | |
| KR20090068662A (en) | Test pattern of semicondictor device and method of manufacturing thereof | |
| CN205177791U (en) | Detection structure of metal bridging defect | |
| US8981842B1 (en) | Integrated circuit comprising buffer chain | |
| CN102981332B (en) | Line-width measuring method and device | |
| KR20100013970A (en) | Test pattern of semiconductor device and method for thereof | |
| KR20100013977A (en) | A test pattern of a semiconductor device and method for manufacturing the same | |
| JP2008098271A (en) | Inspection pad | |
| JP2006071567A (en) | Method for determining contact state of probe, and method and apparatus for inspecting circuit board | |
| KR20080040280A (en) | A pattern structure for teg(test element group) and method of forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |