Templates generator: make Verilog/SystemVerilog module template by parameters and ports list
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Updated
Jan 2, 2023 - Python
Templates generator: make Verilog/SystemVerilog module template by parameters and ports list
Script de PowerShell para configurar rápidamente un entorno de desarrollo SystemVerilog, incluyendo la instalación de VS Code, extensiones relevantes y herramientas de compilación
RISC-V five stage pipline CPU
Segundo proyecto para el curso de Arquitectura de Computadores. La idea es hacer un ASIP (Application Specific Set Processor) que genere interpolación de imagen por medio de un compilador, código en ensamblador, un procesador pipeline y scripts en alto nivel.
MIPS fine-grained multithreaded, five-stage pipelined, and software-interlocked core in SystemVerilog.
A project to implement and test synchronous and asynchronous FIFO using Questasim software.
Course projects, capstone and individual studies.
7-segment snake using a microcontroller
Restricted Instruction Set Computer (V5) OTTER architecture for Xilinx Basys3 Board. Developed using Xilinx Vivado Suite
Simple ipod made using System Verilog and implemented on the De1Soc
CAD for automatically configuring FPGA "Marsohod"
Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
Computer Architecture Lab Projects
First and Last Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with system verilog + Functional verification.
Open IC DEV 是一个基于 iVerilog, SystemC, UVM, verible, verilator, oh-my-zsh,vscode 等开源工具链的开发环境。
Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
Complete design of a 32-bit 5-stage pipelined MIPS Processor with an L1 cache with snoopy coherency with achieved Gate-level Frequency of 53MHz and fully synthesised on an FPGA
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