"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
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Updated
Jul 9, 2023 - Verilog
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
All my projects, homework, hand writings, course slides and anything I have learned and done during my study in IUT universityπ. feel free to give it a β=)
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>
Final Project for Digital Systems Design Course, Fall 2020
Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA
My activity in digital systems
Digital Systems Design - Spring 2023 - Sharif University of Technology
3-stage RISC-V Pipelined Processor with interrupt CSR support
Implementation and verification of a hardware-based controller for a three-phase induction motor on an FPGA β Bachelor's Thesis [UPC-TTU, 2019]
Repositorio con las 12 prΓ‘cticas en VHDL para el curso impartido por la profesora Nayeli Vega, tomada en la ESCOM, IPN.
Term project and lab assignments for CS303 - Logic and Digital System course in SabancΔ± University, Fall 2021-2022.
Digital Logic Design (DLD) is a fundamental subject for the engineering students worldwide. Well, many students find it difficult to design the digital circuits properly while pursuing the DLD course in colleges or universities. Therefore, I will try to assist those students by sharing my lab works with them.
Lab projects using Verilog HDL
This repository contains projects developed by students of the Bachelor of Computer Engineering program at Qazvin Islamic Azad University (QIAU). The projects cover various topics in computer engineering, including digital systems, microprocessor, logical circuits, computer graphics, and etc.
Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications
Contains my resume
Academic Lab Course of the 27th batch of Computer Science & Engineering | University of Rajshahi - π§π©
This GitHub repository Consists of materials, code samples, documentation, and valuable resources related to the Information Technology (IT) Department at the National Institute of Technology Karnataka (NITK). π Resource Library π» Code Samples ποΈ Project Repositories
πΎ My studies with Verilog and notions of digital systems.
Binary Adder, Subtractor, Multiplier, Divider in VHDL with FPGA board.
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