Verilog Experiments

Here are some of my studies that I carry out using the Verilog language.

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😃 Author

Name		Name	Last commit message	Last commit date
Latest commit History 16 Commits
1 - transistors		1 - transistors
2 - gate (NOT)		2 - gate (NOT)
3 - gtkwave - basics		3 - gtkwave - basics
4 - gtkwave - example		4 - gtkwave - example
5 - simple device		5 - simple device
6 - gate (NAND)		6 - gate (NAND)
7 - gate (AND)		7 - gate (AND)
8 - gate (XOR)		8 - gate (XOR)
9 - Half-Adder		9 - Half-Adder
license		license
readme.md		readme.md