WO2022127560A1 - Signal processing system in oscilloscope, oscilloscope and signal processing method - Google Patents

Signal processing system in oscilloscope, oscilloscope and signal processing method Download PDF

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Publication number
WO2022127560A1
WO2022127560A1 PCT/CN2021/133460 CN2021133460W WO2022127560A1 WO 2022127560 A1 WO2022127560 A1 WO 2022127560A1 CN 2021133460 W CN2021133460 W CN 2021133460W WO 2022127560 A1 WO2022127560 A1 WO 2022127560A1
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Prior art keywords
signal
temporarily stored
sampling signal
register
accumulator
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PCT/CN2021/133460
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French (fr)
Chinese (zh)
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刘福奇
徐冬冬
钟隆辉
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深圳市道通科技股份有限公司
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Priority claimed from CN202011478023.5A external-priority patent/CN112600561B/en
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Publication of WO2022127560A1 publication Critical patent/WO2022127560A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values

Definitions

  • the present application relates to the technical field of oscilloscopes, and in particular to a signal processing system in an oscilloscope, an oscilloscope and a signal processing method in the oscilloscope.
  • Oscilloscopes can measure signal characteristics such as amplitude, frequency, phase, spectrum, etc. The deeper the storage depth of the oscilloscope, the more complete the data captured at one time, and it is easier to judge whether the signal is normal by analyzing the characteristics of the signal.
  • the existing oscilloscope When the existing oscilloscope performs signal analysis, it is necessary to first capture the analog signal, and then perform analog-to-digital signal conversion through ADC sampling. The higher the ADC sampling resolution, the lower the theoretical signal quantization distortion and the higher the signal-to-noise ratio. high.
  • the oscilloscope of the current oscilloscope generally has a fixed resolution and a fixed precision, which is not suitable for scenarios with weak signals.
  • embodiments of the present invention provide a signal processing system in an oscilloscope, an oscilloscope, and a signal processing method in the oscilloscope, which are used to solve the problem of low sampling data accuracy of the oscilloscope in the prior art.
  • a signal processing system in an oscilloscope which is applied in an oscilloscope, the signal processing system includes a signal sampling module and at least one register accumulation module; the register accumulation module includes a first register , the second register and the first accumulator;
  • the signal sampling module configured to receive an analog signal and generate a digital sampling signal according to the sampling of the analog signal
  • the first register is used to sequentially receive the first temporarily stored sampling signal and the second temporarily stored sampling signal, send the first temporarily stored sampling signal to the first accumulator and the second register respectively, and Send the second temporarily stored sampling signal to the first accumulator; wherein, the first temporarily stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at the first moment , the second temporarily stored sampling signal is the digital sampling signal of a preset number of digits generated by the signal sampling module at a second moment; the second moment is an adjacent moment after the first moment;
  • the second register configured to receive the first temporarily stored sampling signal, and send the first temporarily stored sampling signal to the first accumulator
  • the first accumulator is configured to accumulate the first temporarily stored sampling signal and the second temporarily stored sampling signal to obtain a first accumulated signal.
  • the signal processing system further includes: a third register, a fourth register, a second accumulator, and a third accumulator;
  • the third register is used to sequentially receive the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the signal sampling module, and store the fourth temporarily stored sampling signal.
  • the storage sampling signal is sent to the second accumulator, and the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal are sent to the the fourth register; wherein, the third temporarily stored sampling signal is the digital sampling signal with a preset number of digits generated by the signal sampling module at the third moment, and the fourth temporarily stored sampling signal is the digital sampling signal of the preset number of bits generated by the signal sampling module at the fourth moment;
  • the fourth register is used to receive the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the third register, and the third temporary storage sampling signal sending the stored sampling signal to the second accumulator, and sending the first temporarily stored sampling signal and the second temporarily stored sampling signal to the first register;
  • the second accumulator for accumulating the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to obtain a second accumulated signal
  • the third accumulator is used for accumulating the first accumulating signal and the second accumulating signal to obtain a target accumulating signal.
  • the oscilloscope includes a processor, the first register, the second register, the third register, the fourth register, the first accumulator, the first Both the two accumulators and the third accumulator are arranged in the processor;
  • the processor is further configured to perform signal processing according to the target accumulated signal to obtain signal characteristics of the target accumulated signal.
  • the first register, the second register, the third register, the fourth register, the first accumulator, the second accumulator, and the third accumulator is the same.
  • a detection module for calculating the amplitude of the digital sampling signal
  • a determination module configured to determine whether the digital sampling signal is lower than a preset threshold according to the amplitude, and send the first temporarily stored sampling signal to the third register when it is lower than the preset threshold.
  • the determining module is further configured to send the first temporarily stored sampling signal to the processor when the amplitude is higher than or equal to the preset threshold;
  • the processor performs signal processing according to the first temporarily stored sampling signal to obtain the signal characteristic of the target accumulated signal.
  • an oscilloscope is provided, and the oscilloscope includes the above-mentioned signal processing system.
  • a signal processing method in an oscilloscope including:
  • the signal sampling module receives the analog signal and generates a digital sampling signal according to the sampling of the analog signal
  • the first register sequentially receives the first temporarily stored sampling signal and the second temporarily stored sampling signal, sends the first temporarily stored sampling signal to the first accumulator and the second register respectively, and sends the second temporarily stored sampling signal to the first accumulator and the second register respectively. sent to the first accumulator; wherein, the first temporarily stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at the first moment, and the second temporarily stored sampling signal is the digital sampling signal of a preset number of digits generated by the signal sampling module at a second moment; the second moment is an adjacent moment after the first moment;
  • the second register receives the first temporarily stored sampling signal, and sends the first temporarily stored sampling signal to the first accumulator;
  • the first accumulator accumulates the first temporarily stored sampling signal and the second temporarily stored sampling signal to obtain a first accumulated signal.
  • the third register sequentially receives the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the signal sampling module, and sends the fourth temporarily stored sampling signal to
  • the second accumulator sends the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to the fourth register;
  • the third temporarily stored sampling signal is the digital sampling signal of a preset number of bits generated by the signal sampling module at the third moment
  • the fourth temporarily stored sampling signal is the signal generated by the signal sampling module at the fourth moment. the digital sampling signal of a preset number of bits;
  • the fourth register receives the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the third register, and sends the third temporarily stored sampling signal to The second accumulator sends the first temporarily stored sampling signal and the second temporarily stored sampling signal to the first register;
  • the second accumulator accumulates the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to obtain a second accumulated signal
  • the third accumulator accumulates the first accumulated signal and the second accumulated signal to obtain a target accumulated signal.
  • the processor performs signal processing according to the target accumulated signal to obtain signal characteristics of the target accumulated signal.
  • the digital sampling signal of the preset number of digits at the current moment can be accumulated with the digital sampling signal of the preset number of digits at the later moment, so that the accumulated signal is amplified,
  • the number of digits of the accumulated signal is more than the preset number of digits, thereby increasing the number of digits of the digital sampling signal, so as to improve the resolution of the digital sampling signal, and finally achieve the beneficial effect of improving the accuracy of the sampling data of the oscilloscope.
  • FIG. 1 shows a schematic structural diagram of a signal processing system in an oscilloscope provided by an embodiment of the present invention
  • Figure 2 shows a schematic diagram of the ADC sampling process
  • FIG. 3 shows a schematic structural diagram of a signal processing system in an oscilloscope provided by another embodiment of the present invention.
  • FIG. 4 shows a schematic structural diagram of a signal processing system in an oscilloscope provided by another embodiment of the present invention.
  • FIG. 5 shows a schematic structural diagram of an oscilloscope provided by an embodiment of the present invention
  • FIG. 6 shows a schematic flowchart of a signal processing method in an oscilloscope provided by an embodiment of the present invention.
  • the analog-to-digital conversion process includes sampling, holding, quantization and encoding. Coding is to encode the quantized signal into binary code output.
  • the analog signal is sampled, the sampled value obtained by sampling is converted into a digital quantity, and the conversion result is given in a certain encoding form.
  • binary encoding such as 8-bit/10-bit/12-bit can be used.
  • Resolution refers to the change of the corresponding output analog quantity (voltage or current) when the least significant bit (LSB) of the input digital quantity changes. It reflects the minimum change value of the output analog quantity.
  • the resolution has a definite relationship with the number of bits of the input digital quantity (the sampled signal input at each moment), which can be expressed as FS/2 ⁇ n.
  • FS represents the full-scale input value, and n is the number of binary digits.
  • the more bits of the input digital quantity the higher the resolution.
  • the embodiment of the present invention is based on the above-mentioned principle, and by setting the connection relationship between multiple registers and accumulators, the digital sampling signals of preset digits at different times are added to increase the number of digits of the digital sampling signals at each time. Thereby, the resolution is improved, and finally the effect of improving the accuracy is obtained.
  • the sampling time interval of the oscilloscope is very small, it is generally in the picosecond level. For example, sampling is performed every 100ps, so the difference between the sampling signals at each moment is very small, so superimposing the signals will not cause the characteristics of the signals to change.
  • FIG. 1 shows a structural diagram of an embodiment of a signal processing system in an oscilloscope of the present invention, where the signal processing system is applied in an oscilloscope.
  • the signal processing system 100 includes a signal sampling module 111 and at least one register accumulation module.
  • the register accumulation module includes a first register 101 , a second register 102 and a first accumulator 105 .
  • the clock excitation signals of the first register 101 , the second register 102 and the first accumulator 105 are the same. in:
  • the signal sampling module 111 is configured to receive an analog signal, and generate a digital sampling signal according to the sampling of the analog signal.
  • Fig. 2 shows the ADC sampling process in the embodiment of the present invention.
  • the analog signal can be converted into a discrete digital sampling signal through ADC sampling, which can be represented by the encoding of preset digits ; For example, for 8-bit sampling precision, it can be represented by 8-bit encoding.
  • the acquisition process of digital sampling signal is real-time and continuous.
  • the first register 101 is used to sequentially receive the first temporarily stored sampling signal and the second temporarily stored sampling signal, and send the first temporarily stored sampling signal to the first accumulator 105 and the second register respectively 102, and send the second temporarily stored sampling signal to the first accumulator 105; wherein, the first temporarily stored sampling signal is all the preset number of bits generated by the signal sampling module at the first moment.
  • the digital sampling signal, the second temporarily stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at the second moment; the second moment is the adjacent time after the first moment moment. That is, after receiving the first temporarily stored sampling signal, the first register 101 sends it to the first accumulator 105 and the second register 102 .
  • the second temporarily stored sampling signal After a clock excitation signal, that is, at the second moment, after receiving the second temporarily stored sampling signal, the second temporarily stored sampling signal is sent to the first input port of the first accumulator 105. At this time, the first accumulator 105 The first temporarily stored sampling signal stored in the previous clock excitation signal is replaced with the second temporarily stored sampling signal of the current clock excitation signal.
  • the second register 102 is configured to receive the first temporarily stored sampling signal and send the first temporarily stored sampling signal to the first accumulator 105 .
  • the first temporarily stored sampling signal received by the second register 102 is sent to the second input port of the first accumulator 105 after a clock excitation signal.
  • the first accumulator 105 is configured to accumulate the first temporarily stored sampling signal and the second temporarily stored sampling signal to obtain a first accumulated signal. At this time, under the current clock excitation signal, the first accumulator 105 simultaneously receives the first temporarily stored sampling signal and the second temporarily stored sampling signal, and accumulates the two to obtain the first accumulated signal.
  • the first register 101 directly sends the second temporarily stored sampling signal to the first accumulator 105 , and at the same time, the first temporarily stored sampling signal passes through the second register 102 to temporarily store a clock excitation signal. After storing, it is sent to the first accumulator 105, which is equivalent to delaying the first temporarily stored sampling signal, so that the second temporarily stored sampling signal is superimposed on the first temporarily stored sampling signal, and the digital sampling signal (the first The first temporarily stored sampling signal generated at the moment and the second temporarily stored sampling signal generated at the second moment) are processed, so that the first temporarily stored sampling signal is amplified.
  • the temporarily stored sampling signal at each subsequent moment is superimposed with the signal of the next or previous moment, so that the first temporarily stored sampling signal is amplified.
  • the sampling accuracy of the ADC is equivalently improved ;
  • window filtering which effectively filters out high-frequency noise.
  • the oscilloscope further includes a processor. After the first accumulated signal is obtained, the oscilloscope is used to perform signal processing on the first accumulated signal to obtain the signal characteristic of the first accumulated signal.
  • the oscilloscope further includes a display module.
  • the display module is used for receiving and displaying the signal characteristics.
  • the digital sampling signal of the preset number of digits at the current moment can be accumulated with the digital sampling signal of the preset number of digits at the following moment, so that the accumulated signal increases , the number of digits of the accumulated signal is more than the preset number of digits, thereby increasing the number of digits of the digital sampling signal, so as to improve the resolution of the digital sampling signal, and finally achieve the beneficial effect of improving the accuracy of the sampling data of the oscilloscope.
  • FIG. 3 shows a schematic structural diagram of a signal processing system in an oscilloscope provided by another embodiment of the present invention.
  • the signal is amplified by a register accumulation module. That is, an overlay magnification is performed. Therefore, the signal sampling module 111 is directly connected to the input end D3 of the first register 101, the output end Q3 of the first register 101 is connected to the first input port of the first accumulator 105, and the output end Q3 of the first register 101 is also connected to the first input port of the first accumulator 105.
  • the input end D4 of the second register 102 is connected, the output port Q4 of the second register 102 is connected to the second input port of the first accumulator 105 , and the output end of the first accumulator is connected to the input end D7 of the seventh register 110 .
  • the clock signals of the first register 101 , the second register 102 , the first accumulator 105 and the seventh register 110 are the same.
  • the first accumulator 105 outputs the result through the first register 110 .
  • the signal sampling module 111 may be an 8-bit digital sampling signal
  • the first register 101 and the second register 102 are basic registers, and may be 9-bit registers, that is, when the rising edge of the clock CLK arrives, the first register 101 and the second register 102 are basic registers.
  • the register 101 and the second register 102 are respectively loaded with 9-bit data in parallel.
  • the first accumulator 105 may be a 9-bit accumulator.
  • the signal sampling module 111 outputs the first temporarily stored sampling signal as an 8-bit digital sampling signal generated at the first moment.
  • the signal sampling module 111 sends the first temporarily stored sampling signal generated at the first moment to the first register 101 in the first clock excitation signal, and the first register 101 receives the 8-bit signal when the rising edge of the first clock excitation signal reaches.
  • the first temporarily stored sampling signal is sent to the first accumulator 105 and the second register 102 when the rising edge of the second clock excitation signal arrives.
  • the first register 101 receives the second temporarily stored sampling signal, and the second register receives the first temporarily stored sampling signal.
  • the first register 101 receives the next temporarily stored sampling signal, and sends the second temporarily stored sampling signal to the first accumulator 105; the first accumulator 105 stores the second clock excitation signal
  • the received first temporarily stored sampling signal is output, while receiving the second temporarily stored sampling signal, the second register 102 receives the second temporarily stored sampling signal, and at the same time sends the first temporarily stored sampling signal to the first accumulator 105; the first The accumulator 105 receives the first temporarily stored sampling signal and the second temporarily stored sampling signal simultaneously with the third clock excitation signal, and performs accumulation calculation to obtain the first accumulated signal.
  • the first accumulated signal is output as the target accumulated signal. Among them, for the 8-bit binary digital sampling signal, after superposition, a 9-bit first accumulated signal is obtained.
  • the processor may be an FPGA.
  • the 8-bit sampling precision is to divide 2V into 256 parts (2 8 power), the average accuracy of each copy is 2V/256, which is 0.0078125V, which is the ordinary ADC sampling resolution. Therefore, after the superposition of the first accumulator 105, it becomes a 9-bit digital sampling signal, and the average precision of each part is 2V/516, which is 0.00390625V, that is, the resolution of the signal is equivalently enhanced.
  • the digital sampling signal of the preset number of digits at the current moment can be accumulated with the digital sampling signal of the preset number of digits at the following moment, so that the accumulated signal increases , the number of digits of the accumulated signal is more than the preset number of digits, thereby increasing the number of digits of the digital sampling signal, so as to improve the resolution of the digital sampling signal, and finally achieve the beneficial effect of improving the accuracy of the sampling data of the oscilloscope.
  • FIG. 4 shows a schematic structural diagram of a signal processing system in an oscilloscope according to another embodiment of the present invention.
  • signal amplification is performed through two register accumulation modules, that is, two superposition amplifications are performed. in,
  • the output end of the signal sampling module 111 is connected to the input end D1 of the third register 103 , the output end Q1 of the third register 103 is connected to the input end D2 of the fourth register and the first input end of the second accumulator 106 , the fourth register
  • the output terminal Q2 of 104 is respectively connected to the second input terminal of the second accumulator 106 and the input terminal D3 of the first register 101, and the output terminal Q3 of the first register 101 is respectively connected to the first signal input terminal of the first accumulator 105 and
  • the input terminal D4 of the second register 102 is connected, and the output terminal Q4 of the second register 102 is connected to the second signal input terminal of the first accumulator 105 .
  • the output end of the first accumulator 105 is connected to the input end D6 of the fifth register 108
  • the output end of the second accumulator 106 is connected to the input end D5 of the sixth register 107
  • the output terminal Q5 of 107 is connected to the first input terminal and the second input terminal of the third accumulator 109, respectively.
  • the output terminal of the third accumulator 109 is connected to the input terminal of the seventh register 110 .
  • the signal sampling module 111 may be an 8-bit digital sampling signal
  • the first register 101, the second register 102, the third register 103, the fourth register 104, the fifth register 108, the sixth register 107 and the seventh register 108 are both basic registers, which may be 9-bit registers, that is, when the rising edge of the clock CLK arrives, the registers are respectively loaded with 9-bit data in parallel.
  • the first accumulator 105, the second accumulator 106 and the third accumulator 109 may be 9-bit accumulators.
  • the signal sampling module 111 outputs the first temporarily stored sampling signal as an 8-bit digital sampling signal generated at the first moment.
  • the signal sampling module 111 sends the first temporarily stored sampling signal generated at the first moment to the third register 103 in the first clock excitation signal, and the third register 103 receives the 8-bit signal when the rising edge of the first clock excitation signal reaches.
  • the first temporarily stored sampling signal is sent to the second accumulator 106 and the fourth register 104 when the rising edge of the second clock excitation signal arrives.
  • the third register 103 receives the second temporarily stored sampling signal
  • the fourth register 104 receives the first temporarily stored sampling signal.
  • the third register 101 receives the third storage sampling signal, and sends the second temporary storage sampling signal to the second accumulator 106; the second accumulator 106 receives the second clock excitation signal
  • the received first temporarily stored sampling signal is output, while receiving the second temporarily stored sampling signal, the fourth register 104 receives the second temporarily stored sampling signal, and simultaneously sends the first temporarily stored sampling signal to the second accumulator 106 and the first register. 104.
  • the third register 103 receives the fourth temporarily stored sampling signal, and at the same time sends the third temporarily stored sampling signal to the second accumulator 106 and the fourth register 104 and the fourth register 104 respectively.
  • the second temporarily stored sampling signal is sent to the first register 101 , and the first register 101 sends the first temporarily stored sampling signal to the first accumulator 105 and the second register 102 respectively.
  • the third register 103 receives the next temporarily stored sampling signal, sends the fourth temporarily stored sampling signal to the second accumulator 106, and at the same time the fourth register 104 stores the third temporarily stored sampling signal
  • the signal is also sent to the second accumulator 106; at the same time, the first register 102 sends the second temporarily stored sampling signal to the first accumulator, and the second register 102 sends the first temporarily stored sampling signal to the first accumulator 105; the first The accumulator 105 accumulates the first temporarily stored sampling signal and the second temporarily stored sampling signal to obtain the first accumulated signal, while the second accumulator 106 accumulates the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to obtain the second. Accumulate signals.
  • the second accumulation signal is sent to the first input terminal of the third accumulator 109 through the sixth register 107
  • the first accumulation signal is sent to the second input terminal of the third accumulator 109 through the fifth register 108
  • the third accumulator 109 converts the The first accumulated signal and the second accumulated signal are accumulated to obtain the target accumulated signal output.
  • the signals at each moment are superimposed once, thereby amplifying the signal and improving the signal resolution.
  • a 10-bit target accumulated signal is obtained for the 8-bit binary digital sampling signal.
  • the target accumulated signal is temporarily stored in the seventh register 110, it is output to the data processing unit of the processor, and the data processing unit of the processor performs signal processing according to the first accumulated signal to obtain the signal characteristics of the target accumulated signal, wherein the Signal characteristics include amplitude, frequency, phase, spectrum and other characteristics.
  • the oscilloscope includes a processor, a first register 101, the second register 102, the third register 103, the fourth register 104, the first accumulator 105, and the second accumulator
  • Both the accumulator 106 and the third accumulator 109 are set in the processor, and can be implemented by using existing registers and accumulators in the processor.
  • the processor may be an FPGA.
  • the signal processing system further includes:
  • a detection module for calculating the amplitude of the digital sampling signal
  • a determination module configured to determine whether the digital sampling signal is lower than a preset threshold according to the amplitude, and send the first temporarily stored sampling signal to the third register when it is lower than the preset threshold.
  • the determining module is further configured to send the first temporarily stored sampling signal to the processor when the amplitude is higher than or equal to the preset threshold;
  • the processor performs signal processing according to the first temporarily stored sampled signal to obtain the signal characteristics of the target accumulated signal.
  • the embodiment of the present invention further determines whether the resolution or signal strength of the digital sampling signal is too low by setting the detection module and the determination module.
  • the signal amplification and noise filtering are performed by the register accumulation module of the embodiment of the present invention to improve the resolution; when it is within the normal range, the first temporarily stored sampling signal can be directly sent to the data processing unit of the processor. Signal processing is performed according to the first accumulated signal to obtain the signal characteristic of the target accumulated signal.
  • the digital sampling signal at the current moment and the digital sampling signal at the following moment can be accumulated, thereby realizing the effect of amplifying the digital sampling signal and increasing the digital sampling signal at each moment.
  • the beneficial effect of improving the accuracy of the sampling data of the oscilloscope is realized.
  • FIG. 5 shows a schematic structural diagram of an embodiment of an oscilloscope of the present invention.
  • the oscilloscope 10 includes the above-mentioned signal processing system 100 .
  • the signal processing system 100 in the oscilloscope 10 according to the embodiment of the present invention has all the features of the above-mentioned embodiments, and details are not described herein again.
  • the digital sampling signal at the current moment and the digital sampling signal at the following moment can be accumulated, thereby realizing the effect of amplifying the digital sampling signal, and finally improving the sampling data of the oscilloscope.
  • the beneficial effect of precision is achieved.
  • FIG. 6 shows a schematic flowchart of an embodiment of a signal processing method in an oscilloscope of the present invention.
  • the signal processing method is applied to an oscilloscope.
  • the signal processing method of the embodiment of the present invention is based on the signal processing system of the above embodiment. As shown in Figure 6, the signal processing method includes:
  • Step 110 The signal sampling module receives the analog signal and generates a digital sampling signal according to the analog signal sampling.
  • Step 120 The first register sequentially receives the first temporarily stored sampling signal and the second temporarily stored sampling signal, sends the first temporarily stored sampling signal to the first accumulator and the second register, respectively, and sends the second temporarily stored sampling signal to the first accumulator and the second register respectively.
  • the stored sampling signal is sent to the first accumulator; wherein, the first temporarily stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at the first moment, and the second temporary sampling signal is The stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a second moment; the second moment is an adjacent moment after the first moment.
  • Step 130 The second register receives the first temporarily stored sampling signal, and sends the first temporarily stored sampling signal to the first accumulator.
  • Step 140 The first accumulator accumulates the first temporarily stored sampling signal and the second temporarily stored sampling signal to obtain a first accumulated signal.
  • the third register sequentially receives the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the signal sampling module, and sends the fourth temporarily stored sampling signal to
  • the second accumulator sends the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to the fourth register;
  • the third temporarily stored sampling signal is the digital sampling signal of a preset number of bits generated by the signal sampling module at the third moment
  • the fourth temporarily stored sampling signal is the signal generated by the signal sampling module at the fourth moment.
  • the digital sampled signal of a preset number of bits.
  • the fourth register receives the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the third register, and sends the third temporarily stored sampling signal to The second accumulator sends the first temporarily stored sampling signal and the second temporarily stored sampling signal to the first register.
  • the second accumulator accumulates the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to obtain a second accumulated signal.
  • the third accumulator accumulates the first accumulated signal and the second accumulated signal to obtain a target accumulated signal.
  • the digital sampling signal at the current moment and the digital sampling signal at the following moment can be accumulated, thereby realizing the effect of amplifying the digital sampling signal, and finally improving the sampling data of the oscilloscope.
  • the beneficial effect of precision is achieved.
  • modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment.
  • the modules or units or components in the embodiments may be combined into one module or unit or component, and they may be divided into multiple sub-modules or sub-units or sub-assemblies. All features disclosed in this specification (including accompanying claims, abstract and drawings) and any method so disclosed may be employed in any combination, unless at least some of such features and/or procedures or elements are mutually exclusive. All processes or units of equipment are combined.
  • Each feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

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Abstract

The embodiments of the present invention relate to the technical field of oscilloscopes. Disclosed is a signal processing system in an oscilloscope. The signal processing system comprises a signal sampling module and at least one register and accumulation module, wherein the register and accumulation module comprises a first register, a second register and a first accumulator; the signal sampling module is used for receiving an analog signal and performing sampling according to the analog signal to generate a digital sampling signal; the first register is used for sequentially receiving a first temporarily stored sampling signal and a second temporarily stored sampling signal, for sending the first temporarily stored sampling signal to the first accumulator and the second register respectively, and for sending the second temporarily stored sampling signal to the first accumulator; the second register is used for receiving the first temporarily stored sampling signal and sending the first temporarily stored sampling signal to the first accumulator; and the first accumulator is used for accumulating the first temporarily stored sampling signal and the second temporarily stored sampling signal, so as to obtain a first accumulated signal. In this way, by means of the embodiments of the present invention, the beneficial effect of enhancing signal resolution is realized.

Description

示波器中的信号处理系统、示波器及信号处理方法Signal processing system in oscilloscope, oscilloscope and signal processing method
本申请要求于2020年12月15日提交中国专利局、申请号为202011478023.5、申请名称为“示波器中的信号处理系统、示波器及信号处理方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application with the application number 202011478023.5 and the application title "Signal Processing System in Oscilloscope, Oscilloscope and Signal Processing Method", which was submitted to the Chinese Patent Office on December 15, 2020, the entire contents of which are by reference Incorporated in this application.
技术领域technical field
本申请涉及示波器技术领域，具体涉及一种示波器中的信号处理系统、示波器及示波器中的信号处理方法。The present application relates to the technical field of oscilloscopes, and in particular to a signal processing system in an oscilloscope, an oscilloscope and a signal processing method in the oscilloscope.
背景技术Background technique
目前，随着汽车技术不断发展汽车电气系统越来越多，一旦系统出现问题，问题排查是首先要解决的。对信号的测量是发现问题的关键，示波器是主要的测量工具。示波器可以测量信号的幅度，频度，相位，频谱等信号的特征。示波器的存储深度越深，一次捕获的数据就越完整，就更容易通过对信号的特征分析，判断信号是否正常。At present, with the continuous development of automotive technology, there are more and more automotive electrical systems. Once a problem occurs in the system, troubleshooting is the first thing to solve. The measurement of the signal is the key to finding the problem, and the oscilloscope is the main measurement tool. Oscilloscopes can measure signal characteristics such as amplitude, frequency, phase, spectrum, etc. The deeper the storage depth of the oscilloscope, the more complete the data captured at one time, and it is easier to judge whether the signal is normal by analyzing the characteristics of the signal.
现有的示波器在进行信号分析时，首先需要对模拟信号进行抓取，再通过ADC采样进行模数信号转换，ADC采样分辨率越高理论上信号的量化失真就越低，信噪声比就越高。然而，目前示波器的示波器，其分辨率一般是固定的，精度也是固定的，这并不适用于信号较弱的场景。When the existing oscilloscope performs signal analysis, it is necessary to first capture the analog signal, and then perform analog-to-digital signal conversion through ADC sampling. The higher the ADC sampling resolution, the lower the theoretical signal quantization distortion and the higher the signal-to-noise ratio. high. However, the oscilloscope of the current oscilloscope generally has a fixed resolution and a fixed precision, which is not suitable for scenarios with weak signals.
发明内容SUMMARY OF THE INVENTION
鉴于上述问题，本发明实施例提供了一种示波器中的信号处理系统、示波器及示波器中的信号处理方法，用于解决现有技术中存在的示波器采样数据精度低的问题。In view of the above problems, embodiments of the present invention provide a signal processing system in an oscilloscope, an oscilloscope, and a signal processing method in the oscilloscope, which are used to solve the problem of low sampling data accuracy of the oscilloscope in the prior art.
根据本发明实施例的一个方面，提供了一种示波器中的信号处理系统，应用于示波器中，所述信号处理系统包括信号采样模块及至少一个寄存累加模块；所述寄存累加模块包括第一寄存器、第二寄存器及第一累加器；According to an aspect of the embodiments of the present invention, a signal processing system in an oscilloscope is provided, which is applied in an oscilloscope, the signal processing system includes a signal sampling module and at least one register accumulation module; the register accumulation module includes a first register , the second register and the first accumulator;
所述信号采样模块，用于接收模拟信号并根据所述模拟信号采样生成数字采样信号；the signal sampling module, configured to receive an analog signal and generate a digital sampling signal according to the sampling of the analog signal;
所述第一寄存器，用于依次接收第一暂存采样信号及第二暂存采样信号，将所述第一暂存采样信号分别发送给所述第一累加器及所述第二寄存器，并将所述第二暂存采样信号发送给所述第一累加器；其中，所述第一暂存采样信号为所述信号采样模块在第一时刻生成的预设位数的所述数字采样信号，所述第二暂存采样信号为所述信号采样模块在第二时刻生成的预设位数的所述数字采样信号；所述第二时刻为所述第一时刻之后相邻的时刻；The first register is used to sequentially receive the first temporarily stored sampling signal and the second temporarily stored sampling signal, send the first temporarily stored sampling signal to the first accumulator and the second register respectively, and Send the second temporarily stored sampling signal to the first accumulator; wherein, the first temporarily stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at the first moment , the second temporarily stored sampling signal is the digital sampling signal of a preset number of digits generated by the signal sampling module at a second moment; the second moment is an adjacent moment after the first moment;
所述第二寄存器，用于接收所述第一暂存采样信号，并将所述第一暂存采样信号发送给所述第一累加器；the second register, configured to receive the first temporarily stored sampling signal, and send the first temporarily stored sampling signal to the first accumulator;
所述第一累加器，用于将所述第一暂存采样信号与所述第二暂存采样信号进行累加，得到第一累加信号。The first accumulator is configured to accumulate the first temporarily stored sampling signal and the second temporarily stored sampling signal to obtain a first accumulated signal.
在一种可选的方式中，所述信号处理系统还包括：第三寄存器、第四寄存器、第二累加器及第三累加器；In an optional manner, the signal processing system further includes: a third register, a fourth register, a second accumulator, and a third accumulator;
所述第三寄存器，用于依次接收所述信号采样模块发送的第一暂存采样信号、第二暂存采样信号、第三暂存采样信号及第四暂存采样信号，并将第四暂存采样信号发送给所述第二累加器，将所述第一暂存采样信号、所述第二暂存采样信号、所述第三暂存采样信号及所述第四暂存采样信号发送给所述第四寄存器；其中，所述第三暂存采样信号为所述信号采样模块在第三时刻生成的预设位数的所述数字采样信号，所述第四暂存采样信号为所述信号采样模块在第四时刻生成的预设位数的所述数字采样信号；The third register is used to sequentially receive the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the signal sampling module, and store the fourth temporarily stored sampling signal. The storage sampling signal is sent to the second accumulator, and the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal are sent to the the fourth register; wherein, the third temporarily stored sampling signal is the digital sampling signal with a preset number of digits generated by the signal sampling module at the third moment, and the fourth temporarily stored sampling signal is the the digital sampling signal of the preset number of bits generated by the signal sampling module at the fourth moment;
所述第四寄存器，用于接收所述第三寄存器发送的第一暂存采样信号、第二暂存采样信号、第三暂存采样信号及第四暂存采样信号，将所述第三暂存采样信号发送给所述第二累加器，将所述第一暂存采样信号及第二暂存采样信号发送给所述第一寄存器；The fourth register is used to receive the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the third register, and the third temporary storage sampling signal sending the stored sampling signal to the second accumulator, and sending the first temporarily stored sampling signal and the second temporarily stored sampling signal to the first register;
所述第二累加器，用于将所述第三暂存采样信号及所述第四暂存采样信号进行累加，得到第二累加信号；the second accumulator for accumulating the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to obtain a second accumulated signal;
所述第三累加器，用于将所述第一累加信号及所述第二累加信号进行累加，得到目标累加信号。The third accumulator is used for accumulating the first accumulating signal and the second accumulating signal to obtain a target accumulating signal.
在一种可选的方式中，所述示波器包括处理器，所述第一寄存器、所述第二寄存器、所述第三寄存器、所述第四寄存器、所述第一累加器、所述第二累加器及所述第三累加器均设置于所述处理器中；In an optional manner, the oscilloscope includes a processor, the first register, the second register, the third register, the fourth register, the first accumulator, the first Both the two accumulators and the third accumulator are arranged in the processor;
所述处理器，还用于根据所述目标累加信号进行信号处理，得到目标累加信号的信号特征。The processor is further configured to perform signal processing according to the target accumulated signal to obtain signal characteristics of the target accumulated signal.
在一种可选的方式中，所述第一寄存器、第二寄存器、所述第三寄存器、所述第四寄存器、所述第一累加器、所述第二累加器及所述第三累加器的时钟激励信号相同。In an optional manner, the first register, the second register, the third register, the fourth register, the first accumulator, the second accumulator, and the third accumulator The clock excitation signal of the device is the same.
在一种可选的方式中，还包括：In an optional manner, it also includes:
检测模块，用于计算所述数字采样信号的幅值；a detection module for calculating the amplitude of the digital sampling signal;
确定模块，用于根据所述幅值确定所述数字采样信号是否低于预设阈值，当低于所述预设阈值时，将所述第一暂存采样信号发送给所述第三寄存器。A determination module, configured to determine whether the digital sampling signal is lower than a preset threshold according to the amplitude, and send the first temporarily stored sampling signal to the third register when it is lower than the preset threshold.
在一种可选的方式中，所述确定模块还用于当所述幅值高于等于所述预设阈值时，将所述第一暂存采样信号发送给所述处理器；In an optional manner, the determining module is further configured to send the first temporarily stored sampling signal to the processor when the amplitude is higher than or equal to the preset threshold;
所述处理器根据所述第一暂存采样信号进行信号处理，得到目标累加信号的信号特征。The processor performs signal processing according to the first temporarily stored sampling signal to obtain the signal characteristic of the target accumulated signal.
根据本发明实施例的另一方面，提供了一种示波器，所述示波器包括上述的信号处理系统。According to another aspect of the embodiments of the present invention, an oscilloscope is provided, and the oscilloscope includes the above-mentioned signal processing system.
根据本发明实施例的另一方面，提供了一种示波器中的信号处理方法，包括：According to another aspect of the embodiments of the present invention, a signal processing method in an oscilloscope is provided, including:
包括以下步骤：Include the following steps:
信号采样模块接收模拟信号并根据所述模拟信号采样生成数字采样信号；The signal sampling module receives the analog signal and generates a digital sampling signal according to the sampling of the analog signal;
第一寄存器依次接收第一暂存采样信号及第二暂存采样信号，将所述第一暂存采样信号分别发送给第一累加器及第二寄存器，并将所述第二暂存采样信号发送给所述第一累加器；其中，所述第一暂存采样信号为所述信号采样模块在第一时刻生成的预设位数的所述数字采样信号，所述第二暂存采样信号为所述信号采样模块在第二时刻生成的预设位数的所述数字采样信号；所述第二时刻为所述第一时刻之后相邻的时刻；The first register sequentially receives the first temporarily stored sampling signal and the second temporarily stored sampling signal, sends the first temporarily stored sampling signal to the first accumulator and the second register respectively, and sends the second temporarily stored sampling signal to the first accumulator and the second register respectively. sent to the first accumulator; wherein, the first temporarily stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at the first moment, and the second temporarily stored sampling signal is the digital sampling signal of a preset number of digits generated by the signal sampling module at a second moment; the second moment is an adjacent moment after the first moment;
第二寄存器接收所述第一暂存采样信号，并将所述第一暂存采样信号发送给所述第一累加器；The second register receives the first temporarily stored sampling signal, and sends the first temporarily stored sampling signal to the first accumulator;
第一累加器将所述第一暂存采样信号与所述第二暂存采样信号进行累加，得到第一累加信号。The first accumulator accumulates the first temporarily stored sampling signal and the second temporarily stored sampling signal to obtain a first accumulated signal.
在一种可选的方式中，还包括以下步骤：In an optional manner, the following steps are also included:
第三寄存器依次接收所述信号采样模块发送的第一暂存采样信号、第二暂存采样信号、第三暂存采样信号及第四暂存采样信号，并将第四暂存采样信号发送给第二累加器，将所述第一暂存采样信号、所述第二暂存采样信号、所述第三暂存采样信号及所述第四暂存采样信号发送给第四寄存器；其中，所述第三暂存采样信号为所述信号采样模块在第三时刻生成的预设位数的所述数字采样信号，所述第四暂存采样信号为所述信号采样模块在第四时刻生成的预设位数的所述数字采样信号；The third register sequentially receives the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the signal sampling module, and sends the fourth temporarily stored sampling signal to The second accumulator sends the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to the fourth register; The third temporarily stored sampling signal is the digital sampling signal of a preset number of bits generated by the signal sampling module at the third moment, and the fourth temporarily stored sampling signal is the signal generated by the signal sampling module at the fourth moment. the digital sampling signal of a preset number of bits;
第四寄存器接收所述第三寄存器发送的第一暂存采样信号、第二暂存采样信号、第三暂存采样信号及第四暂存采样信号，将所述第三暂存采样信号发送给所述第二累加器，将所述第一暂存采样信号及第二暂存采样信号发送给所述第一寄存器；The fourth register receives the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the third register, and sends the third temporarily stored sampling signal to The second accumulator sends the first temporarily stored sampling signal and the second temporarily stored sampling signal to the first register;
所述第二累加器将所述第三暂存采样信号及所述第四暂存采样信号进行累加，得到第二累加信号；The second accumulator accumulates the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to obtain a second accumulated signal;
所述第三累加器将所述第一累加信号及所述第二累加信号进行累加，得到目标累加信号。The third accumulator accumulates the first accumulated signal and the second accumulated signal to obtain a target accumulated signal.
在一种可选的方式中，处理器根据所述目标累加信号进行信号处理，得到目标累加信号的信号特征。In an optional manner, the processor performs signal processing according to the target accumulated signal to obtain signal characteristics of the target accumulated signal.
本发明实施例通过设置级联的寄存器及累加器，能够使得当前时刻的预设位数的数字采样信号与后面时刻的预设位数的数字采样信号进行累加，从而使得累加后的信号放大，累加后的信号的位数多于预设位数，从而增加了数字采样信号的位数，以提高数字采样信号的分辨率，最终实现了提高示波器采样数据的精度的有益效果。In the embodiment of the present invention, by setting cascaded registers and accumulators, the digital sampling signal of the preset number of digits at the current moment can be accumulated with the digital sampling signal of the preset number of digits at the later moment, so that the accumulated signal is amplified, The number of digits of the accumulated signal is more than the preset number of digits, thereby increasing the number of digits of the digital sampling signal, so as to improve the resolution of the digital sampling signal, and finally achieve the beneficial effect of improving the accuracy of the sampling data of the oscilloscope.
进一步地，通过设置检测模块及确定模块，使得能够针对不同的采样信号 进行灵活调整。Further, by setting the detection module and the determination module, it is possible to flexibly adjust for different sampling signals.
上述说明仅是本发明实施例技术方案的概述，为了能够更清楚了解本发明实施例的技术手段，而可依照说明书的内容予以实施，并且为了让本发明实施例的上述和其它目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。The above description is only an overview of the technical solutions of the embodiments of the present invention. In order to understand the technical means of the embodiments of the present invention more clearly, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and The advantages can be more clearly understood, and the following specific embodiments of the present invention are given.
附图说明Description of drawings
附图仅用于示出实施方式，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：The drawings are only used to illustrate the embodiments and are not considered to be limiting of the present invention. Also, the same components are denoted by the same reference numerals throughout the drawings. In the attached image:
图1示出了本发明实施例提供的示波器中的信号处理系统的结构示意图；1 shows a schematic structural diagram of a signal processing system in an oscilloscope provided by an embodiment of the present invention;
图2示出了ADC采样过程示意图；Figure 2 shows a schematic diagram of the ADC sampling process;
图3示出了本发明另一实施例提供的示波器中的信号处理系统的结构示意图；3 shows a schematic structural diagram of a signal processing system in an oscilloscope provided by another embodiment of the present invention;
图4示出了本发明又一实施例提供的示波器中的信号处理系统的结构示意图；4 shows a schematic structural diagram of a signal processing system in an oscilloscope provided by another embodiment of the present invention;
图5示出了本发明实施例提供的示波器的结构示意图；5 shows a schematic structural diagram of an oscilloscope provided by an embodiment of the present invention;
图6示出了本发明实施例提供的示波器中的信号处理方法的流程示意图。FIG. 6 shows a schematic flowchart of a signal processing method in an oscilloscope provided by an embodiment of the present invention.
具体实施方式Detailed ways
下面将参照附图更详细地描述本发明的示例性实施例。虽然附图中显示了本发明的示例性实施例，然而应当理解，可以以各种形式实现本发明而不应被这里阐述的实施例所限制。Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited by the embodiments set forth herein.
首先，对于数字采样信号的采集中涉及的概念进行解释：First, the concepts involved in the acquisition of digital sampling signals are explained:
数字量的位数：模数转换过程包括采样、保持、量化和编码。编码是将量化后的信号编码成二进制代码输出。对模拟信号进行取样，将取样得到的取样值转换成数字量，并按一定的编码形式给出转换结果。如可用8位/10位/12位等二进制编码。Number of bits of digital quantity: The analog-to-digital conversion process includes sampling, holding, quantization and encoding. Coding is to encode the quantized signal into binary code output. The analog signal is sampled, the sampled value obtained by sampling is converted into a digital quantity, and the conversion result is given in a certain encoding form. For example, binary encoding such as 8-bit/10-bit/12-bit can be used.
分辨率是指输入数字量的最低有效位(LSB)发生变化时，所对应的输出模拟量(电压或电流)的变化量。它反映了输出模拟量的最小变化值。分辨率与输入数字量(每一时刻输入的采样信号)的位数有确定的关系，可以表示成FS/2^n。FS表示满量程输入值，n为二进制位数。对于5V的满量程，采用8位的DAC时，分辨率为5V/256＝19.5mV；当采用12位的DAC时，分辨率则为5V/4096＝1.22mV。显然，输入数字量的位数越多分辨率就越高。Resolution refers to the change of the corresponding output analog quantity (voltage or current) when the least significant bit (LSB) of the input digital quantity changes. It reflects the minimum change value of the output analog quantity. The resolution has a definite relationship with the number of bits of the input digital quantity (the sampled signal input at each moment), which can be expressed as FS/2^n. FS represents the full-scale input value, and n is the number of binary digits. For the full scale of 5V, when using an 8-bit DAC, the resolution is 5V/256=19.5mV; when using a 12-bit DAC, the resolution is 5V/4096=1.22mV. Obviously, the more bits of the input digital quantity, the higher the resolution.
因此，当输入数字量的位数增多时，分辨率会提高，对应于影响精度的量化误差会减小。Therefore, when the number of bits of the input digital quantity is increased, the resolution is improved, and the quantization error corresponding to the impact on the precision is reduced.
本发明实施例正是基于上述原理，通过设置多个寄存器及累加器的连接关系，将不同时刻的预设位数的数字采样信号进行相加，以增加各个时刻的数字 采样信号的位数，从而提高分辨率，最终得到提高精度的效果。由于示波器的采样时间间隔非常小，一般在皮秒级别。如每100ps进行一次采样，因此每一个时刻的采样信号之前的差别非常小，因此叠加信号不会导致信号的特征改变。The embodiment of the present invention is based on the above-mentioned principle, and by setting the connection relationship between multiple registers and accumulators, the digital sampling signals of preset digits at different times are added to increase the number of digits of the digital sampling signals at each time. Thereby, the resolution is improved, and finally the effect of improving the accuracy is obtained. Since the sampling time interval of the oscilloscope is very small, it is generally in the picosecond level. For example, sampling is performed every 100ps, so the difference between the sampling signals at each moment is very small, so superimposing the signals will not cause the characteristics of the signals to change.
图1示出了本发明示波器中的信号处理系统实施例的结构图，该信号处理系统应用于示波器中。如图1所示，该信号处理系统100包括信号采样模块111及至少一个寄存累加模块。所述寄存累加模块包括第一寄存器101、第二寄存器102及第一累加器105。本发明实施例中，第一寄存器101、第二寄存器102及第一累加器105的时钟激励信号相同。其中：FIG. 1 shows a structural diagram of an embodiment of a signal processing system in an oscilloscope of the present invention, where the signal processing system is applied in an oscilloscope. As shown in FIG. 1 , the signal processing system 100 includes a signal sampling module 111 and at least one register accumulation module. The register accumulation module includes a first register 101 , a second register 102 and a first accumulator 105 . In this embodiment of the present invention, the clock excitation signals of the first register 101 , the second register 102 and the first accumulator 105 are the same. in:
所述信号采样模块111，用于接收模拟信号，并根据所述模拟信号采样生成数字采样信号。图2示出了本发明实施例中ADC采样过程，对于被测对象所产生的模拟信号，通过ADC采样可以将该模拟信号变为离散化的数字采样信号，可以通过预设位数的编码表示；如，对于8位采样精度，可以通过8位编码表示。数字采样信号的采集过程是实时且连续的。The signal sampling module 111 is configured to receive an analog signal, and generate a digital sampling signal according to the sampling of the analog signal. Fig. 2 shows the ADC sampling process in the embodiment of the present invention. For the analog signal generated by the measured object, the analog signal can be converted into a discrete digital sampling signal through ADC sampling, which can be represented by the encoding of preset digits ; For example, for 8-bit sampling precision, it can be represented by 8-bit encoding. The acquisition process of digital sampling signal is real-time and continuous.
所述第一寄存器101，用于依次接收第一暂存采样信号及第二暂存采样信号，将所述第一暂存采样信号分别发送给所述第一累加器105及所述第二寄存器102，并将所述第二暂存采样信号发送给所述第一累加器105；其中，所述第一暂存采样信号为所述信号采样模块在第一时刻生成的预设位数的所述数字采样信号，所述第二暂存采样信号为所述信号采样模块在第二时刻生成的预设位数的所述数字采样信号；所述第二时刻为所述第一时刻之后相邻的时刻。也即：第一寄存器101在接收到第一暂存采样信号后，将其发送给第一累加器105及第二寄存器102。经过一个时钟激励信号后，也即第二时刻，接收到第二暂存采样信号后，将第二暂存采样信号发送给第一累加器105的第一输入端口，此时第一累加器105在上一个时钟激励信号存储的第一暂存采样信号被替换为当前时钟激励信号的第二暂存采样信号。The first register 101 is used to sequentially receive the first temporarily stored sampling signal and the second temporarily stored sampling signal, and send the first temporarily stored sampling signal to the first accumulator 105 and the second register respectively 102, and send the second temporarily stored sampling signal to the first accumulator 105; wherein, the first temporarily stored sampling signal is all the preset number of bits generated by the signal sampling module at the first moment. The digital sampling signal, the second temporarily stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at the second moment; the second moment is the adjacent time after the first moment moment. That is, after receiving the first temporarily stored sampling signal, the first register 101 sends it to the first accumulator 105 and the second register 102 . After a clock excitation signal, that is, at the second moment, after receiving the second temporarily stored sampling signal, the second temporarily stored sampling signal is sent to the first input port of the first accumulator 105. At this time, the first accumulator 105 The first temporarily stored sampling signal stored in the previous clock excitation signal is replaced with the second temporarily stored sampling signal of the current clock excitation signal.
所述第二寄存器102，用于接收所述第一暂存采样信号，并将所述第一暂存采样信号发送给所述第一累加器105。第二寄存器102接收到的第一暂存采样信号，经过一个时钟激励信号后，将其发送至第一累加器105的第二输入端口。The second register 102 is configured to receive the first temporarily stored sampling signal and send the first temporarily stored sampling signal to the first accumulator 105 . The first temporarily stored sampling signal received by the second register 102 is sent to the second input port of the first accumulator 105 after a clock excitation signal.
所述第一累加器105，用于将所述第一暂存采样信号与所述第二暂存采样信号进行累加，得到第一累加信号。此时，在当前时钟激励信号下，第一累加器105同时接收到第一暂存采样信号及第二暂存采样信号，并将二者进行累加，从而得到第一累加信号。The first accumulator 105 is configured to accumulate the first temporarily stored sampling signal and the second temporarily stored sampling signal to obtain a first accumulated signal. At this time, under the current clock excitation signal, the first accumulator 105 simultaneously receives the first temporarily stored sampling signal and the second temporarily stored sampling signal, and accumulates the two to obtain the first accumulated signal.
本发明实施例通过设置寄存累加模块，第一寄存器101通过将第二暂存采样信号直接发送至第一累加器105，同时将第一暂存采样信号经过第二寄存器102一个时钟激励信号的暂存后，再发送至第一累加器105，相当于对第一暂存采样信号进行了时延，使得第一暂存采样信号叠加了第二暂存采样信号，通过对数字采样信号(第一时刻产生的第一暂存采样信号及第二时刻产生的第二 暂存采样信号)进行处理，从而使得第一暂存采样信号被放大。同样地，后续各个时刻的暂存采样信号均叠加了下一时刻或上一时刻的信号，从而使得第一暂存采样信号被放大，通过这样的方式，一方面等效提高了ADC的采样精度；另一方面，等效为窗口滤波，有效滤除了高频噪声。In this embodiment of the present invention, by setting a register accumulation module, the first register 101 directly sends the second temporarily stored sampling signal to the first accumulator 105 , and at the same time, the first temporarily stored sampling signal passes through the second register 102 to temporarily store a clock excitation signal. After storing, it is sent to the first accumulator 105, which is equivalent to delaying the first temporarily stored sampling signal, so that the second temporarily stored sampling signal is superimposed on the first temporarily stored sampling signal, and the digital sampling signal (the first The first temporarily stored sampling signal generated at the moment and the second temporarily stored sampling signal generated at the second moment) are processed, so that the first temporarily stored sampling signal is amplified. Similarly, the temporarily stored sampling signal at each subsequent moment is superimposed with the signal of the next or previous moment, so that the first temporarily stored sampling signal is amplified. In this way, on the one hand, the sampling accuracy of the ADC is equivalently improved ; On the other hand, it is equivalent to window filtering, which effectively filters out high-frequency noise.
本发明实施例中，示波器还包括处理器。在得到第一累加信号后，所述示波器用于将所述第一累加信号进行信号处理，得到第一累加信号的信号特征。In this embodiment of the present invention, the oscilloscope further includes a processor. After the first accumulated signal is obtained, the oscilloscope is used to perform signal processing on the first accumulated signal to obtain the signal characteristic of the first accumulated signal.
本发明实施例中，所述示波器还包括显示模块。所述显示模块，用于接收所述信号特征，并进行显示。In the embodiment of the present invention, the oscilloscope further includes a display module. The display module is used for receiving and displaying the signal characteristics.
本发明实施例通过设置级联的寄存器及累加器，能够使得当前时刻的预设位数的数字采样信号与后面时刻的预设位数的数字采样信号进行累加，从而使得累加后的信号增大，累加后的信号的位数多于预设位数，从而增加了数字采样信号的位数，以提高数字采样信号的分辨率，最终实现了提高示波器采样数据的精度的有益效果。In the embodiment of the present invention, by setting cascaded registers and accumulators, the digital sampling signal of the preset number of digits at the current moment can be accumulated with the digital sampling signal of the preset number of digits at the following moment, so that the accumulated signal increases , the number of digits of the accumulated signal is more than the preset number of digits, thereby increasing the number of digits of the digital sampling signal, so as to improve the resolution of the digital sampling signal, and finally achieve the beneficial effect of improving the accuracy of the sampling data of the oscilloscope.
图3示出了本发明另一实施例提供的示波器中的信号处理系统的结构示意图。本发明实施例中，通过一个寄存累加模块进行信号的放大。也即进行一次叠加放大。因此，信号采样模块111直接与第一寄存器101的输入端D3连接，第一寄存器101的输出端Q3与第一累加器105的第一输入端口连接，第一寄存器101的输出端Q3还与第二寄存器102的输入端D4连接，第二寄存器102的输出端口Q4与第一累加器105的第二输入端口连接，第一累加器的输出端与第七寄存器110的输入端D7连接。第一寄存器101、第二寄存器102、第一累加器105及第七寄存器110的时钟信号相同。第一累加器105通过第一寄存器110将结果输出。FIG. 3 shows a schematic structural diagram of a signal processing system in an oscilloscope provided by another embodiment of the present invention. In the embodiment of the present invention, the signal is amplified by a register accumulation module. That is, an overlay magnification is performed. Therefore, the signal sampling module 111 is directly connected to the input end D3 of the first register 101, the output end Q3 of the first register 101 is connected to the first input port of the first accumulator 105, and the output end Q3 of the first register 101 is also connected to the first input port of the first accumulator 105. The input end D4 of the second register 102 is connected, the output port Q4 of the second register 102 is connected to the second input port of the first accumulator 105 , and the output end of the first accumulator is connected to the input end D7 of the seventh register 110 . The clock signals of the first register 101 , the second register 102 , the first accumulator 105 and the seventh register 110 are the same. The first accumulator 105 outputs the result through the first register 110 .
本发明实施例中，信号采样模块111可以是8位数字采样信号，第一寄存器101及第二寄存器102为基础寄存器，可以是9位寄存器，也即：当时钟CLK上升沿到达时，第一寄存器101及第二寄存器102分别并行置入9位数据。第一累加器105可以是9位累加器。信号采样模块111输出第一暂存采样信号为第一时刻产生的8位数字采样信号。信号采样模块111将第一时刻产生的第一暂存采样信号在第一时钟激励信号内发送给第一寄存器101，第一寄存器101在第一时钟激励信号上升沿达到时，接收到该8位的第一暂存采样信号，并在第二时钟激励信号上升沿到达时，将该第一暂存采样信号发送给第一累加器105及第二寄存器102。在第二时钟激励信号上升沿到达时，第一寄存器101接收第二暂存采样信号，第二寄存器接收第一暂存采样信号。在第三时钟激励信号上升沿到达时，第一寄存器101接收下一暂存采样信号，并将第二暂存采样信号发送给第一累加器105；第一累加器105将第二时钟激励信号接收到的第一暂存采样信号输出，同时接收第二暂存采样信号，第二寄存器102接收第二暂存采样信号，同时将第一暂存采样信号发送给第一累加器105；第一累加器105在第三时钟激励信号同时接收到第一暂存采样信号及第二暂存采样信号，并进行累加计算，得到第一累加信号。本发明实施例中，将第一累加信号 作为目标累加信号输出。其中，对于8位二进制数字采样信号，经过叠加后，得到9位的第一累加信号。In this embodiment of the present invention, the signal sampling module 111 may be an 8-bit digital sampling signal, the first register 101 and the second register 102 are basic registers, and may be 9-bit registers, that is, when the rising edge of the clock CLK arrives, the first register 101 and the second register 102 are basic registers. The register 101 and the second register 102 are respectively loaded with 9-bit data in parallel. The first accumulator 105 may be a 9-bit accumulator. The signal sampling module 111 outputs the first temporarily stored sampling signal as an 8-bit digital sampling signal generated at the first moment. The signal sampling module 111 sends the first temporarily stored sampling signal generated at the first moment to the first register 101 in the first clock excitation signal, and the first register 101 receives the 8-bit signal when the rising edge of the first clock excitation signal reaches. The first temporarily stored sampling signal is sent to the first accumulator 105 and the second register 102 when the rising edge of the second clock excitation signal arrives. When the rising edge of the second clock excitation signal arrives, the first register 101 receives the second temporarily stored sampling signal, and the second register receives the first temporarily stored sampling signal. When the rising edge of the third clock excitation signal arrives, the first register 101 receives the next temporarily stored sampling signal, and sends the second temporarily stored sampling signal to the first accumulator 105; the first accumulator 105 stores the second clock excitation signal The received first temporarily stored sampling signal is output, while receiving the second temporarily stored sampling signal, the second register 102 receives the second temporarily stored sampling signal, and at the same time sends the first temporarily stored sampling signal to the first accumulator 105; the first The accumulator 105 receives the first temporarily stored sampling signal and the second temporarily stored sampling signal simultaneously with the third clock excitation signal, and performs accumulation calculation to obtain the first accumulated signal. In the embodiment of the present invention, the first accumulated signal is output as the target accumulated signal. Among them, for the 8-bit binary digital sampling signal, after superposition, a 9-bit first accumulated signal is obtained.
第一累加信号通过第七寄存器110暂存后，输出给处理器的数据处理单元，处理器的数据处理单元根据所述第一累加信号进行信号处理，得到目标累加信号的信号特征，其中，所述信号特征包括幅度，频度，相位，频谱等特征。其中，处理器可以为FPGA。After the first accumulated signal is temporarily stored in the seventh register 110, it is output to the data processing unit of the processor, and the data processing unit of the processor performs signal processing according to the first accumulated signal to obtain the signal characteristics of the target accumulated signal, wherein the The signal characteristics include amplitude, frequency, phase, spectrum and other characteristics. The processor may be an FPGA.
本发明实施例中，对于8位采样精度的8位数字采样信号，若信号采样模块111的模拟信号输入峰峰值为2V，则8位(bit)的采样精度为把2V分成256份(2的8次方)，平均每份的精度是2V/256，为0.0078125V，也就是普通的ADC采分辨率。因此，通过第一累加器105的叠加后，变为了9位(bit)数字采样信号，平均每份的精度为2V/516，为0.00390625V，也即，等效增强了信号的分辨率。In the embodiment of the present invention, for an 8-bit digital sampling signal with an 8-bit sampling precision, if the peak-to-peak value of the analog signal input to the signal sampling module 111 is 2V, the 8-bit sampling precision is to divide 2V into 256 parts (2 8 power), the average accuracy of each copy is 2V/256, which is 0.0078125V, which is the ordinary ADC sampling resolution. Therefore, after the superposition of the first accumulator 105, it becomes a 9-bit digital sampling signal, and the average precision of each part is 2V/516, which is 0.00390625V, that is, the resolution of the signal is equivalently enhanced.
本发明实施例通过设置级联的寄存器及累加器，能够使得当前时刻的预设位数的数字采样信号与后面时刻的预设位数的数字采样信号进行累加，从而使得累加后的信号增大，累加后的信号的位数多于预设位数，从而增加了数字采样信号的位数，以提高数字采样信号的分辨率，最终实现了提高示波器采样数据的精度的有益效果。In the embodiment of the present invention, by setting cascaded registers and accumulators, the digital sampling signal of the preset number of digits at the current moment can be accumulated with the digital sampling signal of the preset number of digits at the following moment, so that the accumulated signal increases , the number of digits of the accumulated signal is more than the preset number of digits, thereby increasing the number of digits of the digital sampling signal, so as to improve the resolution of the digital sampling signal, and finally achieve the beneficial effect of improving the accuracy of the sampling data of the oscilloscope.
图4示出了本发明又一实施例提供的示波器中的信号处理系统的结构示意图。本发明实施例中，通过两个寄存累加模块进行信号的放大，也即进行两次叠加放大。其中，FIG. 4 shows a schematic structural diagram of a signal processing system in an oscilloscope according to another embodiment of the present invention. In the embodiment of the present invention, signal amplification is performed through two register accumulation modules, that is, two superposition amplifications are performed. in,
信号采样模块111的输出端与第三寄存器103的输入端D1连接，第三寄存器103的输出端Q1与第四寄存器的输入端D2及第二累加器106的第一输入端连接，第四寄存器104的输出端Q2分别与第二累加器106的第二输入端及第一寄存器101的输入端D3连接，第一寄存器101的输出端Q3分别与第一累加器105的第一信号输入端及第二寄存器102的输入端D4连接，第二寄存器102的输出端Q4与第一累加器105的第二信号输入端连接。第一累加器105的输出端与第五寄存器108的输入端D6连接，第二累加器106的输出端与第六寄存器107的输入端D5连接，第五寄存器108的输出端Q6及第六寄存器107的输出端Q5分别与第三累加器109的第一输入端及第二输入端连接。第三累加器109的输出端与第七寄存器110的输入端连接。The output end of the signal sampling module 111 is connected to the input end D1 of the third register 103 , the output end Q1 of the third register 103 is connected to the input end D2 of the fourth register and the first input end of the second accumulator 106 , the fourth register The output terminal Q2 of 104 is respectively connected to the second input terminal of the second accumulator 106 and the input terminal D3 of the first register 101, and the output terminal Q3 of the first register 101 is respectively connected to the first signal input terminal of the first accumulator 105 and The input terminal D4 of the second register 102 is connected, and the output terminal Q4 of the second register 102 is connected to the second signal input terminal of the first accumulator 105 . The output end of the first accumulator 105 is connected to the input end D6 of the fifth register 108, the output end of the second accumulator 106 is connected to the input end D5 of the sixth register 107, the output end Q6 of the fifth register 108 and the sixth register The output terminal Q5 of 107 is connected to the first input terminal and the second input terminal of the third accumulator 109, respectively. The output terminal of the third accumulator 109 is connected to the input terminal of the seventh register 110 .
具体地，在第一时钟激励信号，信号采样模块111可以是8位数字采样信号，第一寄存器101、第二寄存器102、第三寄存器103、第四寄存器104、第五寄存器108、第六寄存器107及第七寄存器108均为基础寄存器，可以是9位寄存器，也即：当时钟CLK上升沿到达时，寄存器分别并行置入9位数据。第一累加器105、第二累加器106及第三累加器109可以是9位累加器。信号采样模块111输出第一暂存采样信号为第一时刻产生的8位数字采样信号。信号采样模块111将第一时刻产生的第一暂存采样信号在第一时钟激励信号内发送给第三寄存器103，第三寄存器103在第一时钟激励信号上升沿达到时， 接收到该8位的第一暂存采样信号，并在第二时钟激励信号上升沿到达时，将该第一暂存采样信号发送给第二累加器106及第四寄存器104。在第二时钟激励信号上升沿到达时，第三寄存器103接收第二暂存采样信号，第四寄存器104接收第一暂存采样信号。在第三时钟激励信号上升沿到达时，第三寄存器101接收第三存采样信号，并将第二暂存采样信号发送给第二累加器106；第二累加器106将第二时钟激励信号接收到的第一暂存采样信号输出，同时接收第二暂存采样信号，第四寄存器104接收第二暂存采样信号，同时将第一暂存采样信号发送给第二累加器106及第一寄存器104。在第四个时钟激励信号上升沿到达时，第三寄存器103接收第四暂存采样信号，同时将第三暂存采样信号分别发送给第二累加器106及第四寄存器104，第四寄存器104将第二暂存采样信号发送给第一寄存器101，第一寄存器101将第一暂存采样信号分别发送给第一累加器105及第二寄存器102。在第五个时钟激励信号上升沿到达时，第三寄存器103接收下一个暂存采样信号，将第四暂存采样信号发送给第二累加器106，同时第四寄存器104将第三暂存采样信号也发送给第二累加器106；同时第一寄存器102将第二暂存采样信号发送给第一累加器，第二寄存器102将第一暂存采样信号发送给第一累加器105；第一累加器105将第一暂存采样信号及第二暂存采样信号进行累加得到第一累加信号，同时第二累加器106将第三暂存采样信号和第四暂存采样信号进行累加得到第二累加信号。Specifically, in the first clock excitation signal, the signal sampling module 111 may be an 8-bit digital sampling signal, the first register 101, the second register 102, the third register 103, the fourth register 104, the fifth register 108, the sixth register 107 and the seventh register 108 are both basic registers, which may be 9-bit registers, that is, when the rising edge of the clock CLK arrives, the registers are respectively loaded with 9-bit data in parallel. The first accumulator 105, the second accumulator 106 and the third accumulator 109 may be 9-bit accumulators. The signal sampling module 111 outputs the first temporarily stored sampling signal as an 8-bit digital sampling signal generated at the first moment. The signal sampling module 111 sends the first temporarily stored sampling signal generated at the first moment to the third register 103 in the first clock excitation signal, and the third register 103 receives the 8-bit signal when the rising edge of the first clock excitation signal reaches. The first temporarily stored sampling signal is sent to the second accumulator 106 and the fourth register 104 when the rising edge of the second clock excitation signal arrives. When the rising edge of the second clock excitation signal arrives, the third register 103 receives the second temporarily stored sampling signal, and the fourth register 104 receives the first temporarily stored sampling signal. When the rising edge of the third clock excitation signal arrives, the third register 101 receives the third storage sampling signal, and sends the second temporary storage sampling signal to the second accumulator 106; the second accumulator 106 receives the second clock excitation signal The received first temporarily stored sampling signal is output, while receiving the second temporarily stored sampling signal, the fourth register 104 receives the second temporarily stored sampling signal, and simultaneously sends the first temporarily stored sampling signal to the second accumulator 106 and the first register. 104. When the rising edge of the fourth clock excitation signal arrives, the third register 103 receives the fourth temporarily stored sampling signal, and at the same time sends the third temporarily stored sampling signal to the second accumulator 106 and the fourth register 104 and the fourth register 104 respectively The second temporarily stored sampling signal is sent to the first register 101 , and the first register 101 sends the first temporarily stored sampling signal to the first accumulator 105 and the second register 102 respectively. When the rising edge of the fifth clock excitation signal arrives, the third register 103 receives the next temporarily stored sampling signal, sends the fourth temporarily stored sampling signal to the second accumulator 106, and at the same time the fourth register 104 stores the third temporarily stored sampling signal The signal is also sent to the second accumulator 106; at the same time, the first register 102 sends the second temporarily stored sampling signal to the first accumulator, and the second register 102 sends the first temporarily stored sampling signal to the first accumulator 105; the first The accumulator 105 accumulates the first temporarily stored sampling signal and the second temporarily stored sampling signal to obtain the first accumulated signal, while the second accumulator 106 accumulates the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to obtain the second. Accumulate signals.
第二累加信号通过第六寄存器107发送至第三累加器109第一输入端，第一累加信号通过第五寄存器108发送至第三累加器109的第二输入端，第三累加器109将第一累加信号及第二累加信号进行累加，得到目标累加信号输出。通过这样的方式，将每个时刻的信号均进行一次叠加，从而放大了信号，提高了信号分辨率。其中，对于8位二进制数字采样信号，经过2次叠加后，得到10位的目标累加信号。目标累加信号通过第七寄存器110暂存后，输出给处理器的数据处理单元，处理器的数据处理单元根据所述第一累加信号进行信号处理，得到目标累加信号的信号特征，其中，所述信号特征包括幅度，频度，相位，频谱等特征。The second accumulation signal is sent to the first input terminal of the third accumulator 109 through the sixth register 107 , the first accumulation signal is sent to the second input terminal of the third accumulator 109 through the fifth register 108 , and the third accumulator 109 converts the The first accumulated signal and the second accumulated signal are accumulated to obtain the target accumulated signal output. In this way, the signals at each moment are superimposed once, thereby amplifying the signal and improving the signal resolution. Among them, for the 8-bit binary digital sampling signal, after 2 times of superposition, a 10-bit target accumulated signal is obtained. After the target accumulated signal is temporarily stored in the seventh register 110, it is output to the data processing unit of the processor, and the data processing unit of the processor performs signal processing according to the first accumulated signal to obtain the signal characteristics of the target accumulated signal, wherein the Signal characteristics include amplitude, frequency, phase, spectrum and other characteristics.
本发明实施例中，示波器包括处理器，第一寄存器101、所述第二寄存器102、所述第三寄存器103、所述第四寄存器104、所述第一累加器105、所述第二累加器106及所述第三累加器109均设置于所述处理器中，可以采用处理器中的现有寄存器及累加器实现。其中，处理器可以为FPGA。In this embodiment of the present invention, the oscilloscope includes a processor, a first register 101, the second register 102, the third register 103, the fourth register 104, the first accumulator 105, and the second accumulator Both the accumulator 106 and the third accumulator 109 are set in the processor, and can be implemented by using existing registers and accumulators in the processor. The processor may be an FPGA.
本发明实施例中，该信号处理系统还包括：In the embodiment of the present invention, the signal processing system further includes:
检测模块，用于计算所述数字采样信号的幅值；a detection module for calculating the amplitude of the digital sampling signal;
确定模块，用于根据所述幅值确定所述数字采样信号是否低于预设阈值，当低于所述预设阈值时，将所述第一暂存采样信号发送给所述第三寄存器。所述确定模块还用于当所述幅值高于等于所述预设阈值时，将所述第一暂存采样信号发送给所述处理器；A determination module, configured to determine whether the digital sampling signal is lower than a preset threshold according to the amplitude, and send the first temporarily stored sampling signal to the third register when it is lower than the preset threshold. The determining module is further configured to send the first temporarily stored sampling signal to the processor when the amplitude is higher than or equal to the preset threshold;
所述处理器根据所述第一暂存采样信号进行信号处理，得到目标累加信号 的信号特征。The processor performs signal processing according to the first temporarily stored sampled signal to obtain the signal characteristics of the target accumulated signal.
也即，本发明实施例还通过设置检测模块和确定模块，来判断数字采样信号的分辨率或者信号强度是否过低。当过低时通过本发明实施例的寄存累加模块进行信号放大及噪声过滤，提高分辨率；当在正常范围内时，则可选择直接将第一暂存采样信号发送给处理器的数据处理单元根据所述第一累加信号进行信号处理，得到目标累加信号的信号特征。That is, the embodiment of the present invention further determines whether the resolution or signal strength of the digital sampling signal is too low by setting the detection module and the determination module. When it is too low, the signal amplification and noise filtering are performed by the register accumulation module of the embodiment of the present invention to improve the resolution; when it is within the normal range, the first temporarily stored sampling signal can be directly sent to the data processing unit of the processor. Signal processing is performed according to the first accumulated signal to obtain the signal characteristic of the target accumulated signal.
本发明实施例通过设置级联的寄存器及累加器，能够使得当前时刻的数字采样信号与后面时刻的数字采样信号进行累加，从而实现了放大数字采样信号的效果，增加了各个时刻数字采样信号的位数，最终实现了提高示波器采样数据的精度的有益效果。In the embodiment of the present invention, by setting cascaded registers and accumulators, the digital sampling signal at the current moment and the digital sampling signal at the following moment can be accumulated, thereby realizing the effect of amplifying the digital sampling signal and increasing the digital sampling signal at each moment. Finally, the beneficial effect of improving the accuracy of the sampling data of the oscilloscope is realized.
进一步地，通过设置检测模块及确定模块，使得能够针对不同的采样信号进行灵活调整。Further, by setting the detection module and the determination module, it is possible to flexibly adjust for different sampling signals.
图5示出了本发明示波器实施例的结构示意图。如图5所示，该示波器10包括上述的信号处理系统100。其中，本发明实施例示波器10中的信号处理系统100具有上述实施例中的全部特征，此处不再赘述。FIG. 5 shows a schematic structural diagram of an embodiment of an oscilloscope of the present invention. As shown in FIG. 5 , the oscilloscope 10 includes the above-mentioned signal processing system 100 . Wherein, the signal processing system 100 in the oscilloscope 10 according to the embodiment of the present invention has all the features of the above-mentioned embodiments, and details are not described herein again.
本发明实施例通过设置级联的寄存器及累加器，能够使得当前时刻的数字采样信号与后面时刻的数字采样信号进行累加，从而实现了放大数字采样信号的效果，最终实现了提高示波器采样数据的精度的有益效果。In the embodiment of the present invention, by setting cascaded registers and accumulators, the digital sampling signal at the current moment and the digital sampling signal at the following moment can be accumulated, thereby realizing the effect of amplifying the digital sampling signal, and finally improving the sampling data of the oscilloscope. The beneficial effect of precision.
进一步地，通过设置检测模块及确定模块，使得能够针对不同的采样信号进行灵活调整。Further, by setting the detection module and the determination module, it is possible to flexibly adjust for different sampling signals.
图6示出了本发明示波器中的信号处理方法实施例的流程示意图，该信号处理方法应用于示波器中，本发明实施例的信号处理方法基于上述实施例的信号处理系统。如图6所示，该信号处理方法包括：FIG. 6 shows a schematic flowchart of an embodiment of a signal processing method in an oscilloscope of the present invention. The signal processing method is applied to an oscilloscope. The signal processing method of the embodiment of the present invention is based on the signal processing system of the above embodiment. As shown in Figure 6, the signal processing method includes:
步骤110：信号采样模块接收模拟信号并根据所述模拟信号采样生成数字采样信号。Step 110: The signal sampling module receives the analog signal and generates a digital sampling signal according to the analog signal sampling.
步骤120：第一寄存器依次接收第一暂存采样信号及第二暂存采样信号，将所述第一暂存采样信号分别发送给第一累加器及第二寄存器，并将所述第二暂存采样信号发送给所述第一累加器；其中，所述第一暂存采样信号为所述信号采样模块在第一时刻生成的预设位数的所述数字采样信号，所述第二暂存采样信号为所述信号采样模块在第二时刻生成的预设位数的所述数字采样信号；所述第二时刻为所述第一时刻之后相邻的时刻。Step 120: The first register sequentially receives the first temporarily stored sampling signal and the second temporarily stored sampling signal, sends the first temporarily stored sampling signal to the first accumulator and the second register, respectively, and sends the second temporarily stored sampling signal to the first accumulator and the second register respectively. The stored sampling signal is sent to the first accumulator; wherein, the first temporarily stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at the first moment, and the second temporary sampling signal is The stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a second moment; the second moment is an adjacent moment after the first moment.
步骤130：第二寄存器接收所述第一暂存采样信号，并将所述第一暂存采样信号发送给所述第一累加器。Step 130: The second register receives the first temporarily stored sampling signal, and sends the first temporarily stored sampling signal to the first accumulator.
步骤140：第一累加器将所述第一暂存采样信号与所述第二暂存采样信号进行累加，得到第一累加信号。Step 140: The first accumulator accumulates the first temporarily stored sampling signal and the second temporarily stored sampling signal to obtain a first accumulated signal.
本发明实施例的示波器中的信号处理方法，还包括以下步骤：The signal processing method in the oscilloscope according to the embodiment of the present invention further includes the following steps:
第三寄存器依次接收所述信号采样模块发送的第一暂存采样信号、第二暂存采样信号、第三暂存采样信号及第四暂存采样信号，并将第四暂存采样信号发送给第二累加器，将所述第一暂存采样信号、所述第二暂存采样信号、所述第三暂存采样信号及所述第四暂存采样信号发送给第四寄存器；其中，所述第三暂存采样信号为所述信号采样模块在第三时刻生成的预设位数的所述数字采样信号，所述第四暂存采样信号为所述信号采样模块在第四时刻生成的预设位数的所述数字采样信号。The third register sequentially receives the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the signal sampling module, and sends the fourth temporarily stored sampling signal to The second accumulator sends the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to the fourth register; The third temporarily stored sampling signal is the digital sampling signal of a preset number of bits generated by the signal sampling module at the third moment, and the fourth temporarily stored sampling signal is the signal generated by the signal sampling module at the fourth moment. The digital sampled signal of a preset number of bits.
第四寄存器接收所述第三寄存器发送的第一暂存采样信号、第二暂存采样信号、第三暂存采样信号及第四暂存采样信号，将所述第三暂存采样信号发送给所述第二累加器，将所述第一暂存采样信号及第二暂存采样信号发送给所述第一寄存器。The fourth register receives the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the third register, and sends the third temporarily stored sampling signal to The second accumulator sends the first temporarily stored sampling signal and the second temporarily stored sampling signal to the first register.
所述第二累加器将所述第三暂存采样信号及所述第四暂存采样信号进行累加，得到第二累加信号。The second accumulator accumulates the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to obtain a second accumulated signal.
所述第三累加器将所述第一累加信号及所述第二累加信号进行累加，得到目标累加信号。The third accumulator accumulates the first accumulated signal and the second accumulated signal to obtain a target accumulated signal.
其中，本发明实施例的信号处理方法的具体步骤流程与上述方法实施例中的信号处理系统的工作过程相同，此处不再赘述。Wherein, the specific steps of the signal processing method in the embodiment of the present invention are the same as the working process of the signal processing system in the above method embodiment, which will not be repeated here.
本发明实施例通过设置级联的寄存器及累加器，能够使得当前时刻的数字采样信号与后面时刻的数字采样信号进行累加，从而实现了放大数字采样信号的效果，最终实现了提高示波器采样数据的精度的有益效果。In the embodiment of the present invention, by setting cascaded registers and accumulators, the digital sampling signal at the current moment and the digital sampling signal at the following moment can be accumulated, thereby realizing the effect of amplifying the digital sampling signal, and finally improving the sampling data of the oscilloscope. The beneficial effect of precision.
进一步地，通过设置检测模块及确定模块，使得能够针对不同的采样信号进行灵活调整。Further, by setting the detection module and the determination module, it is possible to flexibly adjust for different sampling signals.
在此提供的算法或显示不与任何特定计算机、虚拟系统或者其它设备固有相关。各种通用系统也可以与基于在此的示教一起使用。根据上面的描述，构造这类系统所要求的结构是显而易见的。此外，本发明实施例也不针对任何特定编程语言。应当明白，可以利用各种编程语言实现在此描述的本发明的内容，并且上面对特定语言所做的描述是为了披露本发明的最佳实施方式。The algorithms or displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used with teaching based on this. The structure required to construct such a system is apparent from the above description. Furthermore, embodiments of the present invention are not directed to any particular programming language. It is to be understood that various programming languages may be used to implement the inventions described herein, and that the descriptions of specific languages above are intended to disclose the best mode for carrying out the invention.
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。In the description provided herein, numerous specific details are set forth. It will be understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
类似地，应当理解，为了精简本发明并帮助理解各个发明方面中的一个或多个，在上面对本发明的示例性实施例的描述中，本发明实施例的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本发明要求比在每个权利要求中所明确记载的特征更多的特征。Similarly, it is to be understood that, in the above description of exemplary embodiments of the invention, various features of the embodiments of the invention are sometimes grouped together into a single implementation in order to simplify the invention and to aid in the understanding of one or more of the various aspects of the invention. examples, figures, or descriptions thereof. This disclosure, however, should not be construed as reflecting an intention that the invention as claimed requires more features than are expressly recited in each claim.
本领域技术人员可以理解，可以对实施例中的设备中的模块进行自适应性地改变并且把它们设置在与该实施例不同的一个或多个设备中。可以把实施例 中的模块或单元或组件组合成一个模块或单元或组件，以及可以把它们分成多个子模块或子单元或子组件。除了这样的特征和/或过程或者单元中的至少一些是相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的的替代特征来代替。Those skilled in the art can understand that the modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment. The modules or units or components in the embodiments may be combined into one module or unit or component, and they may be divided into multiple sub-modules or sub-units or sub-assemblies. All features disclosed in this specification (including accompanying claims, abstract and drawings) and any method so disclosed may be employed in any combination, unless at least some of such features and/or procedures or elements are mutually exclusive. All processes or units of equipment are combined. Each feature disclosed in this specification (including accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
应该注意的是上述实施例对本发明进行说明而不是对本发明进行限制，并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。上述实施例中的步骤，除有特殊说明外，不应理解为对执行顺序的限定。It should be noted that the above-described embodiments illustrate rather than limit the invention, and that alternative embodiments may be devised by those skilled in the art without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, and third, etc. do not denote any order. These words can be interpreted as names. The steps in the above embodiments should not be construed as limitations on the execution order unless otherwise specified.

Claims (10)

  1. 一种示波器中的信号处理系统，其特征在于，应用于示波器中，所述信号处理系统包括信号采样模块及至少一个寄存累加模块；所述寄存累加模块包括第一寄存器、第二寄存器及第一累加器；A signal processing system in an oscilloscope, characterized in that, when applied to an oscilloscope, the signal processing system includes a signal sampling module and at least one register accumulation module; the register accumulation module includes a first register, a second register, and a first register and accumulation module. accumulator;
    所述信号采样模块，用于接收模拟信号并根据所述模拟信号采样生成数字采样信号；the signal sampling module, configured to receive an analog signal and generate a digital sampling signal according to the sampling of the analog signal;
    所述第一寄存器，用于依次接收第一暂存采样信号及第二暂存采样信号，将所述第一暂存采样信号分别发送给所述第一累加器及所述第二寄存器，并将所述第二暂存采样信号发送给所述第一累加器；其中，所述第一暂存采样信号为所述信号采样模块在第一时刻生成的预设位数的所述数字采样信号，所述第二暂存采样信号为所述信号采样模块在第二时刻生成的预设位数的所述数字采样信号；所述第二时刻为所述第一时刻之后相邻的时刻；The first register is used to sequentially receive the first temporarily stored sampling signal and the second temporarily stored sampling signal, send the first temporarily stored sampling signal to the first accumulator and the second register respectively, and Send the second temporarily stored sampling signal to the first accumulator; wherein, the first temporarily stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at the first moment , the second temporarily stored sampling signal is the digital sampling signal of a preset number of digits generated by the signal sampling module at a second moment; the second moment is an adjacent moment after the first moment;
    所述第二寄存器，用于接收所述第一暂存采样信号，并将所述第一暂存采样信号发送给所述第一累加器；the second register, configured to receive the first temporarily stored sampling signal, and send the first temporarily stored sampling signal to the first accumulator;
    所述第一累加器，用于将所述第一暂存采样信号与所述第二暂存采样信号进行累加，得到第一累加信号。The first accumulator is configured to accumulate the first temporarily stored sampling signal and the second temporarily stored sampling signal to obtain a first accumulated signal.
  2. 根据权利要求1所述的信号处理系统，其特征在于，所述信号处理系统还包括：第三寄存器、第四寄存器、第二累加器及第三累加器；The signal processing system according to claim 1, wherein the signal processing system further comprises: a third register, a fourth register, a second accumulator and a third accumulator;
    所述第三寄存器，用于依次接收所述信号采样模块发送的第一暂存采样信号、第二暂存采样信号、第三暂存采样信号及第四暂存采样信号，并将第四暂存采样信号发送给所述第二累加器，将所述第一暂存采样信号、所述第二暂存采样信号、所述第三暂存采样信号及所述第四暂存采样信号发送给所述第四寄存器；其中，所述第三暂存采样信号为所述信号采样模块在第三时刻生成的预设位数的所述数字采样信号，所述第四暂存采样信号为所述信号采样模块在第四时刻生成的预设位数的所述数字采样信号；The third register is used to sequentially receive the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the signal sampling module, and store the fourth temporarily stored sampling signal. The storage sampling signal is sent to the second accumulator, and the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal are sent to the the fourth register; wherein, the third temporarily stored sampling signal is the digital sampling signal with a preset number of digits generated by the signal sampling module at the third moment, and the fourth temporarily stored sampling signal is the the digital sampling signal of the preset number of bits generated by the signal sampling module at the fourth moment;
    所述第四寄存器，用于接收所述第三寄存器发送的第一暂存采样信号、第二暂存采样信号、第三暂存采样信号及第四暂存采样信号，将所述第三暂存采样信号发送给所述第二累加器，将所述第一暂存采样信号及第二暂存采样信号发送给所述第一寄存器；The fourth register is used to receive the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the third register, and the third temporary storage sampling signal sending the stored sampling signal to the second accumulator, and sending the first temporarily stored sampling signal and the second temporarily stored sampling signal to the first register;
    所述第二累加器，用于将所述第三暂存采样信号及所述第四暂存采样信号进行累加，得到第二累加信号；the second accumulator for accumulating the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to obtain a second accumulated signal;
    所述第三累加器，用于将所述第一累加信号及所述第二累加信号进行累加，得到目标累加信号。The third accumulator is used for accumulating the first accumulating signal and the second accumulating signal to obtain a target accumulating signal.
  3. 根据权利要求2所述的信号处理系统，其特征在于，所述示波器包括处理器，所述第一寄存器、所述第二寄存器、所述第三寄存器、所述第四寄存器、所述第一累加器、所述第二累加器及所述第三累加器均设置于所述处理器中；The signal processing system according to claim 2, wherein the oscilloscope comprises a processor, the first register, the second register, the third register, the fourth register, the first register The accumulator, the second accumulator and the third accumulator are all arranged in the processor;
    所述处理器，还用于根据所述目标累加信号进行信号处理，得到目标累加 信号的信号特征。The processor is further configured to perform signal processing according to the target accumulated signal to obtain signal characteristics of the target accumulated signal.
  4. 根据权利要求3所述的信号处理系统，其特征在于，所述第一寄存器、第二寄存器、所述第三寄存器、所述第四寄存器、所述第一累加器、所述第二累加器及所述第三累加器的时钟激励信号相同。The signal processing system according to claim 3, wherein the first register, the second register, the third register, the fourth register, the first accumulator, and the second accumulator and the clock excitation signal of the third accumulator is the same.
  5. 根据权利要求2所述的信号处理系统，其特征在于，还包括：The signal processing system according to claim 2, further comprising:
    检测模块，用于计算所述数字采样信号的幅值；a detection module for calculating the amplitude of the digital sampling signal;
    确定模块，用于根据所述幅值确定所述数字采样信号是否低于预设阈值，当低于所述预设阈值时，将所述第一暂存采样信号发送给所述第三寄存器。A determination module, configured to determine whether the digital sampling signal is lower than a preset threshold according to the amplitude, and send the first temporarily stored sampling signal to the third register when it is lower than the preset threshold.
  6. 根据权利要求5所述的信号处理系统，其特征在于，所述确定模块还用于当所述幅值高于等于所述预设阈值时，将所述第一暂存采样信号发送给所述处理器；The signal processing system according to claim 5, wherein the determining module is further configured to send the first temporarily stored sampling signal to the processor;
    所述处理器根据所述第一暂存采样信号进行信号处理，得到目标累加信号的信号特征。The processor performs signal processing according to the first temporarily stored sampled signal to obtain the signal characteristic of the target accumulated signal.
  7. 一种示波器，其特征在于，所述示波器包括如权利要求1-6任一项所述的信号处理系统。An oscilloscope, characterized in that the oscilloscope comprises the signal processing system according to any one of claims 1-6.
  8. 一种示波器中的信号处理方法，其特征在于，包括以下步骤：A signal processing method in an oscilloscope, comprising the following steps:
    信号采样模块接收模拟信号并根据所述模拟信号采样生成数字采样信号；The signal sampling module receives the analog signal and generates a digital sampling signal according to the sampling of the analog signal;
    第一寄存器依次接收第一暂存采样信号及第二暂存采样信号，将所述第一暂存采样信号分别发送给第一累加器及第二寄存器，并将所述第二暂存采样信号发送给所述第一累加器；其中，所述第一暂存采样信号为所述信号采样模块在第一时刻生成的预设位数的所述数字采样信号，所述第二暂存采样信号为所述信号采样模块在第二时刻生成的预设位数的所述数字采样信号；所述第二时刻为所述第一时刻之后相邻的时刻；The first register sequentially receives the first temporarily stored sampling signal and the second temporarily stored sampling signal, sends the first temporarily stored sampling signal to the first accumulator and the second register respectively, and sends the second temporarily stored sampling signal to the first accumulator and the second register respectively. sent to the first accumulator; wherein, the first temporarily stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at the first moment, and the second temporarily stored sampling signal is the digital sampling signal of a preset number of digits generated by the signal sampling module at a second moment; the second moment is an adjacent moment after the first moment;
    第二寄存器接收所述第一暂存采样信号，并将所述第一暂存采样信号发送给所述第一累加器；The second register receives the first temporarily stored sampling signal, and sends the first temporarily stored sampling signal to the first accumulator;
    第一累加器将所述第一暂存采样信号与所述第二暂存采样信号进行累加，得到第一累加信号。The first accumulator accumulates the first temporarily stored sampling signal and the second temporarily stored sampling signal to obtain a first accumulated signal.
  9. 根据权利要求8所述的方法，其特征在于，还包括以下步骤：The method of claim 8, further comprising the steps of:
    第三寄存器依次接收所述信号采样模块发送的第一暂存采样信号、第二暂存采样信号、第三暂存采样信号及第四暂存采样信号，并将第四暂存采样信号发送给第二累加器，将所述第一暂存采样信号、所述第二暂存采样信号、所述第三暂存采样信号及所述第四暂存采样信号发送给第四寄存器；其中，所述第三暂存采样信号为所述信号采样模块在第三时刻生成的预设位数的所述数字采样信号，所述第四暂存采样信号为所述信号采样模块在第四时刻生成的预设位数的所述数字采样信号；The third register sequentially receives the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the signal sampling module, and sends the fourth temporarily stored sampling signal to The second accumulator sends the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to the fourth register; The third temporarily stored sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at the third moment, and the fourth temporarily stored sampling signal is the signal generated by the signal sampling module at the fourth moment. the digital sampling signal of a preset number of bits;
    第四寄存器接收所述第三寄存器发送的第一暂存采样信号、第二暂存采样信号、第三暂存采样信号及第四暂存采样信号，将所述第三暂存采样信号发送给所述第二累加器，将所述第一暂存采样信号及第二暂存采样信号发送给所述 第一寄存器；The fourth register receives the first temporarily stored sampling signal, the second temporarily stored sampling signal, the third temporarily stored sampling signal and the fourth temporarily stored sampling signal sent by the third register, and sends the third temporarily stored sampling signal to The second accumulator sends the first temporarily stored sampling signal and the second temporarily stored sampling signal to the first register;
    所述第二累加器将所述第三暂存采样信号及所述第四暂存采样信号进行累加，得到第二累加信号；The second accumulator accumulates the third temporarily stored sampling signal and the fourth temporarily stored sampling signal to obtain a second accumulated signal;
    所述第三累加器将所述第一累加信号及所述第二累加信号进行累加，得到目标累加信号。The third accumulator accumulates the first accumulated signal and the second accumulated signal to obtain a target accumulated signal.
  10. 根据权利要求9所述的方法，其特征在于，处理器根据所述目标累加信号进行信号处理，得到目标累加信号的信号特征。The method according to claim 9, wherein the processor performs signal processing according to the target accumulated signal to obtain signal characteristics of the target accumulated signal.
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