CN112600561A - Signal processing system in oscilloscope, oscilloscope and signal processing method - Google Patents
Signal processing system in oscilloscope, oscilloscope and signal processing method Download PDFInfo
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Abstract
The embodiment of the invention relates to the technical field of oscilloscopes, and discloses a signal processing system in an oscilloscope, which comprises a signal sampling module and at least one register accumulation module; the register accumulation module comprises a first register, a second register and a first accumulator; the signal sampling module is used for receiving the analog signal and generating a digital sampling signal according to the analog signal; the first register is used for sequentially receiving a first temporary storage sampling signal and a second temporary storage sampling signal, respectively sending the first temporary storage sampling signal to the first accumulator and the second register, and sending the second temporary storage sampling signal to the first accumulator; the second register is used for receiving the first temporary storage sampling signal and sending the first temporary storage sampling signal to the first accumulator; the first accumulator is used for accumulating the first temporary storage sampling signal and the second temporary storage sampling signal to obtain a first accumulated signal. Through the mode, the embodiment of the invention realizes the beneficial effect of enhancing the signal resolution.
Description
Technical Field
The embodiment of the invention relates to the technical field of oscilloscopes, in particular to a signal processing system in an oscilloscope, the oscilloscope and a signal processing method in the oscilloscope.
Background
At present, as automobile technology is continuously developed, more and more automobile electrical systems are provided, and once problems occur in the systems, problem troubleshooting is firstly required to be carried out. Measurement of signals is the key to finding problems, oscilloscopes being the primary measurement tool. The oscilloscope can measure the amplitude, frequency, phase, frequency spectrum and other characteristics of the signal. The deeper the storage depth of the oscilloscope is, the more complete the data captured at one time is, and the more easily the signal can be judged whether to be normal or not through characteristic analysis of the signal.
When the existing oscilloscope performs signal analysis, firstly, an analog signal needs to be captured, and then analog-to-digital signal conversion is performed through ADC sampling, so that the higher the ADC sampling resolution is, the lower the quantization distortion of the signal is theoretically, and the higher the signal-to-noise ratio is. However, the resolution and the accuracy of the conventional oscilloscope are generally fixed, which is not suitable for scenes with weak signals.
Disclosure of Invention
In view of the above problems, embodiments of the present invention provide a signal processing system in an oscilloscope, and a signal processing method in an oscilloscope, which are used to solve the problem in the prior art that the accuracy of sampling data of an oscilloscope is low.
According to an aspect of the embodiments of the present invention, a signal processing system in an oscilloscope is provided, which is applied in the oscilloscope, and the signal processing system includes a signal sampling module and at least one register and accumulation module; the register accumulation module comprises a first register, a second register and a first accumulator;
the signal sampling module is used for receiving an analog signal and generating a digital sampling signal according to the analog signal;
the first register is used for sequentially receiving a first temporary storage sampling signal and a second temporary storage sampling signal, respectively sending the first temporary storage sampling signal to the first accumulator and the second register, and sending the second temporary storage sampling signal to the first accumulator; the first temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a first moment, and the second temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a second moment; the second moment is adjacent moment after the first moment;
the second register is used for receiving the first temporary storage sampling signal and sending the first temporary storage sampling signal to the first accumulator;
the first accumulator is configured to accumulate the first temporary storage sampling signal and the second temporary storage sampling signal to obtain a first accumulated signal.
In an optional manner, the signal processing system further includes: a third register, a fourth register, a second accumulator and a third accumulator;
the third register is used for sequentially receiving the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal sent by the signal sampling module, sending the fourth temporary storage sampling signal to the second accumulator, and sending the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal to the fourth register; the third temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a third moment, and the fourth temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a fourth moment;
the fourth register is configured to receive the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal sent by the third register, send the third temporary storage sampling signal to the second accumulator, and send the first temporary storage sampling signal and the second temporary storage sampling signal to the first register;
the second accumulator is used for accumulating the third temporary storage sampling signal and the fourth temporary storage sampling signal to obtain a second accumulated signal;
the third accumulator is configured to accumulate the first accumulated signal and the second accumulated signal to obtain a target accumulated signal.
In an optional manner, the oscilloscope includes a processor, and the first register, the second register, the third register, the fourth register, the first accumulator, the second accumulator, and the third accumulator are all disposed in the processor;
the processor is further configured to perform signal processing according to the target accumulated signal to obtain a signal characteristic of the target accumulated signal.
In an alternative mode, the clock excitation signals of the first register, the second register, the third register, the fourth register, the first accumulator, the second accumulator and the third accumulator are the same.
In an optional manner, the method further comprises:
the detection module is used for calculating the amplitude of the digital sampling signal;
and the determining module is used for determining whether the digital sampling signal is lower than a preset threshold value according to the amplitude value, and sending the first temporary storage sampling signal to the third register when the digital sampling signal is lower than the preset threshold value.
In an optional manner, the determining module is further configured to send the first temporary sampling signal to the processor when the amplitude is greater than or equal to the preset threshold;
and the processor performs signal processing according to the first temporary storage sampling signal to obtain the signal characteristic of the target accumulated signal.
According to another aspect of the embodiments of the present invention, there is provided an oscilloscope, including the signal processing system described above.
According to another aspect of the embodiments of the present invention, there is provided a signal processing method in an oscilloscope, including:
the method comprises the following steps:
the signal sampling module receives an analog signal and generates a digital sampling signal according to the analog signal;
the method comprises the steps that a first register sequentially receives a first temporary storage sampling signal and a second temporary storage sampling signal, the first temporary storage sampling signal is respectively sent to a first accumulator and a second register, and the second temporary storage sampling signal is sent to the first accumulator; the first temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a first moment, and the second temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a second moment; the second moment is adjacent moment after the first moment;
the second register receives the first temporary storage sampling signal and sends the first temporary storage sampling signal to the first accumulator;
and the first accumulator accumulates the first temporary storage sampling signal and the second temporary storage sampling signal to obtain a first accumulated signal.
In an optional manner, the method further comprises the following steps:
the third register sequentially receives a first temporary storage sampling signal, a second temporary storage sampling signal, a third temporary storage sampling signal and a fourth temporary storage sampling signal sent by the signal sampling module, sends the fourth temporary storage sampling signal to a second accumulator, and sends the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal to a fourth register; the third temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a third moment, and the fourth temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a fourth moment;
the fourth register receives the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal sent by the third register, sends the third temporary storage sampling signal to the second accumulator, and sends the first temporary storage sampling signal and the second temporary storage sampling signal to the first register;
the second accumulator accumulates the third temporary storage sampling signal and the fourth temporary storage sampling signal to obtain a second accumulated signal;
and the third accumulator accumulates the first accumulated signal and the second accumulated signal to obtain a target accumulated signal.
In an alternative mode, the processor performs signal processing according to the target accumulated signal to obtain a signal characteristic of the target accumulated signal.
According to the embodiment of the invention, through the arrangement of the cascaded register and the cascaded accumulator, the digital sampling signal with the preset digit at the current moment and the digital sampling signal with the preset digit at the later moment can be accumulated, so that the accumulated signals are amplified, the digit of the accumulated signals is more than the preset digit, the digit of the digital sampling signals is increased, the resolution ratio of the digital sampling signals is improved, and the beneficial effect of improving the precision of the sampling data of the oscilloscope is finally realized.
Furthermore, the detection module and the determination module are arranged, so that the flexible adjustment can be performed on different sampling signals.
The foregoing description is only an overview of the technical solutions of the embodiments of the present invention, and the embodiments of the present invention can be implemented according to the content of the description in order to make the technical means of the embodiments of the present invention more clearly understood, and the detailed description of the present invention is provided below in order to make the foregoing and other objects, features, and advantages of the embodiments of the present invention more clearly understandable.
Drawings
The drawings are only for purposes of illustrating embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a schematic structural diagram illustrating a signal processing system in an oscilloscope provided by an embodiment of the present invention;
FIG. 2 shows a schematic diagram of an ADC sampling process;
FIG. 3 is a schematic diagram showing a signal processing system in an oscilloscope according to another embodiment of the present invention;
FIG. 4 is a schematic diagram showing a signal processing system in an oscilloscope according to another embodiment of the present invention;
FIG. 5 is a schematic diagram of an oscilloscope provided by an embodiment of the present invention;
fig. 6 is a flowchart illustrating a signal processing method in an oscilloscope according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein.
First, the concept involved in the acquisition of a digital sampling signal is explained:
number of digits of the digital quantity: the analog-to-digital conversion process includes sampling, holding, quantizing, and encoding. The coding is to code the quantized signal into a binary code and output the binary code. Sampling the analog signal, converting the sampled value into digital value and giving out the conversion result according to a certain coding form. Such as 8 bits/10 bits/12 bits, etc.
The resolution is a variation amount of an output analog quantity (voltage or current) corresponding to a variation in the Least Significant Bit (LSB) of an input digital quantity. It reflects the minimum variation value of the output analog quantity. The resolution has a definite relationship with the number of bits of the input digital quantity (the sample signal input at each moment), which can be expressed as FS/2^ n. FS represents the full scale input value and n is the number of binary bits. For a full scale of 5V, when an 8-bit DAC is adopted, the resolution is 19.5mV (measured in terms of 5V/256); when a 12-bit DAC is used, the resolution is 1.22mV versus 5V/4096. Obviously, the more the number of bits of the input digital quantity, the higher the resolution.
Therefore, when the number of bits of the input digital quantity increases, the resolution increases, and the quantization error corresponding to the influence on the precision decreases.
Based on the principle, the digital sampling signals with preset digits at different moments are added by setting the connection relation of the plurality of registers and the accumulator so as to increase the digits of the digital sampling signals at each moment, thereby improving the resolution and finally obtaining the effect of improving the precision. Since the sampling interval of the oscilloscope is very small, typically on the order of picoseconds. E.g. once every 100ps, the difference before sampling the signal at each moment is very small, so that superimposing the signal does not result in a change of the characteristics of the signal.
Fig. 1 is a block diagram showing an embodiment of a signal processing system in an oscilloscope to which the present invention is applied. As shown in fig. 1, the signal processing system 100 includes a signal sampling module 111 and at least one register-and-accumulate module. The register and accumulation module comprises a first register 101, a second register 102 and a first accumulator 105. In the embodiment of the present invention, the clock excitation signals of the first register 101, the second register 102 and the first accumulator 105 are the same. Wherein:
the signal sampling module 111 is configured to receive an analog signal and generate a digital sampling signal according to the analog signal. Fig. 2 illustrates an ADC sampling process in an embodiment of the present invention, for an analog signal generated by a measured object, the analog signal can be converted into a discretized digital sampling signal through ADC sampling, and can be represented by a code with a preset number of bits; for example, for 8-bit sampling accuracy, it can be represented by 8-bit encoding. The acquisition process of the digital sampling signal is real-time and continuous.
The first register 101 is configured to sequentially receive a first temporary storage sampling signal and a second temporary storage sampling signal, send the first temporary storage sampling signal to the first accumulator 105 and the second register 102, respectively, and send the second temporary storage sampling signal to the first accumulator 105; the first temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a first moment, and the second temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a second moment; the second time is an adjacent time after the first time. Namely: after receiving the first temporary sampling signal, the first register 101 sends it to the first accumulator 105 and the second register 102. After receiving the second temporary sampling signal after a clock excitation signal, i.e. at a second time, the second temporary sampling signal is sent to the first input port of the first accumulator 105, and at this time, the first temporary sampling signal stored by the first accumulator 105 in the previous clock excitation signal is replaced by the second temporary sampling signal of the current clock excitation signal.
The second register 102 is configured to receive the first temporary sampling signal and send the first temporary sampling signal to the first accumulator 105. The first temporary sampling signal received by the second register 102 is sent to the second input port of the first accumulator 105 after passing through a clock excitation signal.
The first accumulator 105 is configured to accumulate the first temporary storage sampling signal and the second temporary storage sampling signal to obtain a first accumulated signal. At this time, under the current clock excitation signal, the first accumulator 105 receives the first temporary sampling signal and the second temporary sampling signal at the same time, and accumulates the two signals, thereby obtaining a first accumulated signal.
In the embodiment of the present invention, by providing the register accumulation module, the first register 101 directly sends the second temporary storage sampling signal to the first accumulator 105, and at the same time, the first temporary storage sampling signal is temporarily stored by the second register 102 by a clock excitation signal and then sent to the first accumulator 105, which is equivalent to performing a time delay on the first temporary storage sampling signal, so that the second temporary storage sampling signal is superimposed on the first temporary storage sampling signal, and the digital sampling signal (the first temporary storage sampling signal generated at the first time and the second temporary storage sampling signal generated at the second time) is processed, so that the first temporary storage sampling signal is amplified. Similarly, the temporary storage sampling signals at each subsequent moment are superposed with the signals at the next moment or the previous moment, so that the first temporary storage sampling signal is amplified, and the sampling precision of the ADC is equivalently improved on the one hand; on the other hand, the method is equivalent to window filtering, and high-frequency noise is effectively filtered.
In the embodiment of the invention, the oscilloscope further comprises a processor. And after the first accumulated signal is obtained, the oscilloscope is used for carrying out signal processing on the first accumulated signal to obtain the signal characteristic of the first accumulated signal.
In the embodiment of the invention, the oscilloscope further comprises a display module. And the display module is used for receiving the signal characteristics and displaying the signal characteristics.
According to the embodiment of the invention, through the arrangement of the cascaded register and the cascaded accumulator, the digital sampling signal with the preset digit at the current moment and the digital sampling signal with the preset digit at the later moment can be accumulated, so that the accumulated signals are increased, the digit of the accumulated signals is more than the preset digit, the digit of the digital sampling signals is increased, the resolution ratio of the digital sampling signals is improved, and the beneficial effect of improving the precision of the sampling data of the oscilloscope is finally realized.
Fig. 3 is a schematic structural diagram of a signal processing system in an oscilloscope according to another embodiment of the present invention. In the embodiment of the invention, the signal is amplified through a register accumulation module. I.e. a superposition amplification is performed. Therefore, the signal sampling module 111 is directly connected to the input terminal D3 of the first register 101, the output terminal Q3 of the first register 101 is connected to the first input port of the first accumulator 105, the output terminal Q3 of the first register 101 is further connected to the input terminal D4 of the second register 102, the output port Q4 of the second register 102 is connected to the second input port of the first accumulator 105, and the output terminal of the first accumulator is connected to the input terminal D7 of the seventh register 110. The clock signals of the first register 101, the second register 102, the first accumulator 105 and the seventh register 110 are the same. The first accumulator 105 outputs the result through the first register 110.
In the embodiment of the present invention, the signal sampling module 111 may be an 8-bit digital sampling signal, and the first register 101 and the second register 102 are basic registers, and may be 9-bit registers, that is: when the rising edge of the clock CLK arrives, the first register 101 and the second register 102 are respectively placed in parallel with 9-bit data. The first accumulator 105 may be a 9-bit accumulator. The signal sampling module 111 outputs the first temporary sampling signal as an 8-bit digital sampling signal generated at the first time. The signal sampling module 111 sends a first temporary sampling signal generated at a first time to the first register 101 in the first clock excitation signal, and the first register 101 receives the 8-bit first temporary sampling signal when a rising edge of the first clock excitation signal arrives, and sends the first temporary sampling signal to the first accumulator 105 and the second register 102 when a rising edge of the second clock excitation signal arrives. When the rising edge of the second clock excitation signal arrives, the first register 101 receives the second temporary sampling signal, and the second register receives the first temporary sampling signal. When the rising edge of the third clock excitation signal arrives, the first register 101 receives the next temporary sampling signal and sends the second temporary sampling signal to the first accumulator 105; the first accumulator 105 outputs the first temporary sampling signal received by the second clock excitation signal and simultaneously receives the second temporary sampling signal, the second register 102 receives the second temporary sampling signal and simultaneously sends the first temporary sampling signal to the first accumulator 105; the first accumulator 105 receives the first temporary storage sampling signal and the second temporary storage sampling signal at the same time at the third clock excitation signal, and performs accumulation calculation to obtain a first accumulation signal. In the embodiment of the invention, the first accumulation signal is output as the target accumulation signal. The 8-bit binary digital sampling signals are superposed to obtain a 9-bit first accumulated signal.
The first accumulated signal is temporarily stored in the seventh register 110 and then output to the data processing unit of the processor, and the data processing unit of the processor performs signal processing according to the first accumulated signal to obtain the signal characteristics of the target accumulated signal, wherein the signal characteristics include amplitude, frequency, phase, frequency spectrum and other characteristics. The processor may be an FPGA.
In the embodiment of the present invention, for an 8-bit digital sampling signal with 8-bit sampling precision, if the analog signal input peak value of the signal sampling module 111 is 2V, the sampling precision of 8 bits (bit) is to divide 2V into 256 parts (8 powers of 2), and the precision of each part is 2V/256 and 0.0078125V on average, that is, the resolution of the ordinary ADC. Therefore, after superposition by the first accumulator 105, a 9-bit (bit) digital sampling signal is obtained, the average precision of each part is 2V/516 and 0.00390625V, namely, the resolution of the signal is equivalently enhanced.
According to the embodiment of the invention, through the arrangement of the cascaded register and the cascaded accumulator, the digital sampling signal with the preset digit at the current moment and the digital sampling signal with the preset digit at the later moment can be accumulated, so that the accumulated signals are increased, the digit of the accumulated signals is more than the preset digit, the digit of the digital sampling signals is increased, the resolution ratio of the digital sampling signals is improved, and the beneficial effect of improving the precision of the sampling data of the oscilloscope is finally realized.
Fig. 4 is a schematic structural diagram illustrating a signal processing system in an oscilloscope according to another embodiment of the present invention. In the embodiment of the invention, the signals are amplified through the two register accumulation modules, namely, two times of superposition amplification are carried out. Wherein,
the output end of the signal sampling module 111 is connected to the input end D1 of the third register 103, the output end Q1 of the third register 103 is connected to the input end D2 of the fourth register and the first input end of the second accumulator 106, the output end Q2 of the fourth register 104 is connected to the second input end of the second accumulator 106 and the input end D3 of the first register 101, the output end Q3 of the first register 101 is connected to the first signal input end of the first accumulator 105 and the input end D4 of the second register 102, and the output end Q4 of the second register 102 is connected to the second signal input end of the first accumulator 105. The output of the first accumulator 105 is connected to the input D6 of the fifth register 108, the output of the second accumulator 106 is connected to the input D5 of the sixth register 107, and the output Q6 of the fifth register 108 and the output Q5 of the sixth register 107 are connected to the first input and the second input of the third accumulator 109, respectively. The output of the third accumulator 109 is connected to the input of the seventh register 110.
Specifically, in the first clock excitation signal, the signal sampling module 111 may be an 8-bit digital sampling signal, and the first register 101, the second register 102, the third register 103, the fourth register 104, the fifth register 108, the sixth register 107, and the seventh register 108 are all basic registers, and may be 9-bit registers, that is: when the rising edge of the clock CLK arrives, the registers are respectively put in 9-bit data in parallel. The first accumulator 105, the second accumulator 106, and the third accumulator 109 may be 9-bit accumulators. The signal sampling module 111 outputs the first temporary sampling signal as an 8-bit digital sampling signal generated at the first time. The signal sampling module 111 sends a first temporary sampling signal generated at a first time to the third register 103 in the first clock excitation signal, and the third register 103 receives the 8-bit first temporary sampling signal when a rising edge of the first clock excitation signal arrives, and sends the first temporary sampling signal to the second accumulator 106 and the fourth register 104 when a rising edge of the second clock excitation signal arrives. When the rising edge of the second clock excitation signal arrives, the third register 103 receives the second temporary sampling signal, and the fourth register 104 receives the first temporary sampling signal. When the rising edge of the third clock excitation signal arrives, the third register 101 receives the third temporary sampling signal and sends the second temporary sampling signal to the second accumulator 106; the second accumulator 106 outputs the first temporary sampling signal received by the second clock excitation signal and simultaneously receives the second temporary sampling signal, and the fourth register 104 receives the second temporary sampling signal and simultaneously sends the first temporary sampling signal to the second accumulator 106 and the first register 104. When the rising edge of the fourth clock excitation signal arrives, the third register 103 receives the fourth temporary sampling signal and simultaneously sends the third temporary sampling signal to the second accumulator 106 and the fourth register 104, respectively, the fourth register 104 sends the second temporary sampling signal to the first register 101, and the first register 101 sends the first temporary sampling signal to the first accumulator 105 and the second register 102, respectively. When the rising edge of the fifth clock excitation signal arrives, the third register 103 receives the next temporary sampling signal, and sends the fourth temporary sampling signal to the second accumulator 106, and simultaneously the fourth register 104 sends the third temporary sampling signal to the second accumulator 106; meanwhile, the first register 102 sends the second temporary sampling signal to the first accumulator, and the second register 102 sends the first temporary sampling signal to the first accumulator 105; the first accumulator 105 accumulates the first temporary sampling signal and the second temporary sampling signal to obtain a first accumulated signal, and the second accumulator 106 accumulates the third temporary sampling signal and the fourth temporary sampling signal to obtain a second accumulated signal.
The second accumulation signal is sent to a first input end of a third accumulator 109 through a sixth register 107, the first accumulation signal is sent to a second input end of the third accumulator 109 through a fifth register 108, and the third accumulator 109 accumulates the first accumulation signal and the second accumulation signal to obtain a target accumulation signal and outputs the target accumulation signal. By the mode, the signals at each moment are superposed once, so that the signals are amplified, and the signal resolution is improved. Wherein, for 8-bit binary digital sampling signals, after 2 times of superposition, 10-bit target accumulated signals are obtained. After being temporarily stored in the seventh register 110, the target accumulated signal is output to a data processing unit of the processor, and the data processing unit of the processor performs signal processing according to the first accumulated signal to obtain signal characteristics of the target accumulated signal, where the signal characteristics include amplitude, frequency, phase, frequency spectrum, and the like.
In the embodiment of the present invention, the oscilloscope includes a processor, and the first register 101, the second register 102, the third register 103, the fourth register 104, the first accumulator 105, the second accumulator 106, and the third accumulator 109 are all disposed in the processor, and may be implemented by using existing registers and accumulators in the processor. The processor may be an FPGA.
In an embodiment of the present invention, the signal processing system further includes:
the detection module is used for calculating the amplitude of the digital sampling signal;
and the determining module is used for determining whether the digital sampling signal is lower than a preset threshold value according to the amplitude value, and sending the first temporary storage sampling signal to the third register when the digital sampling signal is lower than the preset threshold value. The determining module is further configured to send the first temporary sampling signal to the processor when the amplitude is greater than or equal to the preset threshold;
and the processor performs signal processing according to the first temporary storage sampling signal to obtain the signal characteristic of the target accumulated signal.
That is, the embodiment of the present invention further sets the detection module and the determination module to determine whether the resolution or the signal strength of the digital sampling signal is too low. When the current is too low, signal amplification and noise filtration are carried out through the register accumulation module of the embodiment of the invention, so that the resolution is improved; and when the sampling signal is in the normal range, the data processing unit which directly sends the first temporary storage sampling signal to the processor can be selected to perform signal processing according to the first accumulation signal, so that the signal characteristic of the target accumulation signal is obtained.
According to the embodiment of the invention, the cascaded register and the cascaded accumulator are arranged, so that the digital sampling signal at the current moment and the digital sampling signal at the later moment can be accumulated, the effect of amplifying the digital sampling signal is realized, the digit of the digital sampling signal at each moment is increased, and the beneficial effect of improving the accuracy of the sampling data of the oscilloscope is finally realized.
Furthermore, the detection module and the determination module are arranged, so that the flexible adjustment can be performed on different sampling signals.
Figure 5 shows a schematic diagram of the structure of an oscilloscope embodiment of the present invention. As shown in fig. 5, the oscilloscope 10 includes the signal processing system 100 described above. The signal processing system 100 in the multiplexer 10 according to the embodiment of the present invention has all the features in the above embodiments, and is not described herein again.
According to the embodiment of the invention, the cascaded register and the cascaded accumulator are arranged, so that the digital sampling signal at the current moment and the digital sampling signal at the later moment can be accumulated, the effect of amplifying the digital sampling signal is realized, and the beneficial effect of improving the accuracy of the sampling data of the oscilloscope is finally realized.
Furthermore, the detection module and the determination module are arranged, so that the flexible adjustment can be performed on different sampling signals.
Fig. 6 is a schematic flow chart showing an embodiment of a signal processing method in an oscilloscope, the signal processing method being applied to the oscilloscope, and the signal processing method in the embodiment of the invention being based on the signal processing system in the above embodiment. As shown in fig. 6, the signal processing method includes:
step 110: the signal sampling module receives an analog signal and generates a digital sampling signal according to the analog signal.
Step 120: the method comprises the steps that a first register sequentially receives a first temporary storage sampling signal and a second temporary storage sampling signal, the first temporary storage sampling signal is respectively sent to a first accumulator and a second register, and the second temporary storage sampling signal is sent to the first accumulator; the first temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a first moment, and the second temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a second moment; the second time is an adjacent time after the first time.
Step 130: the second register receives the first temporary storage sampling signal and sends the first temporary storage sampling signal to the first accumulator.
Step 140: and the first accumulator accumulates the first temporary storage sampling signal and the second temporary storage sampling signal to obtain a first accumulated signal.
The signal processing method in the oscilloscope further comprises the following steps:
the third register sequentially receives a first temporary storage sampling signal, a second temporary storage sampling signal, a third temporary storage sampling signal and a fourth temporary storage sampling signal sent by the signal sampling module, sends the fourth temporary storage sampling signal to a second accumulator, and sends the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal to a fourth register; the third temporary storage sampling signal is the digital sampling signal with the preset digit generated by the signal sampling module at the third moment, and the fourth temporary storage sampling signal is the digital sampling signal with the preset digit generated by the signal sampling module at the fourth moment.
And the fourth register receives the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal sent by the third register, sends the third temporary storage sampling signal to the second accumulator, and sends the first temporary storage sampling signal and the second temporary storage sampling signal to the first register.
And the second accumulator accumulates the third temporary storage sampling signal and the fourth temporary storage sampling signal to obtain a second accumulated signal.
And the third accumulator accumulates the first accumulated signal and the second accumulated signal to obtain a target accumulated signal.
The specific steps of the signal processing method according to the embodiment of the present invention are the same as the working process of the signal processing system in the above method embodiment, and are not described herein again.
According to the embodiment of the invention, the cascaded register and the cascaded accumulator are arranged, so that the digital sampling signal at the current moment and the digital sampling signal at the later moment can be accumulated, the effect of amplifying the digital sampling signal is realized, and the beneficial effect of improving the accuracy of the sampling data of the oscilloscope is finally realized.
Furthermore, the detection module and the determination module are arranged, so that the flexible adjustment can be performed on different sampling signals.
The algorithms or displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general purpose systems may also be used with the teachings herein. The required structure for constructing such a system will be apparent from the description above. In addition, embodiments of the present invention are not directed to any particular programming language. It is appreciated that a variety of programming languages may be used to implement the teachings of the present invention as described herein, and any descriptions of specific languages are provided above to disclose the best mode of the invention.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the embodiments of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the invention and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names. The steps in the above embodiments should not be construed as limiting the order of execution unless specified otherwise.
Claims (10)
1. A signal processing system in an oscilloscope is characterized in that the signal processing system is applied to the oscilloscope and comprises a signal sampling module and at least one register accumulation module; the register accumulation module comprises a first register, a second register and a first accumulator;
the signal sampling module is used for receiving an analog signal and generating a digital sampling signal according to the analog signal;
the first register is used for sequentially receiving a first temporary storage sampling signal and a second temporary storage sampling signal, respectively sending the first temporary storage sampling signal to the first accumulator and the second register, and sending the second temporary storage sampling signal to the first accumulator; the first temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a first moment, and the second temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a second moment; the second moment is adjacent moment after the first moment;
the second register is used for receiving the first temporary storage sampling signal and sending the first temporary storage sampling signal to the first accumulator;
the first accumulator is configured to accumulate the first temporary storage sampling signal and the second temporary storage sampling signal to obtain a first accumulated signal.
2. The signal processing system of claim 1, further comprising: a third register, a fourth register, a second accumulator and a third accumulator;
the third register is used for sequentially receiving the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal sent by the signal sampling module, sending the fourth temporary storage sampling signal to the second accumulator, and sending the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal to the fourth register; the third temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a third moment, and the fourth temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a fourth moment;
the fourth register is configured to receive the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal sent by the third register, send the third temporary storage sampling signal to the second accumulator, and send the first temporary storage sampling signal and the second temporary storage sampling signal to the first register;
the second accumulator is used for accumulating the third temporary storage sampling signal and the fourth temporary storage sampling signal to obtain a second accumulated signal;
the third accumulator is configured to accumulate the first accumulated signal and the second accumulated signal to obtain a target accumulated signal.
3. The signal processing system of claim 2, wherein the oscilloscope comprises a processor, and wherein the first register, the second register, the third register, the fourth register, the first accumulator, the second accumulator, and the third accumulator are disposed in the processor;
the processor is further configured to perform signal processing according to the target accumulated signal to obtain a signal characteristic of the target accumulated signal.
4. The signal processing system of claim 3 wherein clock excitation signals of the first register, second register, third register, fourth register, first accumulator, second accumulator, and third accumulator are the same.
5. The signal processing system of claim 2, further comprising:
the detection module is used for calculating the amplitude of the digital sampling signal;
and the determining module is used for determining whether the digital sampling signal is lower than a preset threshold value according to the amplitude value, and sending the first temporary storage sampling signal to the third register when the digital sampling signal is lower than the preset threshold value.
6. The signal processing system of claim 5, wherein the determining module is further configured to send the first temporary sample signal to the processor when the amplitude value is greater than or equal to the preset threshold value;
and the processor performs signal processing according to the first temporary storage sampling signal to obtain the signal characteristic of the target accumulated signal.
7. An oscilloscope comprising a signal processing system according to any one of claims 1 to 6.
8. A method of signal processing in an oscilloscope, comprising the steps of:
the signal sampling module receives an analog signal and generates a digital sampling signal according to the analog signal;
the method comprises the steps that a first register sequentially receives a first temporary storage sampling signal and a second temporary storage sampling signal, the first temporary storage sampling signal is respectively sent to a first accumulator and a second register, and the second temporary storage sampling signal is sent to the first accumulator; the first temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a first moment, and the second temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a second moment; the second moment is adjacent moment after the first moment;
the second register receives the first temporary storage sampling signal and sends the first temporary storage sampling signal to the first accumulator;
and the first accumulator accumulates the first temporary storage sampling signal and the second temporary storage sampling signal to obtain a first accumulated signal.
9. The method of claim 8, further comprising the steps of:
the third register sequentially receives a first temporary storage sampling signal, a second temporary storage sampling signal, a third temporary storage sampling signal and a fourth temporary storage sampling signal sent by the signal sampling module, sends the fourth temporary storage sampling signal to a second accumulator, and sends the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal to a fourth register; the third temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a third moment, and the fourth temporary storage sampling signal is the digital sampling signal with a preset number of bits generated by the signal sampling module at a fourth moment;
the fourth register receives the first temporary storage sampling signal, the second temporary storage sampling signal, the third temporary storage sampling signal and the fourth temporary storage sampling signal sent by the third register, sends the third temporary storage sampling signal to the second accumulator, and sends the first temporary storage sampling signal and the second temporary storage sampling signal to the first register;
the second accumulator accumulates the third temporary storage sampling signal and the fourth temporary storage sampling signal to obtain a second accumulated signal;
and the third accumulator accumulates the first accumulated signal and the second accumulated signal to obtain a target accumulated signal.
10. The method of claim 9, wherein a processor performs signal processing based on the target accumulated signal to obtain a signal characteristic of the target accumulated signal.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022127560A1 (en) * | 2020-12-15 | 2022-06-23 | 深圳市道通科技股份有限公司 | Signal processing system in oscilloscope, oscilloscope and signal processing method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050024249A1 (en) * | 2002-06-20 | 2005-02-03 | Pavicic Mark J. | System for digitizing transient signals with waveform accumulator |
| CN103034470A (en) * | 2011-09-30 | 2013-04-10 | 上海华魏光纤传感技术有限公司 | Data acquisition accumulator with fast Fourier transform (FFT) filtering function and implement method thereof |
| CN108181492A (en) * | 2018-01-05 | 2018-06-19 | 深圳市道通科技股份有限公司 | A kind of oscilloscope signal processing method, device and oscillograph |
| US10491234B1 (en) * | 2018-06-22 | 2019-11-26 | Texas Instruments Incorporated | Configurable oversampling for an analog-to-digital converter |
| CN111092714A (en) * | 2019-12-10 | 2020-05-01 | 中国科学院微电子研究所 | High-speed signal clock recovery method and device |
| CN111835354A (en) * | 2020-08-18 | 2020-10-27 | 华润半导体（深圳）有限公司 | Digital decimation filter and filtering method, and analog-to-digital converter |
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050024249A1 (en) * | 2002-06-20 | 2005-02-03 | Pavicic Mark J. | System for digitizing transient signals with waveform accumulator |
| CN103034470A (en) * | 2011-09-30 | 2013-04-10 | 上海华魏光纤传感技术有限公司 | Data acquisition accumulator with fast Fourier transform (FFT) filtering function and implement method thereof |
| CN108181492A (en) * | 2018-01-05 | 2018-06-19 | 深圳市道通科技股份有限公司 | A kind of oscilloscope signal processing method, device and oscillograph |
| US10491234B1 (en) * | 2018-06-22 | 2019-11-26 | Texas Instruments Incorporated | Configurable oversampling for an analog-to-digital converter |
| CN111092714A (en) * | 2019-12-10 | 2020-05-01 | 中国科学院微电子研究所 | High-speed signal clock recovery method and device |
| CN111835354A (en) * | 2020-08-18 | 2020-10-27 | 华润半导体（深圳）有限公司 | Digital decimation filter and filtering method, and analog-to-digital converter |
Non-Patent Citations (3)
| Title |
|---|
| YANG, JUN; HUANG, BO; ZHANG, DAWEN; DAI, ZHONGDONG;: "Bit Length Selection in GNSS Receiver Design", 2ND CHINA SATELLITE NAVIGATION CONFERENCE (CSNC 2011), 20 May 2011 (2011-05-20) * |
| 刘胜永;黄庆华;: "嵌入式实时信号采集与处理系统实现方案", 微计算机信息, no. 32, 30 November 2008 (2008-11-30) * |
| 苏晓晓;: "数字化接收机的FPGA设计", 中国优秀硕士学位论文全文数据库 (工程科技Ⅱ辑), no. 04, 15 April 2014 (2014-04-15) * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022127560A1 (en) * | 2020-12-15 | 2022-06-23 | 深圳市道通科技股份有限公司 | Signal processing system in oscilloscope, oscilloscope and signal processing method |
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