WO2017163890A1 - Solid state imaging apparatus, method for driving solid state imaging apparatus, and electronic device - Google Patents

Solid state imaging apparatus, method for driving solid state imaging apparatus, and electronic device Download PDF

Info

Publication number
WO2017163890A1
WO2017163890A1 PCT/JP2017/009366 JP2017009366W WO2017163890A1 WO 2017163890 A1 WO2017163890 A1 WO 2017163890A1 JP 2017009366 W JP2017009366 W JP 2017009366W WO 2017163890 A1 WO2017163890 A1 WO 2017163890A1
Authority
WO
WIPO (PCT)
Prior art keywords
unit
charge
signal
conversion unit
pixel
Prior art date
Application number
PCT/JP2017/009366
Other languages
French (fr)
Japanese (ja)
Inventor
頼人 坂野
元展 鳥居
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Publication of WO2017163890A1 publication Critical patent/WO2017163890A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50Control of the SSIS exposure
    • H04N25/57Control of the dynamic range
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/76Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present technology relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device, and more particularly, to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device that can expand a dynamic range.
  • a time division method is known in which images are taken in time division with different sensitivities and a plurality of images taken in time division are combined.
  • a space division method in which a light receiving element having different sensitivity is provided and a dynamic range is expanded by combining a plurality of images captured by light receiving elements having different sensitivities (see, for example, Patent Document 1). .
  • the dynamic range can be expanded by increasing the number of divisions.
  • the image quality is deteriorated due to the occurrence of artifacts or a decrease in resolution.
  • the present technology makes it possible to expand the dynamic range of the solid-state imaging device while suppressing deterioration in image quality.
  • the solid-state imaging device includes a pixel array unit in which a plurality of unit pixels are arranged, and a driving unit that controls the operation of the unit pixels.
  • the first electric charge generated by the first photoelectric conversion unit is converted into the first electric charge.
  • a first data signal stored in the voltage converter, and a second data in the state where the first charge is stored in a region where the potentials of the first charge voltage converter and the second charge voltage converter are combined.
  • the drive unit includes a first reset signal in a state where the first charge voltage conversion unit is reset, and a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined. It is possible to control to read out the second reset signal in a state where is reset.
  • the third charge is stored in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined.
  • a third reset signal in a state where the region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined is reset. Can be controlled.
  • a first difference signal that is a difference between the first data signal and the first reset signal; a second difference signal that is a difference between the second data signal and the second reset signal; and A signal processing unit that generates a third differential signal that is a difference between the third data signal and the third reset signal can be further provided.
  • the signal processing unit uses the first difference signal as a pixel signal of the unit pixel, and the value of the first difference signal Exceeds the first threshold and the value of the second difference signal is equal to or less than a predetermined second threshold, the second difference signal is used as a pixel signal of the unit pixel, and the second difference signal When the value of exceeds the second threshold, the third difference signal can be used as the pixel signal of the unit pixel.
  • the signal processing unit includes the first difference signal, the first difference signal at a combination ratio set based on at least one value of the first difference signal, the second difference signal, and the third difference signal.
  • a pixel signal of the unit pixel can be generated by combining the second difference signal and the third difference signal.
  • the drive unit reads the second reset signal in a state where the region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined is reset, and then the third charge
  • the first reset signal is read out in a state in which the transfer gate portion is turned off, and then the first transfer gate portion is turned on to convert the first charge into the first charge-voltage conversion.
  • the first data signal can be read out in a state where the data is transferred to a part, and then the second data signal can be read out in a state where the third transfer gate part is turned on.
  • the third charge is stored in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined.
  • the data signal can be controlled to be read out.
  • the unit pixel is formed under a fourth transfer gate unit that transfers charges from the second photoelectric conversion unit to the charge storage unit, and under a gate electrode of the fourth transfer gate unit, An overflow path for transferring charges overflowing from the photoelectric conversion unit to the charge storage unit may be further provided.
  • the second photoelectric conversion unit and the charge storage unit can be connected without a transfer gate unit.
  • the counter electrode of the charge storage unit is connected to a variable voltage power source, and the drive unit has a period of reading a signal based on the charge stored in the charge storage unit in a period of storing charge in the charge storage unit, The voltage applied to the counter electrode of the charge storage portion can be lowered.
  • the driving method of the solid-state imaging device includes a pixel array unit in which a plurality of unit pixels are arranged, and a driving unit that controls the operation of the unit pixels.
  • a second transfer gate unit that couples the potential of the charge storage unit, and a third transfer gate unit that couples the potential of the first charge voltage conversion unit and the second charge voltage conversion unit.
  • the imaging device uses the first charge generated by the first photoelectric conversion unit.
  • the first charge is accumulated in a region where the first data signal accumulated in the first charge-voltage converter and the potentials of the first charge-voltage converter and the second charge-voltage converter are combined.
  • Control is performed to read out the second data signal in the state and the third data signal based on the second charge generated by the second photoelectric conversion unit.
  • An electronic apparatus includes a pixel array unit in which a plurality of unit pixels are arranged, and a drive unit that controls the operation of the unit pixel, and the unit pixel includes a first photoelectric conversion unit.
  • a second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit, a charge accumulation unit that accumulates charges generated by the second photoelectric conversion unit, a first charge voltage conversion unit, A second charge-voltage converter, a first transfer gate that transfers charges from the first photoelectric converter to the first charge-voltage converter, the second charge-voltage converter, and the charge storage
  • a second transfer gate unit that couples the potentials of the first and second charge gates, and a third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter.
  • the first charge generated by the photoelectric conversion unit is accumulated in the first charge voltage conversion unit.
  • a first data signal in a stored state a second data signal in a state in which the first charge is accumulated in a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined, and
  • a solid-state imaging device that controls to read out a third data signal based on the second charge generated by the second photoelectric conversion unit, and a signal processing device that processes a signal from the solid-state imaging device.
  • the first data signal in a state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first data signal, A second data signal in a state where the first charge is accumulated in a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined, and a second data signal generated by the second photoelectric conversion unit.
  • a third data signal based on the charge of 2 is read out.
  • the present technology it is possible to expand the dynamic range of the solid-state imaging device while suppressing deterioration in image quality.
  • FIG. 1 is a system configuration diagram illustrating an outline of a configuration of a CMOS image sensor to which the present technology is applied. It is a system configuration
  • FIG. 6 is a timing chart for explaining a second operation example at the start of exposure of the unit pixel of FIG. 4.
  • FIG. 5 is a timing chart for explaining a second operation example at the time of reading the unit pixel of FIG. 4.
  • FIG. It is a circuit diagram showing an example of composition of a unit pixel in a 2nd embodiment of this art.
  • 10 is a timing chart for explaining an operation example at the start of exposure of the unit pixel of FIG. 9.
  • 10 is a timing chart for explaining an operation example at the time of reading the unit pixel of FIG. 9.
  • FIG. 13 is a timing chart for explaining an operation example at the time of reading the unit pixel of FIG. 12. It is a circuit diagram showing an example of composition of a unit pixel in a 4th embodiment of this art. 16 is a timing chart for explaining an operation example at the start of exposure of the unit pixel in FIG. 15. 16 is a timing chart for explaining an operation example at the time of reading the unit pixel of FIG. 15. It is an incident light quantity-output characteristic diagram for explanation of signal processing. It is a figure which shows the usage example of a solid-state imaging device. It is a block diagram which shows the structural example of an electronic device. It is a block diagram which shows an example of a schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of a vehicle exterior information detection part and an imaging part.
  • FIG. 1 is a system configuration diagram showing an outline of the configuration of a solid-state imaging device to which the present technology is applied, for example, a CMOS image sensor which is a kind of XY address type solid-state imaging device.
  • the CMOS image sensor is an image sensor created by applying or partially using a CMOS process.
  • a CMOS image sensor 10 includes a pixel array unit 11 formed on a semiconductor substrate (chip) (not shown), and a peripheral circuit unit integrated on the same semiconductor substrate as the pixel array unit 11. It has a configuration.
  • the peripheral circuit unit includes, for example, a vertical drive unit 12, a column processing unit 13, a horizontal drive unit 14, and a system control unit 15.
  • the CMOS image sensor 10 further includes a signal processing unit 18 and a data storage unit 19.
  • the signal processing unit 18 and the data storage unit 19 may be mounted on the same substrate as the CMOS image sensor 10 or may be disposed on a different substrate from the CMOS image sensor 10.
  • Each processing of the signal processing unit 18 and the data storage unit 19 may be processing by an external signal processing unit provided on a substrate different from the CMOS image sensor 10, for example, a DSP (Digital Signal Processor) circuit or software. Absent.
  • DSP Digital Signal Processor
  • the pixel array unit 11 includes unit pixels (hereinafter also simply referred to as “pixels”) having a photoelectric conversion unit that generates and accumulates charges according to the received light amount in the row direction and the column direction, that is, The configuration is two-dimensionally arranged in a matrix.
  • the row direction refers to the pixel arrangement direction (that is, the horizontal direction) of the pixel row
  • the column direction refers to the pixel arrangement direction (that is, the vertical direction) of the pixel column. Details of the specific circuit configuration and pixel structure of the unit pixel will be described later.
  • the pixel drive lines 16 are wired along the row direction for each pixel row, and the vertical signal lines 17 are wired along the column direction for each pixel column in the matrix pixel array. .
  • the pixel drive line 16 transmits a drive signal for driving when reading a signal from the pixel.
  • the pixel drive line 16 is shown as one wiring, but is not limited to one.
  • One end of the pixel drive line 16 is connected to an output end corresponding to each row of the vertical drive unit 12.
  • the vertical drive unit 12 is configured by a shift register, an address decoder, and the like, and drives each pixel of the pixel array unit 11 at the same time or in units of rows. That is, the vertical drive unit 12 constitutes a drive unit that controls the operation of each pixel of the pixel array unit 11 together with the system control unit 15 that controls the vertical drive unit 12.
  • the vertical drive unit 12 is not shown in the figure for its specific configuration, but generally has a configuration having two scanning systems, a reading scanning system and a sweeping scanning system.
  • the readout scanning system selectively scans the unit pixels of the pixel array unit 11 in units of rows in order to read out signals from the unit pixels.
  • the signal read from the unit pixel is an analog signal.
  • the sweep-out scanning system performs sweep-out scanning on the readout line on which readout scanning is performed by the readout scanning system prior to the readout scanning by the exposure time.
  • a so-called electronic shutter operation is performed by sweeping (resetting) unnecessary charges by the sweep scanning system.
  • the electronic shutter operation refers to an operation in which the electric charge in the photoelectric conversion unit is discarded and exposure is newly started (charge accumulation is started).
  • the signal read out by the readout operation by the readout scanning system corresponds to the amount of light received after the immediately preceding readout operation or electronic shutter operation.
  • the period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the charge exposure period in the unit pixel.
  • a signal output from each unit pixel of the pixel row selectively scanned by the vertical driving unit 12 is input to the column processing unit 13 through each of the vertical signal lines 17 for each pixel column.
  • the column processing unit 13 performs predetermined signal processing on signals output from the pixels in the selected row through the vertical signal line 17 for each pixel column of the pixel array unit 11, and temporarily outputs the pixel signals after the signal processing. Hold on.
  • the column processing unit 13 performs at least noise removal processing, for example, CDS (Correlated Double Sampling) processing or DDS (Double Data Sampling) processing as signal processing.
  • CDS Correlated Double Sampling
  • DDS Double Data Sampling
  • the CDS process removes pixel-specific fixed pattern noise such as reset noise and threshold variation of amplification transistors in the pixel.
  • the column processing unit 13 may have, for example, an AD (analog-digital) conversion function to convert an analog pixel signal into a digital signal and output the digital signal.
  • AD analog-digital
  • the horizontal drive unit 14 includes a shift register, an address decoder, and the like, and sequentially selects unit circuits corresponding to the pixel columns of the column processing unit 13. By the selective scanning by the horizontal driving unit 14, pixel signals subjected to signal processing for each unit circuit in the column processing unit 13 are sequentially output.
  • the system control unit 15 includes a timing generator that generates various timing signals, and the vertical driving unit 12, the column processing unit 13, and the horizontal driving unit 14 based on various timings generated by the timing generator. Drive control is performed.
  • the signal processing unit 18 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing on the pixel signal output from the column processing unit 13.
  • the data storage unit 19 temporarily stores data necessary for the signal processing in the signal processing unit 18.
  • CMOS image sensor 10 to which the present technology is applied is not limited to the system configuration described above. Examples of other system configurations include the following system configurations.
  • the data storage unit 19 is arranged at the subsequent stage of the column processing unit 13, and the pixel signal output from the column processing unit 13 is supplied to the signal processing unit 18 via the data storage unit 19.
  • a CMOS image sensor 10A having a system configuration.
  • the column processing unit 13 is provided with an AD conversion function for performing AD conversion for each column or a plurality of columns of the pixel array unit 11, and a data storage unit is provided for the column processing unit 13. 19 and a CMOS image sensor 10B having a system configuration in which the signal processing unit 18 is provided in parallel.
  • FIG. 4 is a circuit diagram illustrating a configuration example of the unit pixel 100A arranged in the pixel array unit 11 of FIGS.
  • the unit pixel 100A includes a first photoelectric conversion unit 101a, a second photoelectric conversion unit 101b, a first transfer gate unit 102a to a fourth transfer gate unit 102d, a reset gate unit 103, a charge storage unit 104, and a first FD (floating diffusion) unit.
  • 105 a a second FD (floating diffusion) portion 105 b, an amplification transistor 106, and a selection transistor 107.
  • a plurality of drive lines are wired for each pixel row as the pixel drive lines 16 in FIGS. 1 to 3 with respect to the unit pixel 100A, for example.
  • Various drive signals TGL, FCG, FDG, TGS, RST, and SEL are supplied from the vertical drive unit 12 of FIGS. 1 to 3 through a plurality of drive lines. These drive signals are pulses in which each of the transistors of the unit pixel 100A is an NMOS transistor, so that a high level (for example, power supply voltage VDD) is an active state and a low level (for example, a negative potential) is inactive. Signal.
  • VDD power supply voltage
  • the first photoelectric conversion unit 101a is composed of, for example, a PN junction photodiode.
  • the 1st photoelectric conversion part 101a produces
  • the second photoelectric conversion unit 101b is formed of, for example, a PN junction photodiode, similarly to the first photoelectric conversion unit 101a.
  • the second photoelectric conversion unit 101b generates and accumulates charges corresponding to the received light amount.
  • the first photoelectric conversion unit 101a Comparing the first photoelectric conversion unit 101a and the second photoelectric conversion unit 101b, the first photoelectric conversion unit 101a has a larger light receiving surface area and higher sensitivity, and the second photoelectric conversion unit 101b has a light receiving surface area. Is narrow and has low sensitivity.
  • the first transfer gate unit 102a is connected between the first photoelectric conversion unit 101a and the first FD unit 105a.
  • a drive signal TGL is applied to the gate electrode of the first transfer gate portion 102a.
  • the drive signal TGL becomes active, the first transfer gate unit 102a becomes conductive, and the charge accumulated in the first photoelectric conversion unit 101a is transferred to the first FD unit 105a via the first transfer gate unit 102a. Is done.
  • the second transfer gate portion 102b is connected between the charge storage portion 104 and the second FD portion 105b.
  • a drive signal FCG is applied to the gate electrode of the second transfer gate portion 102b.
  • the drive signal FCG becomes active, the second transfer gate portion 102b becomes conductive, and the potentials of the charge storage portion 104 and the second FD portion 105b are coupled.
  • the third transfer gate unit 102c is connected between the first FD unit 105a and the second FD unit 105b.
  • a drive signal FDG is applied to the gate electrode of the third transfer gate portion 102c.
  • the third transfer gate portion 102c becomes conductive, and the potentials of the first FD portion 105a and the second FD portion 105b are coupled.
  • the fourth transfer gate unit 102d is connected between the second photoelectric conversion unit 101b and the charge storage unit 104.
  • a drive signal TGS is applied to the gate electrode of the fourth transfer gate portion 102d.
  • the fourth transfer gate unit 102d becomes conductive, and the charge accumulated in the second photoelectric conversion unit 101b is transferred to the charge accumulation unit 104 via the fourth transfer gate unit 102d. Transferred.
  • the lower part of the gate electrode of the fourth transfer gate portion 102d has a slightly deep potential, and the charge that exceeds the saturation charge amount of the second photoelectric conversion portion 101b and overflows from the second photoelectric conversion portion 101b is stored in the charge storage portion.
  • An overflow path to be transferred to 104 is formed.
  • the overflow path formed below the gate electrode of the fourth transfer gate portion 102d is simply referred to as the overflow path of the fourth transfer gate portion 102d.
  • the reset gate unit 103 is connected between the power supply VDD that supplies the power supply voltage VDD and the second FD unit 105b.
  • a drive signal RST is applied to the gate electrode of the reset gate portion 103.
  • the reset gate unit 103 becomes conductive. Thereby, for example, the potential of the region where the potentials of the first FD unit 105a and the second FD unit 105b are combined, or the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is Reset to the level of voltage VDD.
  • the charge storage unit 104 is made of a capacitor, for example, and the counter electrode of the charge storage unit 104 is connected between the power supply VDD.
  • the charge storage unit 104 stores the charge transferred from the second photoelectric conversion unit 101b.
  • the first FD unit 105a and the second FD unit 105b convert the charge into a voltage signal and output it.
  • the amplification transistor 106 has a gate electrode connected to the first FD unit 105a, a drain electrode connected to the power supply VDD, and a readout circuit that reads out the charge held in the first FD unit 105a, a so-called source follower circuit input unit and Become. That is, the amplification transistor 106 forms a source follower circuit with the constant current source 108 connected to one end of the vertical signal line 17 by connecting the source electrode to the vertical signal line 17 via the selection transistor 107.
  • the selection transistor 107 is connected between the source electrode of the amplification transistor 106 and the vertical signal line 17.
  • a drive signal SEL is applied to the gate electrode of the selection transistor 107.
  • the drive signal SEL becomes active, the selection transistor 107 becomes conductive and the unit pixel 100A becomes selected.
  • the pixel signal output from the amplification transistor 106 is output to the vertical signal line 17 via the selection transistor 107.
  • each drive signal is in an active state, each drive signal is turned on, and each drive signal is in an inactive state, each drive signal is also turned off.
  • each gate portion or each transistor is turned on, each gate portion or each transistor may be turned on, and each gate portion or each transistor is turned off. It is also said that the transistor is turned off.
  • FIG. 5 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, TGS, and FCG.
  • the horizontal synchronization signal XHS is input, and the exposure processing of the unit pixel 100A starts.
  • the drive signals RST and FDG are turned on, and the reset gate unit 103 and the third transfer gate unit 102c are turned on.
  • the potentials of the first FD portion 105a and the second FD portion 105b are coupled, and the potential of the coupled region is reset to the level of the power supply voltage VDD.
  • the drive signal TGL is turned on, and the first transfer gate unit 102a is turned on.
  • the electric charge accumulated in the first photoelectric conversion unit 101a is transferred to the region where the potentials of the first FD unit 105a and the second FD unit 105b are coupled via the first transfer gate unit 102a.
  • the unit 101a is reset.
  • the drive signal TGL is turned off, and the first transfer gate unit 102a is turned off. Thereby, accumulation of electric charges in the first photoelectric conversion unit 101a is started, and an exposure period is started.
  • the drive signals TGS and FCG are turned on, and the fourth transfer gate unit 102d and the second transfer gate unit 102b are turned on.
  • the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are coupled.
  • the charge accumulated in the second photoelectric conversion unit 101b is transferred to the coupled region via the fourth transfer gate unit 102d, and the second photoelectric conversion unit 101b and the charge accumulation unit 104 are reset.
  • the drive signal TGS is turned off, and the fourth transfer gate unit 102d is turned off. Thereby, accumulation of electric charges in the second photoelectric conversion unit 101b is started.
  • the drive signal FCG is turned off, and the second transfer gate unit 102b is turned off.
  • the charge accumulation unit 104 starts accumulating charges that overflow from the second photoelectric conversion unit 101b and are transferred through the overflow path of the fourth transfer gate unit 102d.
  • the drive signals RST and FDG are turned off, and the reset gate unit 103 and the third transfer gate unit 102c are turned off.
  • the horizontal synchronization signal XHS is input.
  • FIG. 6 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, TGS, and FCG.
  • the horizontal synchronization signal XHS is input, and the readout period of the unit pixel 100A starts.
  • the drive signals SEL, RST, and FDG are turned on, and the selection transistor 107, the reset gate unit 103, and the third transfer gate unit 102c are turned on.
  • the unit pixel 100A is selected.
  • the potentials of the first FD portion 105a and the second FD portion 105b are combined, and the potential of the combined region is reset to the level of the power supply voltage VDD.
  • the drive signal RST is turned off, and the reset gate unit 103 is turned off.
  • a signal NH2 based on the potential of the region where the potentials of the first FD portion 105a and the second FD portion 105b are combined is a vertical signal via the amplification transistor 106 and the selection transistor 107.
  • the signal NH2 is a signal based on a potential in a reset state of a region where the potentials of the first FD unit 105a and the second FD unit 105b are combined.
  • the signal NH2 is also referred to as a high-sensitivity reset signal NH2.
  • the drive signal FDG is turned off and the third transfer gate unit 102c is turned off. Thereby, the potential coupling between the first FD part 105a and the second FD part 105b is canceled.
  • the signal NH1 based on the potential of the first FD unit 105a is output to the vertical signal line 17 via the amplification transistor 106 and the selection transistor 107.
  • the signal NH1 is a signal based on the potential in the reset state of the first FD unit 105a.
  • the signal NH1 is also referred to as a high-sensitivity reset signal NH1.
  • the drive signal TGL is turned on, and the first transfer gate unit 102a is turned on. Thereby, the charge generated and accumulated in the first photoelectric conversion unit 101a during the exposure period is transferred to the first FD unit 105a via the first transfer gate unit 102a.
  • the drive signal TGL is turned off, and the first transfer gate unit 102a is turned off. Thereby, the transfer of charge from the first photoelectric conversion unit 101a to the first FD unit 105a is stopped.
  • a signal SH1 based on the potential of the first FD unit 105a is output to the vertical signal line 17 via the amplification transistor 106 and the selection transistor 107.
  • the signal SH1 is a signal based on the potential of the first FD unit 105a in a state where the electric charge generated and accumulated in the first photoelectric conversion unit 101a during the exposure period is accumulated in the first FD unit 105a.
  • the signal SH1 is also referred to as a high sensitivity data signal SH1.
  • the drive signals FDG and TGL are turned on, and the third transfer gate unit 102c and the first transfer gate unit 102a are turned on.
  • the potentials of the first FD unit 105a and the second FD unit 105b are combined, and the charge remaining in the first photoelectric conversion unit 101a without being transferred between the time t25 and the time t26 passes through the first transfer gate unit 102a.
  • the high-sensitivity data signal SH1 since the capacity for charge-voltage conversion is small with respect to the amount of charge handled, there is no problem even if charges remain in the first photoelectric conversion unit 101a.
  • the charge remaining in the first photoelectric conversion unit 101a only needs to be transferred when the high-sensitivity data signal SH2 is read, and the charge is not damaged in the first photoelectric conversion unit 101a.
  • the drive signal TGL is turned off, and the first transfer gate unit 102a is turned off.
  • the first transfer gate unit 102a is turned off.
  • transfer of charges from the first photoelectric conversion unit 101a to the region where the potentials of the first FD unit 105a and the second FD unit 105b are combined is stopped.
  • the signal SH2 based on the potential of the region where the potentials of the first FD portion 105a and the second FD portion 105b are combined is a vertical signal via the amplification transistor 106 and the selection transistor 107. Output on line 17.
  • the signal SH2 is generated by the first photoelectric conversion unit 101a during the exposure period, and the accumulated electric charge is accumulated in the region where the potentials of the first FD unit 105a and the second FD unit 105b are combined. It becomes a signal based on.
  • the capacity for charge-voltage conversion at the time of reading the signal SH2 is the capacity of the first FD portion 105a and the second FD portion 105b, and is larger than that at the time of reading the high sensitivity data signal SH1 at time tc.
  • the signal SH2 is also referred to as a high-sensitivity data signal SH2.
  • the drive signal RST is turned on and the reset gate unit 103 is turned on.
  • the potential of the region where the potentials of the first FD portion 105a and the second FD portion 105b are combined is reset to the level of the power supply voltage VDD.
  • the drive signal SEL is turned off and the selection transistor 107 is turned off.
  • the unit pixel 100A enters a non-selected state.
  • the drive signal RST is turned off, and the reset gate unit 103 is turned off.
  • the drive signals SEL, TGS, and FCG are turned on, and the selection transistor 107, the fourth transfer gate unit 102d, and the second transfer gate unit 102b are turned on.
  • the unit pixel 100A is selected.
  • the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined, and the charges stored in the second photoelectric conversion unit 101b are transferred to the combined region.
  • charges accumulated in the second photoelectric conversion unit 101b and the charge accumulation unit 104 during the exposure period are accumulated in the combined region.
  • the drive signal TGS is turned off, and the fourth transfer gate unit 102d is turned off. Thereby, the transfer of charge from the second photoelectric conversion unit 101b is stopped.
  • the signal SL based on the potential of the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is selected by the amplification transistor 106 and the selection transistor 106.
  • the signal is output to the vertical signal line 17 through the transistor 107.
  • the signal SL is generated by the second photoelectric conversion unit 101b during the exposure period, and the charges accumulated in the second photoelectric conversion unit 101b and the charge storage unit 104 are converted into the charge storage unit 104, the first FD unit 105a, and the second FD.
  • the signal is based on the potential of the coupled region in the state where the potential of the portion 105b is accumulated in the coupled region. Therefore, the capacity for charge-voltage conversion at the time of reading the signal SL is a total capacity of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b. This capacity is larger than when reading the high sensitivity data signal SH1 at time tc and when reading the high sensitivity data signal SH2 at time td.
  • the signal SL is also referred to as a low-sensitivity data signal SL.
  • the drive signal RST is turned on and the reset gate unit 103 is turned on. Thereby, the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is reset.
  • the drive signals SEL and FCG are turned off, and the selection transistor 107 and the second transfer gate unit 102b are turned off.
  • the unit pixel 100A enters a non-selected state.
  • the potential of the charge storage unit 104 is separated from the potentials of the first FD unit 105a and the second FD unit 105b.
  • the drive signal RST is turned off, and the reset gate unit 103 is turned off.
  • the drive signals SEL and FCG are turned on, and the selection transistor 107 and the second transfer gate unit 102b are turned on. As a result, the unit pixel 100A is selected. Further, the potential of the charge storage unit 104 is combined with the potentials of the first FD unit 105a and the second FD unit 105b.
  • the signal NL based on the potential of the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is selected from the amplification transistor 106 and the selection transistor 106.
  • the signal is output to the vertical signal line 17 through the transistor 107.
  • This signal NL is a signal based on a potential in a reset state of a region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined.
  • the signal NL is also referred to as a low-sensitivity reset signal NL.
  • the drive signals SEL, FDG, and FCG are turned off, and the selection transistor 107, the third transfer gate unit 102c, and the second transfer gate unit 102b are turned off.
  • the unit pixel 100A enters a non-selected state. Further, the potential coupling of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b is eliminated.
  • the horizontal synchronization signal XHS is input, and the readout period of the pixel signal of the unit pixel 100A ends.
  • the drive signal RST does not need to be turned on at time t22 as in the example of FIG. 6 because the drive signal RST is kept turned on at the start of exposure. Further, the drive signal RST is kept on after being turned on at time t34.
  • FIG. 9 is a circuit diagram illustrating a configuration example of a unit pixel 100B that is a modification of the unit pixel 100A of FIG.
  • portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • the fourth transfer gate portion 102d is deleted. That is, the second photoelectric conversion unit 101b is directly connected to the charge storage unit 104 without passing through the fourth transfer gate unit 102d.
  • FIG. 10 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, and FCG.
  • the drive signal FCG is turned on, and the second transfer gate unit 102b is turned on.
  • the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are coupled.
  • the charge accumulated in the charge accumulation unit 104 is transferred to the coupled region via the fourth transfer gate unit 102d, and the second photoelectric conversion unit 101b and the charge accumulation unit 104 are reset.
  • the drive signal FCG is turned off, and the second transfer gate unit 102b is turned off.
  • the charge accumulation unit 104 starts accumulating the charge transferred from the second photoelectric conversion unit 101b.
  • time t7 and time t8 operations similar to those at time t8 and time t9 in FIG. 5 are performed.
  • FIG. 11 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, and FCG.
  • the drive signals SEL and FCG are turned on, and the selection transistor 107 and the second transfer gate unit 102b are turned on.
  • the unit pixel 100A is selected.
  • the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined, and the charges generated in the second photoelectric conversion unit 101b and accumulated in the charge storage unit 104 during the exposure period are Accumulated in the combined area.
  • the fourth transfer gate portion 102d is deleted, the area efficiency of the arrangement of each element constituting the unit pixel 100B is improved. For example, it is possible to increase the area of the light receiving surface of the first photoelectric conversion unit 101a and improve the sensitivity of the first photoelectric conversion unit 101a.
  • FIG. 12 is a circuit diagram illustrating a configuration example of the unit pixel 100C arranged in the pixel array unit 11 of FIGS.
  • portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • the connection position of the counter electrode of the charge storage unit 104 is different. That is, the unit pixel 100C is different in that the counter electrode of the charge storage unit 104 is connected to the variable voltage power supply FCVDD.
  • the power supply voltage FCVDD of the variable voltage power supply FCVDD is set to, for example, a high level voltage FCH or a low level voltage FCL.
  • the voltage FCH is set to substantially the same level as the power supply voltage VDD
  • the voltage FCL is set to a predetermined intermediate potential.
  • FIG. 13 shows a timing chart of the horizontal synchronization signal XHS, drive signals SEL, RST, FDG, TGL, TGS, FCG, and power supply voltage FCVDD.
  • the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t2
  • the state set to the voltage FCH is maintained, and at the time t8, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL.
  • FIG. 14 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, TGS, FCG, and the power supply voltage FCVDD.
  • the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t22, the state set to the voltage FCH is maintained, and at the time t38, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL.
  • the power supply voltage FCVDD is set to the voltage FCH only at the start of exposure and at the time of reading, and the period in which charges are accumulated in the charge accumulating unit 104 from the start of exposure to the start of reading.
  • the power supply voltage FCVDD is set to the voltage FCL.
  • FIG. 15 is a circuit diagram illustrating a configuration example of the unit pixel 100D arranged in the pixel array unit 11 of FIGS. 1 to 3.
  • portions corresponding to those in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • the unit pixel 100D is different from the unit pixel 100C in FIG. 12 in that the fourth transfer gate portion 102d is deleted. That is, the second photoelectric conversion unit 101b is directly connected to the charge storage unit 104 without passing through the fourth transfer gate unit 102d. Further, the unit pixel 100D is different from the unit pixel 100B in FIG. 9 in that the counter electrode of the charge storage unit 104 is connected to the variable voltage power supply FCVDD.
  • FIG. 16 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, FCG, and the power supply voltage FCVDD.
  • the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t2
  • the state set to the voltage FCH is maintained, and at the time t7, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL.
  • FIG. 17 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, FCG, and the power supply voltage FCVDD.
  • the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t22, the state set to the voltage FCH is maintained, and at the time t37, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL.
  • the power supply voltage FCVDD is set to the voltage FCL during the period in which charges are accumulated in the charge accumulation unit 104 from the start of exposure to the start of reading.
  • DDS processing that does not remove reset noise but removes fixed pattern noise peculiar to the pixel such as threshold variation of amplification transistors in the pixel.
  • CDS processing is performed to remove pixel-specific fixed pattern noise such as reset noise and threshold variation of amplification transistors in the pixel.
  • the processing example 1 is an arithmetic processing that does not require the use of a frame memory, there are advantages that the circuit configuration can be simplified and the cost can be reduced.
  • a storage means for example, a frame memory is required. Accordingly, the arithmetic processing of the processing example 2 is performed, for example, by using the data storage unit 19 as a storage unit in the signal processing unit 18 or using a frame memory in an external DSP circuit.
  • the CDS process for removing the fixed pattern noise unique to the pixel such as the reset noise and the threshold variation of the amplification transistor in the pixel is performed for the low-sensitivity signals SL and NL.
  • the signal processing unit 18 sets the ratio of the high sensitivity difference signal SNH2 to the high sensitivity difference signal SNH1 for each pixel, for each pixel, for each color, A gain table is generated by calculating as a gain for every specific pixel in the unit or for all pixels uniformly. Then, the signal processing unit 18 calculates the product of the high sensitivity difference signal SNH2 and the gain table as a correction value for the high sensitivity difference signal SNH2.
  • the gain is G1 and the correction value of the high sensitivity difference signal SNH2 (hereinafter referred to as a correction high sensitivity difference signal) is SNH2 ′
  • the gain G and the correction high sensitivity difference signal SNH2 ′ are expressed by the following equation (1): It can be determined based on (2).
  • Cfd1 is a capacitance value of the first FD unit 105a
  • Cfd2 is a capacitance value of the second FD unit 105b. Therefore, the gain G1 is equivalent to the capacitance ratio of charge-voltage conversion when the high sensitivity data signal SH2 and the high sensitivity reset signal NH2 are read and when the high sensitivity data signal SH1 and the high sensitivity reset signal NH1 are read.
  • the signal processing unit 18 shares the ratio of the low sensitivity difference signal SNL and the high sensitivity difference signal SNH1 for each pixel, for each pixel, for each color.
  • a gain table is generated by calculating as a gain for each specific pixel in a pixel unit or for all pixels uniformly. Then, the signal processing unit 18 calculates the product of the low sensitivity difference signal SNL and the gain table as a correction value for the low sensitivity difference signal SNL.
  • the gain G and the corrected low sensitivity difference signal SNL ′ are expressed by the following equation (3): It can be determined based on (4).
  • Cfc is a capacitance value of the charge storage unit 104. Therefore, the gain G2 is equivalent to the capacitance ratio of charge-voltage conversion when the low sensitivity data signal SL and the low sensitivity reset signal NL are read and when the high sensitivity data signal SH1 and the high sensitivity reset signal NH1 are read.
  • the signal processing unit 18 uses predetermined threshold values Vt1 and Vt2 set in advance.
  • the threshold value Vt1 is set in advance in a region where the high sensitivity difference signal SNH1 is saturated and the optical response characteristic is linear in the optical response characteristic.
  • the threshold value Vt2 is set in advance in a region where the high sensitivity difference signal SNH2 is saturated and the light response characteristic is linear in the light response characteristic.
  • FIG. 18 is a graph showing how the pixel signal SN is switched when the high-sensitivity differential signal SNH2 is not used and when it is used.
  • 18A is a graph when the high-sensitivity difference signal SNH2 is not used
  • FIG. 18B is a graph when the high-sensitivity difference signal SNH2 is used.
  • the pixel signal SN is switched to the low sensitivity difference signal SNL (more precisely, the corrected low sensitivity difference signal SNL ′).
  • the S / N ratio is greatly reduced and the image quality is deteriorated.
  • the pixel signal SN is switched to the high sensitivity difference signal SNH2 (more precisely, the corrected high sensitivity difference signal SNH2 ′). It is done.
  • the value of the high-sensitivity difference signal SNH2 with respect to the light amount at the time of switching is larger than the value of the low-sensitivity difference signal SNL with respect to the same light amount, so that the decrease in the SN ratio is suppressed and the image quality is kept good.
  • the pixel signal SN is switched to the low sensitivity difference signal SNL (more precisely, the corrected low sensitivity difference signal SNL ').
  • the value of the low sensitivity difference signal SNL with respect to the light amount at the time of switching is larger than the value of the low sensitivity difference signal SNL with respect to the light amount at the time of switching when the high sensitivity difference signal SNH2 is not used, and the decrease in the SN ratio is suppressed. The image quality is kept good.
  • the signal processing unit 18 combines the corrected high-sensitivity difference signal SNH2 ′ and the high-sensitivity difference signal SNH1 at a preset ratio within a predetermined range, and the pixel signal Output as SN. Further, the signal processing unit 18 synthesizes the corrected low-sensitivity difference signal SNL ′ and the corrected high-sensitivity difference signal SNH2 ′ at a preset ratio so that the pixel signal SN Output as.
  • the signal processing unit 18 performs the correction high-sensitivity difference step by step as in the following formulas (5) to (11) within the range before and after the high-sensitivity difference signal SNH1 with the threshold value Vt1 as a reference.
  • the synthesis ratio of the signal SNH2 ′ and the high sensitivity difference signal SNH1 is changed.
  • the signal processing unit 18 uses the threshold value Vt2 as a reference, and the corrected low-sensitivity difference step by step as in the following formulas (11) to (17) within the range before and after the high-sensitivity difference signal SNH2
  • the synthesis ratio of the signal SNL ′ and the corrected high sensitivity difference signal SNH2 ′ is changed.
  • the level at which the low-sensitivity data signal SL is saturated can be raised by providing the charge storage unit 104 for the low-sensitivity second photoelectric conversion unit 101b.
  • the maximum value of the dynamic range can be increased while the minimum value of the dynamic range is maintained, and the dynamic range can be expanded.
  • LED flicker in which a blinking subject such as an LED light source cannot be imaged at the blinking timing.
  • This LED flicker occurs, for example, because the dynamic range of a conventional image sensor is low and it is necessary to adjust the exposure time for each subject.
  • the exposure time is long for low-illuminance subjects and the exposure time is short for high-illuminance subjects. Thereby, it is possible to deal with subjects with various illuminances even in a low dynamic range.
  • the readout speed is constant regardless of the exposure time, when the exposure time is set in a unit shorter than the readout time, light incident on the photoelectric conversion unit other than the exposure time is photoelectrically converted into electric charges. , Discarded without being read.
  • the dynamic range can be expanded as described above, and the exposure time can be set long, so that the occurrence of LED flicker can be suppressed.
  • CMOS image sensors 10, 10A, and 10B as described above, it is possible to prevent the occurrence of artifacts and the reduction in resolution that occur when the number of divisions is increased by the time division method or the space division method.
  • the signal is read twice from the high-sensitivity first photoelectric conversion unit 101a by switching the charge-voltage conversion capacitor, and by using two types of high-sensitivity signals, the SN at the time of signal switching is changed. A decrease in the ratio can be suppressed.
  • the signal may be switched by comparing the low sensitivity difference signal SNL with a threshold value.
  • the charge storage unit may be provided in at least the photoelectric conversion unit having the lowest sensitivity without providing the charge storage unit in the photoelectric conversion unit having the highest sensitivity. Further, it is only necessary to read out a signal to at least the photoelectric conversion unit having the highest sensitivity by switching the charge-voltage conversion capacitor twice. Further, if this condition is satisfied, it is possible to provide two or more photoelectric conversion units having the same sensitivity.
  • the signal readout for the same photoelectric conversion unit may be performed by three or more different charge-voltage conversion capacitors.
  • the high-sensitivity reset signal NH2 the high-sensitivity reset signal NH1, the high-sensitivity data signal SH1, and the high-sensitivity data signal SH2 are read.
  • the reading order of the low sensitivity data signal SL and the low sensitivity reset signal NL can be reversed.
  • the present invention is applied to a CMOS image sensor in which unit pixels are arranged in a matrix.
  • the present technology is not limited to application to a CMOS image sensor. That is, the present technology can be applied to all XY address type solid-state imaging devices in which unit pixels are two-dimensionally arranged in a matrix.
  • the present technology is not limited to application to a solid-state imaging device that detects the distribution of the amount of incident light of visible light and captures it as an image, but a solid-state that captures the distribution of the incident amount of infrared rays, X-rays, or particles as an image. Applicable to all imaging devices.
  • the solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.
  • FIG. 19 is a diagram illustrating a usage example of the above-described solid-state imaging device.
  • the solid-state imaging device described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows.
  • Devices for taking images for viewing such as digital cameras and mobile devices with camera functions
  • Devices used for traffic such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc.
  • Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ⁇ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc.
  • Equipment used for medical and health care ⁇ Security equipment such as security surveillance cameras and personal authentication cameras ⁇ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports, such as action cameras and wearable cameras for sports applications, etc.
  • Equipment used for agriculture such as cameras for monitoring the condition of fields and crops
  • FIG. 20 is a block diagram illustrating a configuration example of an imaging apparatus (camera apparatus) 400 that is an example of an electronic apparatus to which the present technology is applied.
  • the imaging apparatus 400 includes an optical system including a lens group 401, an imaging element 402, a DSP circuit 403 that is a camera signal processing unit, a frame memory 404, a display device 405, a recording device 406, and an operation system 407. And a power supply system 408 and the like.
  • the DSP circuit 403, the frame memory 404, the display device 405, the recording device 406, the operation system 407, and the power supply system 408 are connected to each other via a bus line 409.
  • the lens group 401 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 402.
  • the imaging element 402 converts the amount of incident light imaged on the imaging surface by the lens group 401 into an electrical signal in units of pixels and outputs it as a pixel signal.
  • the display device 405 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image sensor 402.
  • the recording device 406 records the moving image or still image captured by the image sensor 402 on a recording medium such as a memory card, a video tape, or a DVD (Digital Versatile Disk).
  • the operation system 407 issues operation commands for various functions of the imaging apparatus 400 under the operation of the user.
  • the power supply system 408 appropriately supplies various power supplies serving as operation power supplies for the DSP circuit 403, the frame memory 404, the display device 405, the recording device 406, and the operation system 407 to these supply targets.
  • Such an imaging apparatus 400 is applied to a camera module for a mobile device such as a video camera, a digital still camera, and a smartphone or a mobile phone.
  • the solid-state imaging apparatus according to each of the above-described embodiments can be used as the imaging element 402. Thereby, the image quality of the imaging device 400 can be improved.
  • the technology according to the present disclosure is mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, and a robot. It may be realized as a device.
  • FIG. 21 is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 includes a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism that adjusts and a braking device that generates a braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a blinker, or a fog lamp.
  • the body control unit 12020 can be input with radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives input of these radio waves or signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle.
  • the vehicle outside information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted.
  • the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030.
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image.
  • the vehicle outside information detection unit 12030 may perform an object detection process or a distance detection process such as a person, a car, an obstacle, a sign, or a character on a road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light.
  • the imaging unit 12031 can output an electrical signal as an image, or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared rays.
  • the vehicle interior information detection unit 12040 detects vehicle interior information.
  • a driver state detection unit 12041 that detects a driver's state is connected to the in-vehicle information detection unit 12040.
  • the driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver is asleep.
  • the microcomputer 12051 calculates a control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside / outside the vehicle acquired by the vehicle outside information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit A control command can be output to 12010.
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, following traveling based on inter-vehicle distance, vehicle speed maintenance traveling, vehicle collision warning, or vehicle lane departure warning. It is possible to perform cooperative control for the purpose.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of automatic driving that autonomously travels without depending on the operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle outside information detection unit 12030.
  • the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare, such as switching from a high beam to a low beam. It can be carried out.
  • the sound image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying information to a vehicle occupant or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 22 is a diagram illustrating an example of an installation position of the imaging unit 12031.
  • the vehicle 12100 includes imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper part of a windshield in the vehicle interior of the vehicle 12100.
  • the imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided in the side mirror mainly acquire an image of the side of the vehicle 12100.
  • the imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100.
  • the forward images acquired by the imaging units 12101 and 12105 are mainly used for detection of a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
  • FIG. 22 shows an example of the shooting range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of the imaging part 12104 provided in the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image when the vehicle 12100 is viewed from above is obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object in the imaging range 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100).
  • a predetermined speed for example, 0 km / h or more
  • the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like.
  • automatic brake control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • cooperative control for the purpose of autonomous driving or the like autonomously traveling without depending on the operation of the driver can be performed.
  • the microcomputer 12051 converts the three-dimensional object data related to the three-dimensional object to other three-dimensional objects such as a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and a utility pole based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles.
  • the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 is connected via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration or avoidance steering via the drive system control unit 12010, driving assistance for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is, for example, whether or not the user is a pedestrian by performing a pattern matching process on a sequence of feature points indicating the outline of an object and a procedure for extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras. It is carried out by the procedure for determining.
  • the audio image output unit 12052 When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 has a rectangular contour line for emphasizing the recognized pedestrian.
  • the display unit 12062 is controlled so as to be superimposed and displayed.
  • voice image output part 12052 may control the display part 12062 so that the icon etc. which show a pedestrian may be displayed on a desired position.
  • the technology according to the present disclosure may be applied to the imaging unit 12031, for example.
  • the CMOS image sensor 10 to the CMOS image sensor 10B in FIGS. 1 to 3 can be applied to the imaging unit 12031.
  • the dynamic range of the imaging unit 12031 can be expanded. As a result, for example, generation of LED flicker, generation of artifacts, reduction in resolution, and the like can be suppressed.
  • the present technology can take the following configurations.
  • the unit pixel is A first photoelectric conversion unit;
  • a second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
  • a third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter;
  • the driving unit includes a first data signal in a state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge voltage conversion unit, the first charge voltage conversion unit, and the first charge voltage conversion unit.
  • a second data signal in a state where the first charge is accumulated in a region where the potentials of the two charge-voltage conversion units are combined, and a third charge based on the second charge generated by the second photoelectric conversion unit.
  • a solid-state imaging device that controls to read data signals.
  • the drive unit includes a first reset signal in a state where the first charge voltage conversion unit is reset, and a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined.
  • the solid-state imaging device according to (1) wherein control is performed so as to read a second reset signal in a reset state.
  • the driving unit is configured to store the second charge in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined.
  • a data signal is read out, and a third reset signal in a state in which a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined is reset is read out.
  • the solid-state imaging device according to (2) A first difference signal that is a difference between the first data signal and the first reset signal; a second difference signal that is a difference between the second data signal and the second reset signal; and The solid-state imaging device according to (3), further including a signal processing unit that generates a third differential signal that is a difference between the third data signal and the third reset signal.
  • the signal processing unit uses the first difference signal as a pixel signal of the unit pixel when the value of the first difference signal is equal to or less than a predetermined first threshold, and the value of the first difference signal is When the first threshold value is exceeded and the value of the second difference signal is less than or equal to a predetermined second threshold value, the second difference signal is used as a pixel signal of the unit pixel, and the second difference signal.
  • the signal processing unit includes the first difference signal, the first difference signal at a combination ratio set based on at least one value of the first difference signal, the second difference signal, and the third difference signal,
  • the drive unit reads the second reset signal in a state where the region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined is reset, and then the third charge voltage conversion unit In a state where the transfer gate portion is in a non-conducting state, the first reset signal is read, then the first transfer gate portion is brought into a conducting state, and the first charge is converted into the first charge-voltage converting portion The first data signal is read in the state transferred to, and then the second data signal is read in the state where the third transfer gate portion is turned on.
  • the solid-state imaging device according to any one of (6).
  • the driving unit is configured to store the second charge in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined.
  • the unit pixel is A fourth transfer gate section for transferring charges from the second photoelectric conversion section to the charge storage section; An overflow path formed under the gate electrode of the fourth transfer gate portion and transferring the charge overflowing from the second photoelectric conversion portion to the charge storage portion;
  • the solid-state imaging device according to any one of the above.
  • the first data signal in the state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first charge-voltage conversion unit, and the second charge-voltage conversion A second data signal in a state where the first charge is accumulated in a region where the potentials of the first and second parts are combined, and a third data signal based on the second charge generated by the second photoelectric conversion unit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The present invention pertains to a solid state imaging apparatus that is capable of expanding the dynamic range of the solid state imaging apparatus while suppressing the deterioration of image quality, a method for driving the solid state imaging apparatus, and an electronic device. The solid state imaging apparatus executes control to read: a first data signal in a state in which a first charge generated by a first photoelectric conversion unit is stored in a first charge voltage conversion unit; a second data signal in a state in which the first charge is stored in a region in which the potentials of the first charge voltage conversion unit and a second charge voltage conversion unit are coupled; and a third data signal based on a second charge generated by a second photoelectric conversion unit. The present invention can be applied to, for example, a solid state imaging apparatus.

Description

固体撮像装置、固体撮像装置の駆動方法、及び、電子機器Solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus
 本技術は、固体撮像装置、固体撮像装置の駆動方法、及び、電子機器に関し、特に、ダイナミックレンジを拡大できるようにした固体撮像装置、固体撮像装置の駆動方法、及び、電子機器に関する。 The present technology relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device, and more particularly, to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device that can expand a dynamic range.
 従来、様々な方式の固体撮像装置のダイナミックレンジ拡大技術が存在する。 Conventionally, there are technologies for expanding the dynamic range of various types of solid-state imaging devices.
 例えば、異なる感度で時分割に撮影し、時分割に撮影した複数の画像を合成する時分割方式が知られている。 For example, a time division method is known in which images are taken in time division with different sensitivities and a plurality of images taken in time division are combined.
 また、例えば、感度が異なる受光素子を設け、感度が異なる受光素子でそれぞれ撮影した複数の画像を合成することによりダイナミックレンジを拡大する空間分割方式が知られている(例えば、特許文献1参照)。 In addition, for example, a space division method is known in which a light receiving element having different sensitivity is provided and a dynamic range is expanded by combining a plurality of images captured by light receiving elements having different sensitivities (see, for example, Patent Document 1). .
特開2006-253876号公報JP 2006-253876 A
 しかしながら、時分割方式や空間分割方式では、分割数を増やすことによりダイナミックレンジを拡大することができる一方、分割数が増えると、アーチファクトの発生や解像度の低下等による画質の劣化が発生する。 However, in the time division method and the space division method, the dynamic range can be expanded by increasing the number of divisions. On the other hand, when the number of divisions is increased, the image quality is deteriorated due to the occurrence of artifacts or a decrease in resolution.
 そこで、本技術は、画質の劣化を抑制しつつ、固体撮像装置のダイナミックレンジを拡大できるようにするものである。 Therefore, the present technology makes it possible to expand the dynamic range of the solid-state imaging device while suppressing deterioration in image quality.
 本技術の第1の側面の固体撮像装置は、複数の単位画素が配置されている画素アレイ部と、前記単位画素の動作を制御する駆動部とを備え、前記単位画素は、第1の光電変換部と、前記第1の光電変換部より感度が低い第2の光電変換部と、前記第2の光電変換部が生成した電荷を蓄積する電荷蓄積部と、第1の電荷電圧変換部と、第2の電荷電圧変換部と、前記第1の光電変換部から前記第1の電荷電圧変換部に電荷を転送する第1の転送ゲート部と、前記第2の電荷電圧変換部と前記電荷蓄積部のポテンシャルを結合する第2の転送ゲート部と、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合する第3の転送ゲート部とを備え、前記駆動部は、前記第1の光電変換部が生成した第1の電荷を前記第1の電荷電圧変換部に蓄積した状態における第1のデータ信号、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域に前記第1の電荷を蓄積した状態における第2のデータ信号、並びに、前記第2の光電変換部が生成した第2の電荷に基づく第3のデータ信号を読み出すように制御する。 The solid-state imaging device according to the first aspect of the present technology includes a pixel array unit in which a plurality of unit pixels are arranged, and a driving unit that controls the operation of the unit pixels. A conversion unit; a second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit; a charge storage unit that stores charges generated by the second photoelectric conversion unit; and a first charge-voltage conversion unit; , A second charge voltage conversion unit, a first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge A second transfer gate unit that couples the potential of the storage unit; and a third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter. The first electric charge generated by the first photoelectric conversion unit is converted into the first electric charge. A first data signal stored in the voltage converter, and a second data in the state where the first charge is stored in a region where the potentials of the first charge voltage converter and the second charge voltage converter are combined. And a third data signal based on the second charge generated by the second photoelectric conversion unit.
 前記駆動部には、前記第1の電荷電圧変換部をリセットした状態における第1のリセット信号、並びに、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域をリセットした状態における第2のリセット信号を読み出すように制御させることができる。 The drive unit includes a first reset signal in a state where the first charge voltage conversion unit is reset, and a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined. It is possible to control to read out the second reset signal in a state where is reset.
 前記駆動部には、前記第1の電荷電圧変換部、前記第2の電荷電圧変換部、及び、前記電荷蓄積部のポテンシャルを結合した領域に前記第2の電荷を蓄積した状態において前記第3のデータ信号を読み出すとともに、前記第1の電荷電圧変換部、前記第2の電荷電圧変換部、及び、前記電荷蓄積部のポテンシャルを結合した領域をリセットした状態における第3のリセット信号を読み出すように制御させることができる。 In the driving unit, the third charge is stored in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined. And a third reset signal in a state where the region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined is reset. Can be controlled.
 前記第1のデータ信号と前記第1のリセット信号との差分である第1の差分信号、前記第2のデータ信号と前記第2のリセット信号との差分である第2の差分信号、及び、前記第3のデータ信号と前記第3のリセット信号との差分である第3の差分信号を生成する信号処理部をさらに設けることができる。 A first difference signal that is a difference between the first data signal and the first reset signal; a second difference signal that is a difference between the second data signal and the second reset signal; and A signal processing unit that generates a third differential signal that is a difference between the third data signal and the third reset signal can be further provided.
 前記信号処理部には、前記第1の差分信号の値が所定の第1の閾値以下の場合、前記第1の差分信号を前記単位画素の画素信号に用い、前記第1の差分信号の値が前記第1の閾値を超え、前記第2の差分信号の値が所定の第2の閾値以下の場合、前記第2の差分信号を前記単位画素の画素信号に用い、前記第2の差分信号の値が前記第2の閾値を超える場合、前記第3の差分信号を前記単位画素の画素信号に用いらせることができる。 When the value of the first difference signal is equal to or less than a predetermined first threshold, the signal processing unit uses the first difference signal as a pixel signal of the unit pixel, and the value of the first difference signal Exceeds the first threshold and the value of the second difference signal is equal to or less than a predetermined second threshold, the second difference signal is used as a pixel signal of the unit pixel, and the second difference signal When the value of exceeds the second threshold, the third difference signal can be used as the pixel signal of the unit pixel.
 前記信号処理部には、前記第1の差分信号、前記第2の差分信号、及び、前記第3の差分信号のうち少なくとも1つの値に基づいて設定した合成比率で前記第1の差分信号、前記第2の差分信号、及び、前記第3の差分信号を合成することにより、前記単位画素の画素信号を生成させることができる。 The signal processing unit includes the first difference signal, the first difference signal at a combination ratio set based on at least one value of the first difference signal, the second difference signal, and the third difference signal. A pixel signal of the unit pixel can be generated by combining the second difference signal and the third difference signal.
 前記駆動部には、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域をリセットした状態において、前記第2のリセット信号を読み出し、次に、前記第3の転送ゲート部を非導通状態にした状態において、前記第1のリセット信号を読み出し、次に、前記第1の転送ゲート部を導通状態にし、前記第1の電荷を前記第1の電荷電圧変換部に転送した状態において、前記第1のデータ信号を読み出し、次に、前記第3の転送ゲート部を導通状態にした状態において、前記第2のデータ信号を読み出すように制御させることができる。 The drive unit reads the second reset signal in a state where the region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined is reset, and then the third charge The first reset signal is read out in a state in which the transfer gate portion is turned off, and then the first transfer gate portion is turned on to convert the first charge into the first charge-voltage conversion. The first data signal can be read out in a state where the data is transferred to a part, and then the second data signal can be read out in a state where the third transfer gate part is turned on.
 前記駆動部には、前記第1の電荷電圧変換部、前記第2の電荷電圧変換部、及び、前記電荷蓄積部のポテンシャルを結合した領域に前記第2の電荷を蓄積した状態において前記第3のデータ信号を読み出すように制御させることができる。 In the driving unit, the third charge is stored in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined. The data signal can be controlled to be read out.
 前記単位画素は、前記第2の光電変換部から前記電荷蓄積部に電荷を転送する第4の転送ゲート部と、前記第4の転送ゲート部のゲート電極の下部に形成され、前記第2の光電変換部から溢れた電荷を前記電荷蓄積部に転送するオーバーフローパスとをさらに設けることができる。 The unit pixel is formed under a fourth transfer gate unit that transfers charges from the second photoelectric conversion unit to the charge storage unit, and under a gate electrode of the fourth transfer gate unit, An overflow path for transferring charges overflowing from the photoelectric conversion unit to the charge storage unit may be further provided.
 前記第2の光電変換部と前記電荷蓄積部とを転送ゲート部を介さずに接続させることができる。 The second photoelectric conversion unit and the charge storage unit can be connected without a transfer gate unit.
 前記電荷蓄積部の対向電極を可変電圧電源に接続させ、前記駆動部には、前記電荷蓄積部に電荷を蓄積する期間において、前記電荷蓄積部に蓄積された電荷に基づく信号を読み出す期間より、前記電荷蓄積部の対向電極に印加される電圧を低くさせることができる。 The counter electrode of the charge storage unit is connected to a variable voltage power source, and the drive unit has a period of reading a signal based on the charge stored in the charge storage unit in a period of storing charge in the charge storage unit, The voltage applied to the counter electrode of the charge storage portion can be lowered.
 所定の電圧の電源と前記第2の電荷電圧変換部との間に接続されているリセットゲート部をさらに設けることができる。 It is possible to further provide a reset gate portion connected between a power supply of a predetermined voltage and the second charge voltage conversion portion.
 本技術の第2の側面の固体撮像装置の駆動方法は、複数の単位画素が配置されている画素アレイ部と、前記単位画素の動作を制御する駆動部とを備え、前記単位画素は、第1の光電変換部と、前記第1の光電変換部より感度が低い第2の光電変換部と、前記第2の光電変換部が生成した電荷を蓄積する電荷蓄積部と、第1の電荷電圧変換部と、第2の電荷電圧変換部と、前記第1の光電変換部から前記第1の電荷電圧変換部に電荷を転送する第1の転送ゲート部と、前記第2の電荷電圧変換部と前記電荷蓄積部のポテンシャルを結合する第2の転送ゲート部と、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合する第3の転送ゲート部とを備える固体撮像装置が、前記第1の光電変換部が生成した第1の電荷を前記第1の電荷電圧変換部に蓄積した状態における第1のデータ信号、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域に前記第1の電荷を蓄積した状態における第2のデータ信号、並びに、前記第2の光電変換部が生成した第2の電荷に基づく第3のデータ信号を読み出すように制御する。 The driving method of the solid-state imaging device according to the second aspect of the present technology includes a pixel array unit in which a plurality of unit pixels are arranged, and a driving unit that controls the operation of the unit pixels. 1 photoelectric conversion unit, a second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit, a charge storage unit for storing charges generated by the second photoelectric conversion unit, and a first charge voltage A conversion unit; a second charge voltage conversion unit; a first transfer gate unit configured to transfer charges from the first photoelectric conversion unit to the first charge voltage conversion unit; and the second charge voltage conversion unit. And a second transfer gate unit that couples the potential of the charge storage unit, and a third transfer gate unit that couples the potential of the first charge voltage conversion unit and the second charge voltage conversion unit. The imaging device uses the first charge generated by the first photoelectric conversion unit. The first charge is accumulated in a region where the first data signal accumulated in the first charge-voltage converter and the potentials of the first charge-voltage converter and the second charge-voltage converter are combined. Control is performed to read out the second data signal in the state and the third data signal based on the second charge generated by the second photoelectric conversion unit.
 本技術の第3の側面の電子機器は、複数の単位画素が配置されている画素アレイ部と、前記単位画素の動作を制御する駆動部とを備え、前記単位画素は、第1の光電変換部と、前記第1の光電変換部より感度が低い第2の光電変換部と、前記第2の光電変換部が生成した電荷を蓄積する電荷蓄積部と、第1の電荷電圧変換部と、第2の電荷電圧変換部と、前記第1の光電変換部から前記第1の電荷電圧変換部に電荷を転送する第1の転送ゲート部と、前記第2の電荷電圧変換部と前記電荷蓄積部のポテンシャルを結合する第2の転送ゲート部と、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合する第3の転送ゲート部とを備え、前記第1の光電変換部が生成した第1の電荷を前記第1の電荷電圧変換部に蓄積した状態における第1のデータ信号、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域に前記第1の電荷を蓄積した状態における第2のデータ信号、並びに、前記第2の光電変換部が生成した第2の電荷に基づく第3のデータ信号を読み出すように制御する固体撮像装置と、前記固体撮像装置からの信号を処理する信号処理装置とを備える。 An electronic apparatus according to a third aspect of the present technology includes a pixel array unit in which a plurality of unit pixels are arranged, and a drive unit that controls the operation of the unit pixel, and the unit pixel includes a first photoelectric conversion unit. A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit, a charge accumulation unit that accumulates charges generated by the second photoelectric conversion unit, a first charge voltage conversion unit, A second charge-voltage converter, a first transfer gate that transfers charges from the first photoelectric converter to the first charge-voltage converter, the second charge-voltage converter, and the charge storage A second transfer gate unit that couples the potentials of the first and second charge gates, and a third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter. The first charge generated by the photoelectric conversion unit is accumulated in the first charge voltage conversion unit. A first data signal in a stored state, a second data signal in a state in which the first charge is accumulated in a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined, and A solid-state imaging device that controls to read out a third data signal based on the second charge generated by the second photoelectric conversion unit, and a signal processing device that processes a signal from the solid-state imaging device.
 本技術の第1の側面乃至第3の側面においては、第1の光電変換部が生成した第1の電荷を前記第1の電荷電圧変換部に蓄積した状態における第1のデータ信号、前記第1の電荷電圧変換部と第2の電荷電圧変換部のポテンシャルを結合した領域に前記第1の電荷を蓄積した状態における第2のデータ信号、並びに、前記第2の光電変換部が生成した第2の電荷に基づく第3のデータ信号が読み出される。 In the first to third aspects of the present technology, the first data signal in a state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first data signal, A second data signal in a state where the first charge is accumulated in a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined, and a second data signal generated by the second photoelectric conversion unit. A third data signal based on the charge of 2 is read out.
 本技術の第1の側面乃至第3の側面によれば、画質の劣化を抑制しつつ、固体撮像装置のダイナミックレンジを拡大することができる。 According to the first to third aspects of the present technology, it is possible to expand the dynamic range of the solid-state imaging device while suppressing deterioration in image quality.
本技術が適用されるCMOSイメージセンサの構成の概略を示すシステム構成図である。1 is a system configuration diagram illustrating an outline of a configuration of a CMOS image sensor to which the present technology is applied. 本技術が適用されるCMOSイメージセンサの他のシステム構成を示すシステム構成図(その1)である。It is a system configuration | structure figure (the 1) which shows the other system configuration | structure of the CMOS image sensor to which this technique is applied. 本技術が適用されるCMOSイメージセンサの他のシステム構成を示すシステム構成図(その2)である。It is a system configuration figure (the 2) showing other system composition of a CMOS image sensor to which this art is applied. 本技術の第1の実施の形態における単位画素の構成例を示す回路図である。It is a circuit diagram showing an example of composition of a unit pixel in a 1st embodiment of this art. 図4の単位画素の露光開始時の第1の動作例を説明するためのタイミングチャートである。5 is a timing chart for explaining a first operation example at the start of exposure of the unit pixel of FIG. 4. 図4の単位画素の読み出し時の第1の動作例を説明するためのタイミングチャートである。FIG. 5 is a timing chart for explaining a first operation example during reading of the unit pixel of FIG. 4. FIG. 図4の単位画素の露光開始時の第2の動作例を説明するためのタイミングチャートである。6 is a timing chart for explaining a second operation example at the start of exposure of the unit pixel of FIG. 4. 図4の単位画素の読み出し時の第2の動作例を説明するためのタイミングチャートである。FIG. 5 is a timing chart for explaining a second operation example at the time of reading the unit pixel of FIG. 4. FIG. 本技術の第2の実施の形態における単位画素の構成例を示す回路図である。It is a circuit diagram showing an example of composition of a unit pixel in a 2nd embodiment of this art. 図9の単位画素の露光開始時の動作例を説明するためのタイミングチャートである。10 is a timing chart for explaining an operation example at the start of exposure of the unit pixel of FIG. 9. 図9の単位画素の読み出し時の動作例を説明するためのタイミングチャートである。10 is a timing chart for explaining an operation example at the time of reading the unit pixel of FIG. 9. 本技術の第3の実施の形態における単位画素の構成例を示す回路図である。It is a circuit diagram showing an example of composition of a unit pixel in a 3rd embodiment of this art. 図12の単位画素の露光開始時の動作例を説明するためのタイミングチャートである。13 is a timing chart for explaining an operation example at the start of exposure of the unit pixel in FIG. 12. 図12の単位画素の読み出し時の動作例を説明するためのタイミングチャートである。13 is a timing chart for explaining an operation example at the time of reading the unit pixel of FIG. 12. 本技術の第4の実施の形態における単位画素の構成例を示す回路図である。It is a circuit diagram showing an example of composition of a unit pixel in a 4th embodiment of this art. 図15の単位画素の露光開始時の動作例を説明するためのタイミングチャートである。16 is a timing chart for explaining an operation example at the start of exposure of the unit pixel in FIG. 15. 図15の単位画素の読み出し時の動作例を説明するためのタイミングチャートである。16 is a timing chart for explaining an operation example at the time of reading the unit pixel of FIG. 15. 信号処理の説明に供する入射光量-出力の特性図である。It is an incident light quantity-output characteristic diagram for explanation of signal processing. 固体撮像装置の使用例を示す図である。It is a figure which shows the usage example of a solid-state imaging device. 電子機器の構成例を示すブロック図である。It is a block diagram which shows the structural example of an electronic device. 車両制御システムの概略的な構成の一例を示すブロック図である。It is a block diagram which shows an example of a schematic structure of a vehicle control system. 車外情報検出部及び撮像部の設置位置の一例を示す説明図である。It is explanatory drawing which shows an example of the installation position of a vehicle exterior information detection part and an imaging part.
 以下、発明を実施するための形態(以下、「実施形態」と記述する)について図面を用いて詳細に説明する。なお、説明は以下の順序で行う。
 1.本技術が適用される固体撮像装置
 2.第1の実施の形態
 3.第2の実施の形態(第1の実施の形態から第4転送ゲート部を削除した例)
 4.第3の実施の形態(電荷蓄積部の対向電極に印加する電圧を可変にした例)
 5.第4の実施の形態(第3の実施の形態から第4転送ゲート部を削除した例)
 6.ノイズ除去処理及び演算処理に関する説明
 7.変形例
 8.固体撮像装置の使用例
Hereinafter, modes for carrying out the invention (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The description will be given in the following order.
1. 1. Solid-state imaging device to which the present technology is applied 1. First embodiment Second embodiment (example in which the fourth transfer gate unit is deleted from the first embodiment)
4). Third Embodiment (Example in which voltage applied to counter electrode of charge storage unit is variable)
5. Fourth embodiment (example in which the fourth transfer gate unit is deleted from the third embodiment)
6). 6. Explanation regarding noise removal processing and arithmetic processing Modification 8 Examples of using solid-state imaging devices
<1.本技術が適用される固体撮像装置>
{1-1.基本的なシステム構成}
 図1は、本技術が適用される固体撮像装置、例えばX-Yアドレス方式固体撮像装置の一種であるCMOSイメージセンサの構成の概略を示すシステム構成図である。ここで、CMOSイメージセンサとは、CMOSプロセスを応用して、又は、部分的に使用して作成されたイメージセンサである。
<1. Solid-state imaging device to which the present technology is applied>
{1-1. Basic system configuration}
FIG. 1 is a system configuration diagram showing an outline of the configuration of a solid-state imaging device to which the present technology is applied, for example, a CMOS image sensor which is a kind of XY address type solid-state imaging device. Here, the CMOS image sensor is an image sensor created by applying or partially using a CMOS process.
 本適用例に係るCMOSイメージセンサ10は、図示せぬ半導体基板(チップ)上に形成された画素アレイ部11と、当該画素アレイ部11と同じ半導体基板上に集積された周辺回路部とを有する構成となっている。周辺回路部は、例えば、垂直駆動部12、カラム処理部13、水平駆動部14及びシステム制御部15から構成されている。 A CMOS image sensor 10 according to this application example includes a pixel array unit 11 formed on a semiconductor substrate (chip) (not shown), and a peripheral circuit unit integrated on the same semiconductor substrate as the pixel array unit 11. It has a configuration. The peripheral circuit unit includes, for example, a vertical drive unit 12, a column processing unit 13, a horizontal drive unit 14, and a system control unit 15.
 CMOSイメージセンサ10は更に、信号処理部18及びデータ格納部19を備えている。信号処理部18及びデータ格納部19については、本CMOSイメージセンサ10と同じ基板上に搭載しても構わないし、本CMOSイメージセンサ10とは別の基板上に配置するようにしても構わない。また、信号処理部18及びデータ格納部19の各処理については、本CMOSイメージセンサ10とは別の基板に設けられる外部信号処理部、例えば、DSP(Digital Signal Processor)回路やソフトウェアによる処理でも構わない。 The CMOS image sensor 10 further includes a signal processing unit 18 and a data storage unit 19. The signal processing unit 18 and the data storage unit 19 may be mounted on the same substrate as the CMOS image sensor 10 or may be disposed on a different substrate from the CMOS image sensor 10. Each processing of the signal processing unit 18 and the data storage unit 19 may be processing by an external signal processing unit provided on a substrate different from the CMOS image sensor 10, for example, a DSP (Digital Signal Processor) circuit or software. Absent.
 画素アレイ部11は、受光した光量に応じた電荷を生成しかつ蓄積する光電変換部を有する単位画素(以下、単に「画素」と記述する場合もある)が行方向及び列方向に、すなわち、行列状に2次元配置された構成となっている。ここで、行方向とは画素行の画素の配列方向(すなわち、水平方向)を言い、列方向とは画素列の画素の配列方向(すなわち、垂直方向)を言う。単位画素の具体的な回路構成や画素構造の詳細については後述する。 The pixel array unit 11 includes unit pixels (hereinafter also simply referred to as “pixels”) having a photoelectric conversion unit that generates and accumulates charges according to the received light amount in the row direction and the column direction, that is, The configuration is two-dimensionally arranged in a matrix. Here, the row direction refers to the pixel arrangement direction (that is, the horizontal direction) of the pixel row, and the column direction refers to the pixel arrangement direction (that is, the vertical direction) of the pixel column. Details of the specific circuit configuration and pixel structure of the unit pixel will be described later.
 画素アレイ部11において、行列状の画素配列に対して、画素行ごとに画素駆動線16が行方向に沿って配線され、画素列ごとに垂直信号線17が列方向に沿って配線されている。画素駆動線16は、画素から信号を読み出す際の駆動を行うための駆動信号を伝送する。図1では、画素駆動線16について1本の配線として示しているが、1本に限られるものではない。画素駆動線16の一端は、垂直駆動部12の各行に対応した出力端に接続されている。 In the pixel array unit 11, the pixel drive lines 16 are wired along the row direction for each pixel row, and the vertical signal lines 17 are wired along the column direction for each pixel column in the matrix pixel array. . The pixel drive line 16 transmits a drive signal for driving when reading a signal from the pixel. In FIG. 1, the pixel drive line 16 is shown as one wiring, but is not limited to one. One end of the pixel drive line 16 is connected to an output end corresponding to each row of the vertical drive unit 12.
 垂直駆動部12は、シフトレジスタやアドレスデコーダなどによって構成され、画素アレイ部11の各画素を全画素同時あるいは行単位等で駆動する。すなわち、垂直駆動部12は、当該垂直駆動部12を制御するシステム制御部15と共に、画素アレイ部11の各画素の動作を制御する駆動部を構成している。この垂直駆動部12はその具体的な構成については図示を省略するが、一般的に、読出し走査系と掃出し走査系の2つの走査系を有する構成となっている。 The vertical drive unit 12 is configured by a shift register, an address decoder, and the like, and drives each pixel of the pixel array unit 11 at the same time or in units of rows. That is, the vertical drive unit 12 constitutes a drive unit that controls the operation of each pixel of the pixel array unit 11 together with the system control unit 15 that controls the vertical drive unit 12. The vertical drive unit 12 is not shown in the figure for its specific configuration, but generally has a configuration having two scanning systems, a reading scanning system and a sweeping scanning system.
 読出し走査系は、単位画素から信号を読み出すために、画素アレイ部11の単位画素を行単位で順に選択走査する。単位画素から読み出される信号はアナログ信号である。掃出し走査系は、読出し走査系によって読出し走査が行われる読出し行に対して、その読出し走査よりも露光時間分だけ先行して掃出し走査を行う。 The readout scanning system selectively scans the unit pixels of the pixel array unit 11 in units of rows in order to read out signals from the unit pixels. The signal read from the unit pixel is an analog signal. The sweep-out scanning system performs sweep-out scanning on the readout line on which readout scanning is performed by the readout scanning system prior to the readout scanning by the exposure time.
 この掃出し走査系による掃出し走査により、読出し行の単位画素の光電変換部から不要な電荷が掃き出されることによって当該光電変換部がリセットされる。そして、この掃出し走査系による不要電荷の掃き出す(リセットする)ことにより、所謂電子シャッタ動作が行われる。ここで、電子シャッタ動作とは、光電変換部の電荷を捨てて、新たに露光を開始する(電荷の蓄積を開始する)動作のことを言う。 By the sweep scanning by the sweep scanning system, unnecessary charges are swept out from the photoelectric conversion unit of the unit pixel in the readout row, thereby resetting the photoelectric conversion unit. A so-called electronic shutter operation is performed by sweeping (resetting) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the electric charge in the photoelectric conversion unit is discarded and exposure is newly started (charge accumulation is started).
 読出し走査系による読出し動作によって読み出される信号は、その直前の読出し動作又は電子シャッタ動作以降に受光した光量に対応するものである。そして、直前の読出し動作による読出しタイミング又は電子シャッタ動作による掃出しタイミングから、今回の読出し動作による読出しタイミングまでの期間が、単位画素における電荷の露光期間となる。 The signal read out by the readout operation by the readout scanning system corresponds to the amount of light received after the immediately preceding readout operation or electronic shutter operation. The period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the charge exposure period in the unit pixel.
 垂直駆動部12によって選択走査された画素行の各単位画素から出力される信号は、画素列ごとに垂直信号線17の各々を通してカラム処理部13に入力される。カラム処理部13は、画素アレイ部11の画素列ごとに、選択行の各画素から垂直信号線17を通して出力される信号に対して所定の信号処理を行うとともに、信号処理後の画素信号を一時的に保持する。 A signal output from each unit pixel of the pixel row selectively scanned by the vertical driving unit 12 is input to the column processing unit 13 through each of the vertical signal lines 17 for each pixel column. The column processing unit 13 performs predetermined signal processing on signals output from the pixels in the selected row through the vertical signal line 17 for each pixel column of the pixel array unit 11, and temporarily outputs the pixel signals after the signal processing. Hold on.
 具体的には、カラム処理部13は、信号処理として少なくとも、ノイズ除去処理、例えばCDS(Correlated Double Sampling;相関二重サンプリング)処理や、DDS(Double Data Sampling)処理を行う。例えば、CDS処理により、リセットノイズや画素内の増幅トランジスタの閾値ばらつき等の画素固有の固定パターンノイズが除去される。カラム処理部13にノイズ除去処理以外に、例えば、AD(アナログ-デジタル)変換機能を持たせ、アナログの画素信号をデジタル信号に変換して出力することも可能である。 Specifically, the column processing unit 13 performs at least noise removal processing, for example, CDS (Correlated Double Sampling) processing or DDS (Double Data Sampling) processing as signal processing. For example, the CDS process removes pixel-specific fixed pattern noise such as reset noise and threshold variation of amplification transistors in the pixel. In addition to noise removal processing, the column processing unit 13 may have, for example, an AD (analog-digital) conversion function to convert an analog pixel signal into a digital signal and output the digital signal.
 水平駆動部14は、シフトレジスタやアドレスデコーダなどによって構成され、カラム処理部13の画素列に対応する単位回路を順番に選択する。この水平駆動部14による選択走査により、カラム処理部13において単位回路ごとに信号処理された画素信号が順番に出力される。 The horizontal drive unit 14 includes a shift register, an address decoder, and the like, and sequentially selects unit circuits corresponding to the pixel columns of the column processing unit 13. By the selective scanning by the horizontal driving unit 14, pixel signals subjected to signal processing for each unit circuit in the column processing unit 13 are sequentially output.
 システム制御部15は、各種のタイミング信号を生成するタイミングジェネレータなどによって構成され、当該タイミングジェネレータで生成された各種のタイミングを基に、垂直駆動部12、カラム処理部13、及び、水平駆動部14などの駆動制御を行う。 The system control unit 15 includes a timing generator that generates various timing signals, and the vertical driving unit 12, the column processing unit 13, and the horizontal driving unit 14 based on various timings generated by the timing generator. Drive control is performed.
 信号処理部18は、少なくとも演算処理機能を有し、カラム処理部13から出力される画素信号に対して演算処理等の種々の信号処理を行う。データ格納部19は、信号処理部18での信号処理に当たって、その処理に必要なデータを一時的に格納する。 The signal processing unit 18 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing on the pixel signal output from the column processing unit 13. The data storage unit 19 temporarily stores data necessary for the signal processing in the signal processing unit 18.
{1-2.他のシステム構成}
 本技術が適用されるCMOSイメージセンサ10としては、上述したシステム構成のものに限られるものではない。他のシステム構成として、以下のようなシステム構成のものを挙げることができる。
{1-2. Other system configuration}
The CMOS image sensor 10 to which the present technology is applied is not limited to the system configuration described above. Examples of other system configurations include the following system configurations.
 例えば、図2に示すように、データ格納部19をカラム処理部13の後段に配置し、カラム処理部13から出力される画素信号を、データ格納部19を経由して信号処理部18に供給するシステム構成のCMOSイメージセンサ10Aを挙げることができる。 For example, as shown in FIG. 2, the data storage unit 19 is arranged at the subsequent stage of the column processing unit 13, and the pixel signal output from the column processing unit 13 is supplied to the signal processing unit 18 via the data storage unit 19. And a CMOS image sensor 10A having a system configuration.
 更には、図3に示すように、画素アレイ部11の列ごとあるいは複数の列ごとにAD変換するAD変換機能をカラム処理部13に持たせるとともに、当該カラム処理部13に対してデータ格納部19及び信号処理部18を並列的に設けるシステム構成のCMOSイメージセンサ10Bを挙げることができる。 Further, as shown in FIG. 3, the column processing unit 13 is provided with an AD conversion function for performing AD conversion for each column or a plurality of columns of the pixel array unit 11, and a data storage unit is provided for the column processing unit 13. 19 and a CMOS image sensor 10B having a system configuration in which the signal processing unit 18 is provided in parallel.
<2.第1の実施の形態>
 次に、図4乃至図7を参照して、本技術の第1の実施の形態について説明する。
<2. First Embodiment>
Next, a first embodiment of the present technology will be described with reference to FIGS. 4 to 7.
{単位画素100Aの回路構成}
 図4は、図1乃至図3の画素アレイ部11に配置される単位画素100Aの構成例を示す回路図である。
{Circuit configuration of unit pixel 100A}
FIG. 4 is a circuit diagram illustrating a configuration example of the unit pixel 100A arranged in the pixel array unit 11 of FIGS.
 単位画素100Aは、第1光電変換部101a、第2光電変換部101b、第1転送ゲート部102a乃至第4転送ゲート部102d、リセットゲート部103、電荷蓄積部104、第1FD(フローティングディフュージョン)部105a、第2FD(フローティングディフュージョン)部105b、増幅トランジスタ106、及び、選択トランジスタ107を含むように構成される。 The unit pixel 100A includes a first photoelectric conversion unit 101a, a second photoelectric conversion unit 101b, a first transfer gate unit 102a to a fourth transfer gate unit 102d, a reset gate unit 103, a charge storage unit 104, and a first FD (floating diffusion) unit. 105 a, a second FD (floating diffusion) portion 105 b, an amplification transistor 106, and a selection transistor 107.
 また、単位画素100Aに対して、図1乃至図3の画素駆動線16として、複数の駆動線が、例えば画素行毎に配線される。そして、図1乃至図3の垂直駆動部12から複数の駆動線を介して、各種の駆動信号TGL、FCG、FDG、TGS、RST、SELが供給される。これらの駆動信号は、単位画素100Aの各トランジスタがNMOSトランジスタなので、高レベル(例えば、電源電圧VDD)の状態がアクティブ状態となり、低レベルの状態(例えば、負電位)が非アクティブ状態となるパルス信号である。 In addition, a plurality of drive lines are wired for each pixel row as the pixel drive lines 16 in FIGS. 1 to 3 with respect to the unit pixel 100A, for example. Various drive signals TGL, FCG, FDG, TGS, RST, and SEL are supplied from the vertical drive unit 12 of FIGS. 1 to 3 through a plurality of drive lines. These drive signals are pulses in which each of the transistors of the unit pixel 100A is an NMOS transistor, so that a high level (for example, power supply voltage VDD) is an active state and a low level (for example, a negative potential) is inactive. Signal.
 第1光電変換部101aは、例えば、PN接合のフォトダイオードからなる。第1光電変換部101aは、受光した光量に応じた電荷を生成し、蓄積する。 The first photoelectric conversion unit 101a is composed of, for example, a PN junction photodiode. The 1st photoelectric conversion part 101a produces | generates and accumulate | stores the electric charge according to the received light quantity.
 第2光電変換部101bは、第1光電変換部101aと同様に、例えば、PN接合のフォトダイオードからなる。第2光電変換部101bは、受光した光量に応じた電荷を生成し、蓄積する。 The second photoelectric conversion unit 101b is formed of, for example, a PN junction photodiode, similarly to the first photoelectric conversion unit 101a. The second photoelectric conversion unit 101b generates and accumulates charges corresponding to the received light amount.
 第1光電変換部101aと第2光電変換部101bを比較すると、第1光電変換部101aの方が受光面の面積が広く、感度が高く、第2光電変換部101bの方が受光面の面積が狭く、感度が低い。 Comparing the first photoelectric conversion unit 101a and the second photoelectric conversion unit 101b, the first photoelectric conversion unit 101a has a larger light receiving surface area and higher sensitivity, and the second photoelectric conversion unit 101b has a light receiving surface area. Is narrow and has low sensitivity.
 第1転送ゲート部102aは、第1光電変換部101aと第1FD部105aとの間に接続されている。第1転送ゲート部102aのゲート電極には、駆動信号TGLが印加される。駆動信号TGLがアクティブ状態になると、第1転送ゲート部102aが導通状態になり、第1光電変換部101aに蓄積されている電荷が、第1転送ゲート部102aを介して第1FD部105aに転送される。 The first transfer gate unit 102a is connected between the first photoelectric conversion unit 101a and the first FD unit 105a. A drive signal TGL is applied to the gate electrode of the first transfer gate portion 102a. When the drive signal TGL becomes active, the first transfer gate unit 102a becomes conductive, and the charge accumulated in the first photoelectric conversion unit 101a is transferred to the first FD unit 105a via the first transfer gate unit 102a. Is done.
 第2転送ゲート部102bは、電荷蓄積部104と第2FD部105bとの間に接続されている。第2転送ゲート部102bのゲート電極には、駆動信号FCGが印加される。駆動信号FCGがアクティブ状態になると、第2転送ゲート部102bが導通状態になり、電荷蓄積部104と第2FD部105bのポテンシャルが結合する。 The second transfer gate portion 102b is connected between the charge storage portion 104 and the second FD portion 105b. A drive signal FCG is applied to the gate electrode of the second transfer gate portion 102b. When the drive signal FCG becomes active, the second transfer gate portion 102b becomes conductive, and the potentials of the charge storage portion 104 and the second FD portion 105b are coupled.
 第3転送ゲート部102cは、第1FD部105aと第2FD部105bとの間に接続されている。第3転送ゲート部102cのゲート電極には、駆動信号FDGが印加される。駆動信号FDGがアクティブ状態になると、第3転送ゲート部102cが導通状態になり、第1FD部105aと第2FD部105bとのポテンシャルが結合する。 The third transfer gate unit 102c is connected between the first FD unit 105a and the second FD unit 105b. A drive signal FDG is applied to the gate electrode of the third transfer gate portion 102c. When the drive signal FDG becomes active, the third transfer gate portion 102c becomes conductive, and the potentials of the first FD portion 105a and the second FD portion 105b are coupled.
 第4転送ゲート部102dは、第2光電変換部101bと電荷蓄積部104との間に接続されている。第4転送ゲート部102dのゲート電極には、駆動信号TGSが印加される。駆動信号TGSがアクティブ状態になると、第4転送ゲート部102dが導通状態になり、第2光電変換部101bに蓄積されている電荷が、第4転送ゲート部102dを介して、電荷蓄積部104に転送される。 The fourth transfer gate unit 102d is connected between the second photoelectric conversion unit 101b and the charge storage unit 104. A drive signal TGS is applied to the gate electrode of the fourth transfer gate portion 102d. When the drive signal TGS is in the active state, the fourth transfer gate unit 102d becomes conductive, and the charge accumulated in the second photoelectric conversion unit 101b is transferred to the charge accumulation unit 104 via the fourth transfer gate unit 102d. Transferred.
 また、第4転送ゲート部102dのゲート電極の下部は、ポテンシャルが若干深くなっており、第2光電変換部101bの飽和電荷量を超え、第2光電変換部101bから溢れた電荷を電荷蓄積部104に転送するオーバーフローパスが形成されている。なお、以下、第4転送ゲート部102dのゲート電極の下部に形成されているオーバーフローパスを、単に第4転送ゲート部102dのオーバーフローパスと称する。 In addition, the lower part of the gate electrode of the fourth transfer gate portion 102d has a slightly deep potential, and the charge that exceeds the saturation charge amount of the second photoelectric conversion portion 101b and overflows from the second photoelectric conversion portion 101b is stored in the charge storage portion. An overflow path to be transferred to 104 is formed. Hereinafter, the overflow path formed below the gate electrode of the fourth transfer gate portion 102d is simply referred to as the overflow path of the fourth transfer gate portion 102d.
 リセットゲート部103は、電源電圧VDDを供給する電源VDDと第2FD部105bとの間に接続されている。リセットゲート部103のゲート電極には、駆動信号RSTが印加される。駆動信号RSTがアクティブ状態になると、リセットゲート部103が導通状態になる。これにより、例えば、第1FD部105aと第2FD部105bのポテンシャルが結合した領域、又は、電荷蓄積部104、第1FD部105a、及び、第2FD部105bのポテンシャルが結合した領域の電位が、電源電圧VDDのレベルにリセットされる。 The reset gate unit 103 is connected between the power supply VDD that supplies the power supply voltage VDD and the second FD unit 105b. A drive signal RST is applied to the gate electrode of the reset gate portion 103. When the drive signal RST becomes active, the reset gate unit 103 becomes conductive. Thereby, for example, the potential of the region where the potentials of the first FD unit 105a and the second FD unit 105b are combined, or the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is Reset to the level of voltage VDD.
 電荷蓄積部104は、例えば、キャパシタからなり、電荷蓄積部104の対向電極は、電源VDDの間に接続されている。電荷蓄積部104は、第2光電変換部101bから転送される電荷を蓄積する。 The charge storage unit 104 is made of a capacitor, for example, and the counter electrode of the charge storage unit 104 is connected between the power supply VDD. The charge storage unit 104 stores the charge transferred from the second photoelectric conversion unit 101b.
 第1FD部105a及び第2FD部105bは、電荷を電圧信号に電荷電圧変換して出力する。 The first FD unit 105a and the second FD unit 105b convert the charge into a voltage signal and output it.
 増幅トランジスタ106は、ゲート電極が第1FD部105aに接続され、ドレイン電極が電源VDDに接続されており、第1FD部105aに保持されている電荷を読み出す読出し回路、所謂ソースフォロワ回路の入力部となる。すなわち、増幅トランジスタ106は、ソース電極が選択トランジスタ107を介して垂直信号線17に接続されることにより、当該垂直信号線17の一端に接続される定電流源108とソースフォロワ回路を構成する。 The amplification transistor 106 has a gate electrode connected to the first FD unit 105a, a drain electrode connected to the power supply VDD, and a readout circuit that reads out the charge held in the first FD unit 105a, a so-called source follower circuit input unit and Become. That is, the amplification transistor 106 forms a source follower circuit with the constant current source 108 connected to one end of the vertical signal line 17 by connecting the source electrode to the vertical signal line 17 via the selection transistor 107.
 選択トランジスタ107は、増幅トランジスタ106のソース電極と垂直信号線17との間に接続されている。選択トランジスタ107のゲート電極には、駆動信号SELが印加される。駆動信号SELがアクティブ状態になると、選択トランジスタ107が導通状態になり、単位画素100Aが選択状態となる。これにより、増幅トランジスタ106から出力される画素信号が、選択トランジスタ107を介して、垂直信号線17に出力される。 The selection transistor 107 is connected between the source electrode of the amplification transistor 106 and the vertical signal line 17. A drive signal SEL is applied to the gate electrode of the selection transistor 107. When the drive signal SEL becomes active, the selection transistor 107 becomes conductive and the unit pixel 100A becomes selected. As a result, the pixel signal output from the amplification transistor 106 is output to the vertical signal line 17 via the selection transistor 107.
 なお、以下、各駆動信号がアクティブ状態になることを、各駆動信号がオンするともいい、各駆動信号が非アクティブ状態になることを、各駆動信号がオフするともいう。また、以下、各ゲート部又は各トランジスタが導通状態になることを、各ゲート部又は各トランジスタがオンするともいい、各ゲート部又は各トランジスタが非導通状態になることを、各ゲート部又は各トランジスタがオフするともいう。 Note that, hereinafter, each drive signal is in an active state, each drive signal is turned on, and each drive signal is in an inactive state, each drive signal is also turned off. In addition, hereinafter, each gate portion or each transistor is turned on, each gate portion or each transistor may be turned on, and each gate portion or each transistor is turned off. It is also said that the transistor is turned off.
{単位画素100Aの動作}
 次に、図5乃至図8のタイミングチャートを参照して、単位画素100Aの動作について説明する。
{Operation of Unit Pixel 100A}
Next, the operation of the unit pixel 100A will be described with reference to the timing charts of FIGS.
(単位画素100Aの露光開始時の第1の動作例)
 まず、図5のタイミングチャートを参照して、単位画素100Aの露光開始時の第1の動作例について説明する。この処理は、例えば、画素アレイ部11の画素行毎、又は、複数の画素行毎に、所定の走査順で行われる。なお、図5には、水平同期信号XHS、駆動信号SEL、RST、FDG、TGL、TGS、FCGのタイミングチャートが示されている。
(First operation example at the start of exposure of the unit pixel 100A)
First, a first operation example at the start of exposure of the unit pixel 100A will be described with reference to the timing chart of FIG. This process is performed, for example, in a predetermined scanning order for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows. FIG. 5 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, TGS, and FCG.
 まず、時刻t1において、水平同期信号XHSが入力され、単位画素100Aの露光処理が開始する。 First, at time t1, the horizontal synchronization signal XHS is input, and the exposure processing of the unit pixel 100A starts.
 次に、時刻t2において、駆動信号RST、FDGがオンし、リセットゲート部103、第3転送ゲート部102cがオンする。これにより、第1FD部105aと第2FD部105bのポテンシャルが結合され、結合した領域の電位が、電源電圧VDDのレベルにリセットされる。 Next, at time t2, the drive signals RST and FDG are turned on, and the reset gate unit 103 and the third transfer gate unit 102c are turned on. As a result, the potentials of the first FD portion 105a and the second FD portion 105b are coupled, and the potential of the coupled region is reset to the level of the power supply voltage VDD.
 次に、時刻t3において、駆動信号TGLがオンし、第1転送ゲート部102aがオンする。これにより、第1光電変換部101aに蓄積されている電荷が、第1転送ゲート部102aを介して、第1FD部105aと第2FD部105bのポテンシャルが結合した領域に転送され、第1光電変換部101aがリセットされる。 Next, at time t3, the drive signal TGL is turned on, and the first transfer gate unit 102a is turned on. As a result, the electric charge accumulated in the first photoelectric conversion unit 101a is transferred to the region where the potentials of the first FD unit 105a and the second FD unit 105b are coupled via the first transfer gate unit 102a. The unit 101a is reset.
 次に、時刻t4において、駆動信号TGLがオフし、第1転送ゲート部102aがオフする。これにより、第1光電変換部101aへの電荷の蓄積が開始され、露光期間が開始する。 Next, at time t4, the drive signal TGL is turned off, and the first transfer gate unit 102a is turned off. Thereby, accumulation of electric charges in the first photoelectric conversion unit 101a is started, and an exposure period is started.
 次に、時刻t5において、駆動信号TGS、FCGがオンし、第4転送ゲート部102d、第2転送ゲート部102bがオンする。これにより、電荷蓄積部104、第1FD部105a、及び、第2FD部105bのポテンシャルが結合する。また、第2光電変換部101bに蓄積されている電荷が、第4転送ゲート部102dを介して結合した領域に転送され、第2光電変換部101b及び電荷蓄積部104がリセットされる。 Next, at time t5, the drive signals TGS and FCG are turned on, and the fourth transfer gate unit 102d and the second transfer gate unit 102b are turned on. As a result, the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are coupled. In addition, the charge accumulated in the second photoelectric conversion unit 101b is transferred to the coupled region via the fourth transfer gate unit 102d, and the second photoelectric conversion unit 101b and the charge accumulation unit 104 are reset.
 次に、時刻t6において、駆動信号TGSがオフし、第4転送ゲート部102dがオフする。これにより、第2光電変換部101bへの電荷の蓄積が開始される。 Next, at time t6, the drive signal TGS is turned off, and the fourth transfer gate unit 102d is turned off. Thereby, accumulation of electric charges in the second photoelectric conversion unit 101b is started.
 次に、時刻t7において、駆動信号FCGがオフし、第2転送ゲート部102bがオフする。これにより、電荷蓄積部104が、第2光電変換部101bから溢れ、第4転送ゲート部102dのオーバーフローパスを介して転送されてくる電荷の蓄積を開始する。 Next, at time t7, the drive signal FCG is turned off, and the second transfer gate unit 102b is turned off. As a result, the charge accumulation unit 104 starts accumulating charges that overflow from the second photoelectric conversion unit 101b and are transferred through the overflow path of the fourth transfer gate unit 102d.
 次に、時刻t8において、駆動信号RST、FDGがオフし、リセットゲート部103、第3転送ゲート部102cがオフする。 Next, at time t8, the drive signals RST and FDG are turned off, and the reset gate unit 103 and the third transfer gate unit 102c are turned off.
 そして、時刻t9において、水平同期信号XHSが入力される。 At time t9, the horizontal synchronization signal XHS is input.
(単位画素100Aの読み出し時の第1の動作例)
 次に、図6のタイミングチャートを参照して、単位画素100Aの画素信号の読み出し時の第1の動作例について説明する。この処理は、例えば、画素アレイ部11の画素行毎、又は、複数の画素行毎に、図5の処理が行われてから所定の時間後に所定の走査順で行われる。なお、図6には、水平同期信号XHS、駆動信号SEL、RST、FDG、TGL、TGS、FCGのタイミングチャートが示されている。
(First operation example when reading out the unit pixel 100A)
Next, a first operation example at the time of reading a pixel signal of the unit pixel 100A will be described with reference to a timing chart of FIG. This processing is performed in a predetermined scanning order after a predetermined time after the processing of FIG. 5 is performed for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows, for example. FIG. 6 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, TGS, and FCG.
 まず、時刻t21において、水平同期信号XHSが入力され、単位画素100Aの読み出し期間が開始する。 First, at time t21, the horizontal synchronization signal XHS is input, and the readout period of the unit pixel 100A starts.
 次に、時刻t22において、駆動信号SEL、RST、FDGがオンし、選択トランジスタ107、リセットゲート部103、第3転送ゲート部102cがオンする。これにより、単位画素100Aが選択状態になる。また、第1FD部105aと第2FD部105bのポテンシャルが結合され、結合した領域の電位が、電源電圧VDDのレベルにリセットされる。 Next, at time t22, the drive signals SEL, RST, and FDG are turned on, and the selection transistor 107, the reset gate unit 103, and the third transfer gate unit 102c are turned on. As a result, the unit pixel 100A is selected. Further, the potentials of the first FD portion 105a and the second FD portion 105b are combined, and the potential of the combined region is reset to the level of the power supply voltage VDD.
 次に、時刻t23において、駆動信号RSTがオフし、リセットゲート部103がオフする。 Next, at time t23, the drive signal RST is turned off, and the reset gate unit 103 is turned off.
 次に、時刻t23と時刻t24の間の時刻taにおいて、第1FD部105aと第2FD部105bのポテンシャルが結合した領域の電位に基づく信号NH2が、増幅トランジスタ106及び選択トランジスタ107を介して垂直信号線17に出力される。信号NH2は、第1FD部105aと第2FD部105bのポテンシャルを結合した領域のリセットした状態における電位に基づく信号となる。 Next, at time ta between time t23 and time t24, a signal NH2 based on the potential of the region where the potentials of the first FD portion 105a and the second FD portion 105b are combined is a vertical signal via the amplification transistor 106 and the selection transistor 107. Output on line 17. The signal NH2 is a signal based on a potential in a reset state of a region where the potentials of the first FD unit 105a and the second FD unit 105b are combined.
 なお、以下、信号NH2のことを、高感度リセット信号NH2とも称する。 Hereinafter, the signal NH2 is also referred to as a high-sensitivity reset signal NH2.
 次に、時刻t24において、駆動信号FDGがオフし、第3転送ゲート部102cがオフする。これにより、第1FD部105aと第2FD部105bのポテンシャルの結合が解消される。 Next, at time t24, the drive signal FDG is turned off and the third transfer gate unit 102c is turned off. Thereby, the potential coupling between the first FD part 105a and the second FD part 105b is canceled.
 次に、時刻t24と時刻t25の間の時刻tbにおいて、第1FD部105aの電位に基づく信号NH1が、増幅トランジスタ106及び選択トランジスタ107を介して垂直信号線17に出力される。信号NH1は、第1FD部105aのリセットした状態における電位に基づく信号となる。 Next, at time tb between time t24 and time t25, the signal NH1 based on the potential of the first FD unit 105a is output to the vertical signal line 17 via the amplification transistor 106 and the selection transistor 107. The signal NH1 is a signal based on the potential in the reset state of the first FD unit 105a.
 なお、以下、信号NH1のことを、高感度リセット信号NH1とも称する。 Hereinafter, the signal NH1 is also referred to as a high-sensitivity reset signal NH1.
 次に、時刻t25において、駆動信号TGLがオンし、第1転送ゲート部102aがオンする。これにより、露光期間中に第1光電変換部101aで生成され、蓄積された電荷が、第1転送ゲート部102aを介して第1FD部105aに転送される。 Next, at time t25, the drive signal TGL is turned on, and the first transfer gate unit 102a is turned on. Thereby, the charge generated and accumulated in the first photoelectric conversion unit 101a during the exposure period is transferred to the first FD unit 105a via the first transfer gate unit 102a.
 この時刻t25において、画素信号の読み出しが開始され、露光期間が終了する。 At this time t25, reading of the pixel signal is started, and the exposure period ends.
 次に、時刻t26において、駆動信号TGLがオフし、第1転送ゲート部102aがオフする。これにより、第1光電変換部101aから第1FD部105aへの電荷の転送が停止する。 Next, at time t26, the drive signal TGL is turned off, and the first transfer gate unit 102a is turned off. Thereby, the transfer of charge from the first photoelectric conversion unit 101a to the first FD unit 105a is stopped.
 次に、時刻t26と時刻t27の間の時刻tcにおいて、第1FD部105aの電位に基づく信号SH1が、増幅トランジスタ106及び選択トランジスタ107を介して垂直信号線17に出力される。信号SH1は、露光期間中に第1光電変換部101aで生成され、蓄積された電荷が第1FD部105aに蓄積された状態における第1FD部105aの電位に基づく信号となる。 Next, at time tc between time t26 and time t27, a signal SH1 based on the potential of the first FD unit 105a is output to the vertical signal line 17 via the amplification transistor 106 and the selection transistor 107. The signal SH1 is a signal based on the potential of the first FD unit 105a in a state where the electric charge generated and accumulated in the first photoelectric conversion unit 101a during the exposure period is accumulated in the first FD unit 105a.
 なお、以下、信号SH1のことを、高感度データ信号SH1とも称する。 Hereinafter, the signal SH1 is also referred to as a high sensitivity data signal SH1.
 次に、時刻t27において、駆動信号FDG、TGLがオンし、第3転送ゲート部102c、第1転送ゲート部102aがオンする。これにより、第1FD部105aと第2FD部105bのポテンシャルが結合し、時刻t25から時刻t26の間に転送しきれずに第1光電変換部101aに残っている電荷が、第1転送ゲート部102aを介して、結合した領域に転送される。なお、高感度データ信号SH1の読み出し時には、取り扱う電荷量に対して電荷電圧変換する容量が小さいため、第1光電変換部101aに電荷が残っていても問題にはならない。第1光電変換部101aに残った電荷は、高感度データ信号SH2の読み出し時に電荷転送できればよく、第1光電変換部101aに電荷を毀損することはない。 Next, at time t27, the drive signals FDG and TGL are turned on, and the third transfer gate unit 102c and the first transfer gate unit 102a are turned on. As a result, the potentials of the first FD unit 105a and the second FD unit 105b are combined, and the charge remaining in the first photoelectric conversion unit 101a without being transferred between the time t25 and the time t26 passes through the first transfer gate unit 102a. To the combined area. Note that when reading the high-sensitivity data signal SH1, since the capacity for charge-voltage conversion is small with respect to the amount of charge handled, there is no problem even if charges remain in the first photoelectric conversion unit 101a. The charge remaining in the first photoelectric conversion unit 101a only needs to be transferred when the high-sensitivity data signal SH2 is read, and the charge is not damaged in the first photoelectric conversion unit 101a.
 次に、時刻t28において、駆動信号TGLがオフし、第1転送ゲート部102aがオフする。これにより、第1光電変換部101aから第1FD部105aと第2FD部105bのポテンシャルが結合した領域への電荷の転送が停止する。 Next, at time t28, the drive signal TGL is turned off, and the first transfer gate unit 102a is turned off. As a result, transfer of charges from the first photoelectric conversion unit 101a to the region where the potentials of the first FD unit 105a and the second FD unit 105b are combined is stopped.
 次に、時刻t28と時刻t29の間の時刻tdにおいて、第1FD部105aと第2FD部105bのポテンシャルを結合した領域の電位に基づく信号SH2が、増幅トランジスタ106及び選択トランジスタ107を介して垂直信号線17に出力される。信号SH2は、露光期間中に第1光電変換部101aで生成され、蓄積された電荷が、第1FD部105aと第2FD部105bのポテンシャルを結合した領域に蓄積された状態における結合した領域の電位に基づく信号となる。従って、信号SH2の読み出し時に電荷電圧変換する容量は、第1FD部105aと第2FD部105bを合わせた容量となり、時刻tcにおける高感度データ信号SH1の読み出し時より大きくなる。 Next, at time td between time t28 and time t29, the signal SH2 based on the potential of the region where the potentials of the first FD portion 105a and the second FD portion 105b are combined is a vertical signal via the amplification transistor 106 and the selection transistor 107. Output on line 17. The signal SH2 is generated by the first photoelectric conversion unit 101a during the exposure period, and the accumulated electric charge is accumulated in the region where the potentials of the first FD unit 105a and the second FD unit 105b are combined. It becomes a signal based on. Accordingly, the capacity for charge-voltage conversion at the time of reading the signal SH2 is the capacity of the first FD portion 105a and the second FD portion 105b, and is larger than that at the time of reading the high sensitivity data signal SH1 at time tc.
 なお、以下、信号SH2のことを、高感度データ信号SH2とも称する。 Hereinafter, the signal SH2 is also referred to as a high-sensitivity data signal SH2.
 次に、時刻t29において、駆動信号RSTがオンし、リセットゲート部103がオンする。これにより、第1FD部105aと第2FD部105bのポテンシャルを結合した領域の電位が、電源電圧VDDのレベルにリセットされる。 Next, at time t29, the drive signal RST is turned on and the reset gate unit 103 is turned on. As a result, the potential of the region where the potentials of the first FD portion 105a and the second FD portion 105b are combined is reset to the level of the power supply voltage VDD.
 次に、時刻t30において、駆動信号SELがオフし、選択トランジスタ107がオフする。これにより、単位画素100Aが非選択状態になる。 Next, at time t30, the drive signal SEL is turned off and the selection transistor 107 is turned off. As a result, the unit pixel 100A enters a non-selected state.
 次に、時刻t31において、駆動信号RSTがオフし、リセットゲート部103がオフする。 Next, at time t31, the drive signal RST is turned off, and the reset gate unit 103 is turned off.
 次に、時刻t32において、駆動信号SEL、TGS、FCGがオンし、選択トランジスタ107、第4転送ゲート部102d、第2転送ゲート部102bがオンする。これにより、単位画素100Aが選択状態になる。また、電荷蓄積部104、第1FD部105a、及び、第2FD部105bのポテンシャルが結合するとともに、第2光電変換部101bに蓄積されている電荷が、結合した領域に転送される。これにより、露光期間中に第2光電変換部101b及び電荷蓄積部104に蓄積された電荷が、結合した領域に蓄積される。 Next, at time t32, the drive signals SEL, TGS, and FCG are turned on, and the selection transistor 107, the fourth transfer gate unit 102d, and the second transfer gate unit 102b are turned on. As a result, the unit pixel 100A is selected. Further, the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined, and the charges stored in the second photoelectric conversion unit 101b are transferred to the combined region. As a result, charges accumulated in the second photoelectric conversion unit 101b and the charge accumulation unit 104 during the exposure period are accumulated in the combined region.
 次に、時刻t33において、駆動信号TGSがオフし、第4転送ゲート部102dがオフする。これにより、第2光電変換部101bからの電荷の転送が停止する。 Next, at time t33, the drive signal TGS is turned off, and the fourth transfer gate unit 102d is turned off. Thereby, the transfer of charge from the second photoelectric conversion unit 101b is stopped.
 次に、時刻t33と時刻t34の間の時刻teにおいて、電荷蓄積部104、第1FD部105a、及び、第2FD部105bのポテンシャルが結合した領域の電位に基づく信号SLが、増幅トランジスタ106及び選択トランジスタ107を介して垂直信号線17に出力される。信号SLは、露光期間中に第2光電変換部101bで生成され、第2光電変換部101b及び電荷蓄積部104に蓄積された電荷が、電荷蓄積部104、第1FD部105a、及び、第2FD部105bのポテンシャルが結合した領域に蓄積された状態における結合した領域の電位に基づく信号となる。従って、信号SLの読み出し時に電荷電圧変換する容量は、電荷蓄積部104、第1FD部105a、及び、第2FD部105bを合わせた容量となる。この容量は、時刻tcにおける高感度データ信号SH1の読み出し時、及び、時刻tdにおける高感度データ信号SH2の読み出し時より大きくなる。 Next, at time te between time t33 and time t34, the signal SL based on the potential of the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is selected by the amplification transistor 106 and the selection transistor 106. The signal is output to the vertical signal line 17 through the transistor 107. The signal SL is generated by the second photoelectric conversion unit 101b during the exposure period, and the charges accumulated in the second photoelectric conversion unit 101b and the charge storage unit 104 are converted into the charge storage unit 104, the first FD unit 105a, and the second FD. The signal is based on the potential of the coupled region in the state where the potential of the portion 105b is accumulated in the coupled region. Therefore, the capacity for charge-voltage conversion at the time of reading the signal SL is a total capacity of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b. This capacity is larger than when reading the high sensitivity data signal SH1 at time tc and when reading the high sensitivity data signal SH2 at time td.
 なお、以下、信号SLのことを、低感度データ信号SLとも称する。 Hereinafter, the signal SL is also referred to as a low-sensitivity data signal SL.
 次に、時刻t34において、駆動信号RSTがオンし、リセットゲート部103がオンする。これにより、電荷蓄積部104、第1FD部105a、及び、第2FD部105bのポテンシャルが結合した領域がリセットされる。 Next, at time t34, the drive signal RST is turned on and the reset gate unit 103 is turned on. Thereby, the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is reset.
 次に、時刻t35において、駆動信号SEL、FCGがオフし、選択トランジスタ107、第2転送ゲート部102bがオフする。これにより、単位画素100Aが非選択状態になる。また、電荷蓄積部104のポテンシャルが、第1FD部105a及び第2FD部105bのポテンシャルから切り離される。 Next, at time t35, the drive signals SEL and FCG are turned off, and the selection transistor 107 and the second transfer gate unit 102b are turned off. As a result, the unit pixel 100A enters a non-selected state. In addition, the potential of the charge storage unit 104 is separated from the potentials of the first FD unit 105a and the second FD unit 105b.
 次に、時刻t36において、駆動信号RSTがオフし、リセットゲート部103がオフする。 Next, at time t36, the drive signal RST is turned off, and the reset gate unit 103 is turned off.
 次に、時刻t37において、駆動信号SEL、FCGがオンし、選択トランジスタ107、第2転送ゲート部102bがオンする。これにより、単位画素100Aが選択状態になる。また、電荷蓄積部104のポテンシャルが、第1FD部105a及び第2FD部105bのポテンシャルと結合する。 Next, at time t37, the drive signals SEL and FCG are turned on, and the selection transistor 107 and the second transfer gate unit 102b are turned on. As a result, the unit pixel 100A is selected. Further, the potential of the charge storage unit 104 is combined with the potentials of the first FD unit 105a and the second FD unit 105b.
 次に、時刻t37と時刻t38の間の時刻tfにおいて、電荷蓄積部104、第1FD部105a、及び、第2FD部105bのポテンシャルが結合した領域の電位に基づく信号NLが、増幅トランジスタ106及び選択トランジスタ107を介して垂直信号線17に出力される。この信号NLは、電荷蓄積部104、第1FD部105a、及び、第2FD部105bのポテンシャルが結合した領域のリセットされた状態における電位に基づく信号となる。 Next, at time tf between time t37 and time t38, the signal NL based on the potential of the region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined is selected from the amplification transistor 106 and the selection transistor 106. The signal is output to the vertical signal line 17 through the transistor 107. This signal NL is a signal based on a potential in a reset state of a region where the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined.
 なお、以下、信号NLのことを、低感度リセット信号NLとも称する。 Hereinafter, the signal NL is also referred to as a low-sensitivity reset signal NL.
 次に、時刻t38において、駆動信号SEL、FDG、FCGがオフし、選択トランジスタ107、第3転送ゲート部102c、第2転送ゲート部102bがオフする。これにより、単位画素100Aが非選択状態になる。また、電荷蓄積部104、第1FD部105a、及び、第2FD部105bのポテンシャルの結合が解消される。 Next, at time t38, the drive signals SEL, FDG, and FCG are turned off, and the selection transistor 107, the third transfer gate unit 102c, and the second transfer gate unit 102b are turned off. As a result, the unit pixel 100A enters a non-selected state. Further, the potential coupling of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b is eliminated.
 次に、時刻t39において、水平同期信号XHSが入力され、単位画素100Aの画素信号の読み出し期間が終了する。 Next, at time t39, the horizontal synchronization signal XHS is input, and the readout period of the pixel signal of the unit pixel 100A ends.
(単位画素100Aの露光開始時の第2の動作例)
 次に、図7のタイミングチャートを参照して、単位画素100Aの画素信号の露光開始時の第2の動作例について説明する。
(Second operation example at the start of exposure of the unit pixel 100A)
Next, a second operation example at the start of exposure of the pixel signal of the unit pixel 100A will be described with reference to the timing chart of FIG.
 図7のタイミングチャートを図5のタイミングチャートと比較すると、駆動信号RSTの動作タイミングのみが異なる。具体的には、図7のタイミングチャートでは、駆動信号RSTは、オフすることなく、オンした状態が維持される。 7 is compared with the timing chart of FIG. 5, only the operation timing of the drive signal RST is different. Specifically, in the timing chart of FIG. 7, the drive signal RST is kept on without being turned off.
(単位画素100Aの読み出し時の第2の動作例)
 次に、図8のタイミングチャートを参照して、単位画素100Aの画素信号の読み出し時の第2の動作例について説明する。この処理は、例えば、画素アレイ部11の画素行毎、又は、複数の画素行毎に、図7の処理が行われてから所定の時間後に所定の走査順で行われる。
(Second Example of Operation when Reading Unit Pixel 100A)
Next, a second operation example at the time of reading a pixel signal of the unit pixel 100A will be described with reference to a timing chart of FIG. This processing is performed in a predetermined scanning order after a predetermined time after the processing of FIG. 7 is performed for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows, for example.
 図8のタイミングチャートを図6のタイミングチャートと比較すると、駆動信号RSTの動作タイミングのみが異なる。具体的には、図7を参照して上述したように、駆動信号RSTは、露光開始時にオンした状態が維持されるため、図6の例のように、時刻t22においてオンする必要はない。また、駆動信号RSTは、時刻t34においてオンされた後、そのままオンした状態が維持される。 8 is compared with the timing chart of FIG. 6, only the operation timing of the drive signal RST is different. Specifically, as described above with reference to FIG. 7, the drive signal RST does not need to be turned on at time t22 as in the example of FIG. 6 because the drive signal RST is kept turned on at the start of exposure. Further, the drive signal RST is kept on after being turned on at time t34.
<3.第2の実施の形態>
 次に、図9乃至図11を参照して、本技術の第2の実施の形態について説明する。
<3. Second Embodiment>
Next, a second embodiment of the present technology will be described with reference to FIGS. 9 to 11.
{単位画素100Bの回路構成}
 図9は、図4の単位画素100Aの変形例である単位画素100Bの構成例を示す回路図である。なお、図中、図4と対応する部分には、同じ符号を付してあり、その説明は適宜省略する。
{Circuit configuration of unit pixel 100B}
FIG. 9 is a circuit diagram illustrating a configuration example of a unit pixel 100B that is a modification of the unit pixel 100A of FIG. In the figure, portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
 単位画素100Bを図4の単位画素100Aと比較すると、第4転送ゲート部102dが削除されている点が異なる。すなわち、第2光電変換部101bが、第4転送ゲート部102dを介さずに、電荷蓄積部104に直接接続されている。 4 is different from the unit pixel 100A of FIG. 4 in that the fourth transfer gate portion 102d is deleted. That is, the second photoelectric conversion unit 101b is directly connected to the charge storage unit 104 without passing through the fourth transfer gate unit 102d.
{単位画素100Bの動作}
 次に、図10及び図11のタイミングチャートを参照して、単位画素100Bの動作について説明する。
{Operation of Unit Pixel 100B}
Next, the operation of the unit pixel 100B will be described with reference to the timing charts of FIGS.
(単位画素100Bの露光開始時の動作例)
 まず、図10のタイミングチャートを参照して、単位画素100Bの露光開始時の動作例について説明する。この処理は、例えば、画素アレイ部11の画素行毎、又は、複数の画素行毎に、所定の走査順で行われる。なお、図10には、水平同期信号XHS、駆動信号SEL、RST、FDG、TGL、FCGのタイミングチャートが示されている。
(Operation example when starting exposure of unit pixel 100B)
First, an operation example at the start of exposure of the unit pixel 100B will be described with reference to the timing chart of FIG. This process is performed, for example, in a predetermined scanning order for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows. FIG. 10 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, and FCG.
 時刻t1乃至時刻t4において、図5の時刻t1乃至t4と同様の動作が行われる。 From time t1 to time t4, operations similar to those from time t1 to t4 in FIG. 5 are performed.
 次に、時刻t5において、駆動信号FCGがオンし、第2転送ゲート部102bがオンする。これにより、電荷蓄積部104、第1FD部105a、及び、第2FD部105bのポテンシャルが結合する。また、電荷蓄積部104に蓄積されている電荷が、第4転送ゲート部102dを介して結合した領域に転送され、第2光電変換部101b及び電荷蓄積部104がリセットされる。 Next, at time t5, the drive signal FCG is turned on, and the second transfer gate unit 102b is turned on. As a result, the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are coupled. In addition, the charge accumulated in the charge accumulation unit 104 is transferred to the coupled region via the fourth transfer gate unit 102d, and the second photoelectric conversion unit 101b and the charge accumulation unit 104 are reset.
 次に、時刻t6において、駆動信号FCGがオフし、第2転送ゲート部102bがオフする。これにより、電荷蓄積部104は、第2光電変換部101bから転送された電荷の蓄積を開始する。 Next, at time t6, the drive signal FCG is turned off, and the second transfer gate unit 102b is turned off. As a result, the charge accumulation unit 104 starts accumulating the charge transferred from the second photoelectric conversion unit 101b.
 その後、時刻t7及び時刻t8において、図5の時刻t8及び時刻t9と同様の動作が行われる。 Thereafter, at time t7 and time t8, operations similar to those at time t8 and time t9 in FIG. 5 are performed.
(単位画素100Bの読み出し時の動作例)
 次に、図11のタイミングチャートを参照して、単位画素100Bの画素信号の読み出し時の動作例について説明する。この処理は、例えば、画素アレイ部11の画素行毎、又は、複数の画素行毎に、図10の処理が行われてから所定の時間後に所定の走査順で行われる。なお、図11には、水平同期信号XHS、駆動信号SEL、RST、FDG、TGL、FCGのタイミングチャートが示されている。
(Operation example when reading out the unit pixel 100B)
Next, with reference to the timing chart of FIG. 11, an operation example at the time of reading the pixel signal of the unit pixel 100B will be described. This processing is performed in a predetermined scanning order after a predetermined time after the processing of FIG. 10 is performed, for example, for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows. FIG. 11 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, and FCG.
 時刻t21乃至時刻t31において、図6の時刻t21乃至時刻t31と同様の動作が行われる。 From time t21 to time t31, operations similar to those from time t21 to time t31 in FIG. 6 are performed.
 時刻t32において、駆動信号SEL、FCGがオンし、選択トランジスタ107、第2転送ゲート部102bがオンする。これにより、単位画素100Aが選択状態になる。また、電荷蓄積部104、第1FD部105a、及び、第2FD部105bのポテンシャルが結合するとともに、露光期間中に第2光電変換部101bで生成され、電荷蓄積部104に蓄積された電荷が、結合した領域に蓄積される。 At time t32, the drive signals SEL and FCG are turned on, and the selection transistor 107 and the second transfer gate unit 102b are turned on. As a result, the unit pixel 100A is selected. Further, the potentials of the charge storage unit 104, the first FD unit 105a, and the second FD unit 105b are combined, and the charges generated in the second photoelectric conversion unit 101b and accumulated in the charge storage unit 104 during the exposure period are Accumulated in the combined area.
 その後、時刻te乃至時刻t38において、図6の時刻te乃至時刻t39と同様の動作が行われた後、単位画素100Bの画素信号の読み出し期間が終了する。 After that, from time te to time t38, the same operation as that from time te to time t39 in FIG. 6 is performed, and then the pixel signal readout period of the unit pixel 100B ends.
 単位画素100Bでは、第4転送ゲート部102dが削除されるので、単位画素100Bを構成する各素子の配置の面積効率が向上する。例えば、第1光電変換部101aの受光面の面積を拡大し、第1光電変換部101aの感度を向上させることが可能である。 In the unit pixel 100B, since the fourth transfer gate portion 102d is deleted, the area efficiency of the arrangement of each element constituting the unit pixel 100B is improved. For example, it is possible to increase the area of the light receiving surface of the first photoelectric conversion unit 101a and improve the sensitivity of the first photoelectric conversion unit 101a.
 なお、図10及び図11のタイミングチャートにおいて、駆動信号RSTの動作タイミングを、上述した図7及び図8の例と同様にすることが可能である。 In the timing charts of FIGS. 10 and 11, the operation timing of the drive signal RST can be made the same as in the above-described examples of FIGS.
<4.第3の実施の形態>
 次に、図12乃至図14を参照して、本技術の第3の実施の形態について説明する。
<4. Third Embodiment>
Next, a third embodiment of the present technology will be described with reference to FIGS.
{単位画素100Cの回路構成}
 図12は、図1乃至図3の画素アレイ部11に配置される単位画素100Cの構成例を示す回路図である。なお、図中、図4と対応する部分には、同じ符号を付してあり、その説明は適宜省略する。
{Circuit configuration of unit pixel 100C}
FIG. 12 is a circuit diagram illustrating a configuration example of the unit pixel 100C arranged in the pixel array unit 11 of FIGS. In the figure, portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
 単位画素100Cを図4の単位画素100Aと比較すると、電荷蓄積部104の対向電極の接続位置が異なる。すなわち、単位画素100Cにおいて、電荷蓄積部104の対向電極が可変電圧電源FCVDDに接続されている点が異なる。可変電圧電源FCVDDの電源電圧FCVDDは、例えば、Highレベルの電圧FCH、又は、Lowレベルの電圧FCLに設定される。例えば、電圧FCHは、電源電圧VDDとほぼ同じレベルに設定され、電圧FCLは、所定の中間電位に設定される。 When the unit pixel 100C is compared with the unit pixel 100A of FIG. 4, the connection position of the counter electrode of the charge storage unit 104 is different. That is, the unit pixel 100C is different in that the counter electrode of the charge storage unit 104 is connected to the variable voltage power supply FCVDD. The power supply voltage FCVDD of the variable voltage power supply FCVDD is set to, for example, a high level voltage FCH or a low level voltage FCL. For example, the voltage FCH is set to substantially the same level as the power supply voltage VDD, and the voltage FCL is set to a predetermined intermediate potential.
{単位画素100Cの動作例}
 次に、図13及び図14のタイミングチャートを参照して、単位画素100Cの動作について説明する。
{Operation example of unit pixel 100C}
Next, the operation of the unit pixel 100C will be described with reference to the timing charts of FIGS.
(単位画素100Cの露光開始時の動作例)
 まず、図13のタイミングチャートを参照して、単位画素100Cの露光開始時の動作例について説明する。この処理は、例えば、画素アレイ部11の画素行毎、又は、複数の画素行毎に、所定の走査順で行われる。なお、図13には、水平同期信号XHS、駆動信号SEL、RST、FDG、TGL、TGS、FCG、電源電圧FCVDDのタイミングチャートが示されている。
(Operation example at the start of exposure of the unit pixel 100C)
First, an operation example at the start of exposure of the unit pixel 100C will be described with reference to the timing chart of FIG. This process is performed, for example, in a predetermined scanning order for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows. FIG. 13 shows a timing chart of the horizontal synchronization signal XHS, drive signals SEL, RST, FDG, TGL, TGS, FCG, and power supply voltage FCVDD.
 図13のタイミングチャートを、図5のタイミングチャートと比較すると、電源電圧FCVDDの動作タイミングのみが異なる。 13 is compared with the timing chart of FIG. 5, only the operation timing of the power supply voltage FCVDD is different.
 具体的には、時刻t2において、電源電圧FCVDDが、電圧FCLから電圧FCHに設定された後、電圧FCHに設定された状態が維持され、時刻t8において、電源電圧FCVDDが、電圧FCHから電圧FCLに設定される。 Specifically, after the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t2, the state set to the voltage FCH is maintained, and at the time t8, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL. Set to
(単位画素100Cの読み出し時の動作例)
 次に、図14のタイミングチャートを参照して、単位画素100Cの画素信号の読み出し時の動作例について説明する。この処理は、例えば、画素アレイ部11の画素行毎、又は、複数の画素行毎に、図13の処理が行われてから所定の時間後に所定の走査順で行われる。なお、図14には、水平同期信号XHS、駆動信号SEL、RST、FDG、TGL、TGS、FCG、電源電圧FCVDDのタイミングチャートが示されている。
(Operation example when reading out the unit pixel 100C)
Next, with reference to the timing chart of FIG. 14, an example of operation at the time of reading a pixel signal of the unit pixel 100C will be described. This processing is performed in a predetermined scanning order after a predetermined time after the processing of FIG. 13 is performed for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows, for example. FIG. 14 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, TGS, FCG, and the power supply voltage FCVDD.
 図14のタイミングチャートを、図6のタイミングチャートと比較すると、電源電圧FCVDDの動作タイミングのみが異なる。 14 is compared with the timing chart of FIG. 6, only the operation timing of the power supply voltage FCVDD is different.
 具体的には、時刻t22において、電源電圧FCVDDが、電圧FCLから電圧FCHに設定された後、電圧FCHに設定された状態が維持され、時刻t38において、電源電圧FCVDDが、電圧FCHから電圧FCLに設定される。 Specifically, after the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t22, the state set to the voltage FCH is maintained, and at the time t38, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL. Set to
 このように、単位画素100Cでは、露光開始時及び読み出し時にのみ電源電圧FCVDDが電圧FCHに設定され、露光が開始されてから読み出しが開始されるまでの電荷蓄積部104に電荷が蓄積される期間中には、電源電圧FCVDDは電圧FCLに設定される。これにより、電荷蓄積部104に電荷が蓄積される期間中に電荷蓄積部104に印加される電界が緩和され、電荷蓄積部104に発生する暗電流が抑制される。 Thus, in the unit pixel 100C, the power supply voltage FCVDD is set to the voltage FCH only at the start of exposure and at the time of reading, and the period in which charges are accumulated in the charge accumulating unit 104 from the start of exposure to the start of reading. Among them, the power supply voltage FCVDD is set to the voltage FCL. As a result, the electric field applied to the charge storage unit 104 during the period in which charges are stored in the charge storage unit 104 is relaxed, and dark current generated in the charge storage unit 104 is suppressed.
 なお、図13及び図14のタイミングチャートにおいて、駆動信号RSTの動作タイミングを、上述した図7及び図8の例と同様にすることが可能である。 In the timing charts of FIGS. 13 and 14, the operation timing of the drive signal RST can be made the same as in the above-described examples of FIGS.
<5.第4の実施の形態>
 次に、図15乃至図17を参照して、本技術の第4の実施の形態について説明する。
<5. Fourth Embodiment>
Next, a fourth embodiment of the present technology will be described with reference to FIGS. 15 to 17.
{単位画素100Dの回路構成}
 図15は、図1乃至図3の画素アレイ部11に配置される単位画素100Dの構成例を示す回路図である。なお、図中、図12と対応する部分には、同じ符号を付してあり、その説明は適宜省略する。
{Circuit configuration of unit pixel 100D}
FIG. 15 is a circuit diagram illustrating a configuration example of the unit pixel 100D arranged in the pixel array unit 11 of FIGS. 1 to 3. In the figure, portions corresponding to those in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
 単位画素100Dを図12の単位画素100Cと比較すると、第4転送ゲート部102dが削除されている点が異なる。すなわち、第2光電変換部101bが、第4転送ゲート部102dを介さずに、電荷蓄積部104に直接接続されている。また、単位画素100Dは、図9の単位画素100Bと比較して、電荷蓄積部104の対向電極が可変電圧電源FCVDDに接続されている点が異なる。 The unit pixel 100D is different from the unit pixel 100C in FIG. 12 in that the fourth transfer gate portion 102d is deleted. That is, the second photoelectric conversion unit 101b is directly connected to the charge storage unit 104 without passing through the fourth transfer gate unit 102d. Further, the unit pixel 100D is different from the unit pixel 100B in FIG. 9 in that the counter electrode of the charge storage unit 104 is connected to the variable voltage power supply FCVDD.
{単位画素100Dの動作例}
 次に、図16及び図17のタイミングチャートを参照して、単位画素100Dの動作について説明する。
{Operation example of unit pixel 100D}
Next, the operation of the unit pixel 100D will be described with reference to the timing charts of FIGS.
(単位画素100Dの露光開始時の動作例)
 まず、図16のタイミングチャートを参照して、単位画素100Dの露光開始時の動作例について説明する。この処理は、例えば、画素アレイ部11の画素行毎、又は、複数の画素行毎に、所定の走査順で行われる。なお、図16には、水平同期信号XHS、駆動信号SEL、RST、FDG、TGL、FCG、電源電圧FCVDDのタイミングチャートが示されている。
(Operation example at the start of exposure of the unit pixel 100D)
First, an operation example at the start of exposure of the unit pixel 100D will be described with reference to the timing chart of FIG. This process is performed, for example, in a predetermined scanning order for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows. FIG. 16 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, FCG, and the power supply voltage FCVDD.
 図16のタイミングチャートを、図10のタイミングチャートと比較すると、電源電圧FCVDDの動作タイミングのみが異なる。 16 is compared with the timing chart of FIG. 10, only the operation timing of the power supply voltage FCVDD is different.
 具体的には、時刻t2において、電源電圧FCVDDが、電圧FCLから電圧FCHに設定された後、電圧FCHに設定された状態が維持され、時刻t7において、電源電圧FCVDDが、電圧FCHから電圧FCLに設定される。 Specifically, after the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t2, the state set to the voltage FCH is maintained, and at the time t7, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL. Set to
(単位画素100Dの読み出し時の動作例)
 次に、図17のタイミングチャートを参照して、単位画素100Dの画素信号の読み出し時の動作例について説明する。この処理は、例えば、画素アレイ部11の画素行毎、又は、複数の画素行毎に、図16の処理が行われてから所定の時間後に所定の走査順で行われる。なお、図17には、水平同期信号XHS、駆動信号SEL、RST、FDG、TGL、FCG、電源電圧FCVDDのタイミングチャートが示されている。
(Operation example when reading out the unit pixel 100D)
Next, with reference to the timing chart of FIG. 17, an operation example at the time of reading the pixel signal of the unit pixel 100D will be described. This processing is performed in a predetermined scanning order after a predetermined time after the processing of FIG. 16 is performed, for example, for each pixel row of the pixel array unit 11 or for each of a plurality of pixel rows. FIG. 17 shows a timing chart of the horizontal synchronization signal XHS, the drive signals SEL, RST, FDG, TGL, FCG, and the power supply voltage FCVDD.
 図17のタイミングチャートを、図11のタイミングチャートと比較すると、電源電圧FCVDDの動作タイミングのみが異なる。 17 is compared with the timing chart of FIG. 11, only the operation timing of the power supply voltage FCVDD is different.
 具体的には、時刻t22において、電源電圧FCVDDが、電圧FCLから電圧FCHに設定された後、電圧FCHに設定された状態が維持され、時刻t37において、電源電圧FCVDDが、電圧FCHから電圧FCLに設定される。 Specifically, after the power supply voltage FCVDD is set from the voltage FCL to the voltage FCH at the time t22, the state set to the voltage FCH is maintained, and at the time t37, the power supply voltage FCVDD is changed from the voltage FCH to the voltage FCL. Set to
 このように、単位画素100Dにおいても、単位画素100Cと同様に、露光が開始されてから読み出しが開始されるまでの電荷蓄積部104に電荷が蓄積される期間中に、電源電圧FCVDDが電圧FCLに設定される。これにより、電荷蓄積部104に電荷が蓄積される期間中に電荷蓄積部104に印加される電界が緩和され、電荷蓄積部104に発生する暗電流が抑制される。 As described above, in the unit pixel 100D, similarly to the unit pixel 100C, the power supply voltage FCVDD is set to the voltage FCL during the period in which charges are accumulated in the charge accumulation unit 104 from the start of exposure to the start of reading. Set to As a result, the electric field applied to the charge storage unit 104 during the period in which charges are stored in the charge storage unit 104 is relaxed, and dark current generated in the charge storage unit 104 is suppressed.
 なお、図16及び図17のタイミングチャートにおいて、駆動信号RSTの動作タイミングを、上述した図7及び図8の例と同様にすることが可能である。 In the timing charts of FIGS. 16 and 17, the operation timing of the drive signal RST can be made the same as in the examples of FIGS. 7 and 8 described above.
<6.ノイズ除去処理及び演算処理に関する説明>
 上述した単位画素100A乃至100Dからは、高感度リセット信号NH2、高感度リセット信号NH1、高感度データ信号SH1、高感度データ信号SH2、低感度データ信号SL、低感度リセット信号NLの順に、垂直信号線17に対して信号が出力される。そして、後段の信号処理部、例えば、図1乃至図3に示すカラム処理部13や信号処理部18において、それらの信号に対して所定のノイズ除去処理及び信号処理が行われる。以下、後段のカラム処理部13におけるノイズ除去処理及び信号処理部18における演算処理の例について説明する。
<6. Explanation regarding noise removal processing and arithmetic processing>
From the above-described unit pixels 100A to 100D, a vertical signal in the order of a high sensitivity reset signal NH2, a high sensitivity reset signal NH1, a high sensitivity data signal SH1, a high sensitivity data signal SH2, a low sensitivity data signal SL, and a low sensitivity reset signal NL. A signal is output to line 17. Then, in a subsequent signal processing unit, for example, the column processing unit 13 or the signal processing unit 18 shown in FIGS. 1 to 3, predetermined noise removal processing and signal processing are performed on these signals. Hereinafter, an example of noise removal processing in the column processing unit 13 in the subsequent stage and calculation processing in the signal processing unit 18 will be described.
{ノイズ除去処理}
 最初に、カラム処理部13によるノイズ除去処理について説明する。
{Noise removal processing}
First, noise removal processing by the column processing unit 13 will be described.
(ノイズ除去処理の処理例1)
 まず、ノイズ除去処理の処理例1について説明する。
(Processing example 1 of noise removal processing)
First, processing example 1 of the noise removal processing will be described.
 例えば、カラム処理部13は、高感度データ信号SH1と高感度リセット信号NH1との差分をとることにより、高感度差分信号SNH1を生成する。従って、高感度差分信号SNH1=高感度データ信号SH1-高感度リセット信号NH1となる。 For example, the column processing unit 13 generates the high sensitivity difference signal SNH1 by taking the difference between the high sensitivity data signal SH1 and the high sensitivity reset signal NH1. Therefore, the high sensitivity difference signal SNH1 = the high sensitivity data signal SH1−the high sensitivity reset signal NH1.
 また、カラム処理部13は、高感度データ信号SH2と高感度リセット信号NH2との差分をとることにより、高感度差分信号SNH2を生成する。従って、高感度差分信号SNH2=高感度データ信号SH2-高感度リセット信号NH2となる。 Also, the column processing unit 13 generates the high sensitivity difference signal SNH2 by taking the difference between the high sensitivity data signal SH2 and the high sensitivity reset signal NH2. Therefore, the high sensitivity difference signal SNH2 = the high sensitivity data signal SH2-the high sensitivity reset signal NH2.
 さらに、カラム処理部13は、低感度データ信号SLと低感度リセット信号NLとの差分をとることにより、低感度差分信号SNLを生成する。従って、低感度差分信号SNL=低感度データ信号SL-低感度リセット信号NLとなる。 Further, the column processing unit 13 generates a low sensitivity difference signal SNL by taking the difference between the low sensitivity data signal SL and the low sensitivity reset signal NL. Therefore, the low sensitivity difference signal SNL = the low sensitivity data signal SL−the low sensitivity reset signal NL.
 このように、処理例1では、低感度の信号SL、NLに対しては、画素内の増幅トランジスタの閾値ばらつき等の画素固有の固定パターンノイズは除去されるもののリセットノイズは除去されないDDS処理が行われる。高感度の信号SH1、SH2、NH1、NH2については、リセットノイズや画素内の増幅トランジスタの閾値ばらつき等の画素固有の固定パターンノイズが除去されるCDS処理が行われる。 As described above, in the processing example 1, for low-sensitivity signals SL and NL, DDS processing that does not remove reset noise but removes fixed pattern noise peculiar to the pixel such as threshold variation of amplification transistors in the pixel. Done. For high-sensitivity signals SH1, SH2, NH1, and NH2, CDS processing is performed to remove pixel-specific fixed pattern noise such as reset noise and threshold variation of amplification transistors in the pixel.
 また、処理例1では、フレームメモリを用いる必要がない演算処理であることから、回路構成の簡略化、及び、低コスト化が図れる利点がある。 Further, since the processing example 1 is an arithmetic processing that does not require the use of a frame memory, there are advantages that the circuit configuration can be simplified and the cost can be reduced.
(ノイズ除去処理の処理例2)
 次に、ノイズ除去処理の処理例2について説明する。
(Noise removal processing example 2)
Next, processing example 2 of the noise removal process will be described.
 処理例2では、前のフレームの情報を用いるために、記憶手段、例えば、フレームメモリが必要になる。従って、処理例2の演算処理は、例えば、信号処理部18において、データ格納部19を記憶手段として用いたり、外部のDSP回路において、フレームメモリを用いたりして行うことになる。 In the processing example 2, in order to use the information of the previous frame, a storage means, for example, a frame memory is required. Accordingly, the arithmetic processing of the processing example 2 is performed, for example, by using the data storage unit 19 as a storage unit in the signal processing unit 18 or using a frame memory in an external DSP circuit.
 具体的には、まず、カラム処理部13は、低感度データ信号SLと、前フレームにおける低感度リセット信号NLAとの差分をとることにより、低感度差分信号SNLを生成する。従って、低感度差分信号SNL=低感度データ信号SL-低感度リセット信号NLAとなる。 Specifically, first, the column processing unit 13 generates the low sensitivity difference signal SNL by taking the difference between the low sensitivity data signal SL and the low sensitivity reset signal NLA in the previous frame. Therefore, the low sensitivity difference signal SNL = the low sensitivity data signal SL−the low sensitivity reset signal NLA.
 次に、カラム処理部13は、高感度データ信号SH1と高感度リセット信号NH1との差分をとることにより、高感度差分信号SNH1を生成する。従って、高感度差分信号SNH1=高感度データ信号SH1-高感度リセット信号NH1となる。 Next, the column processing unit 13 generates the high sensitivity difference signal SNH1 by taking the difference between the high sensitivity data signal SH1 and the high sensitivity reset signal NH1. Therefore, the high sensitivity difference signal SNH1 = the high sensitivity data signal SH1−the high sensitivity reset signal NH1.
 また、カラム処理部13は、高感度データ信号SH2と高感度リセット信号NH2との差分をとることにより、高感度差分信号SNH2を生成する。従って、高感度差分信号SNH2=高感度データ信号SH2-高感度リセット信号NH2となる。 Also, the column processing unit 13 generates the high sensitivity difference signal SNH2 by taking the difference between the high sensitivity data signal SH2 and the high sensitivity reset signal NH2. Therefore, the high sensitivity difference signal SNH2 = the high sensitivity data signal SH2-the high sensitivity reset signal NH2.
 このように、処理例2では、低感度の信号SL、NLについても、リセットノイズや画素内の増幅トランジスタの閾値ばらつき等の画素固有の固定パターンノイズが除去されるCDS処理が行われる。これにより、フレームメモリ等の記憶手段が必要になるものの、処理例1に比べてリセットノイズを大幅に抑制できる利点がある。 As described above, in the processing example 2, the CDS process for removing the fixed pattern noise unique to the pixel such as the reset noise and the threshold variation of the amplification transistor in the pixel is performed for the low-sensitivity signals SL and NL. Thereby, although a storage means such as a frame memory is required, there is an advantage that the reset noise can be significantly suppressed as compared with the processing example 1.
{画素信号の演算処理}
 次に、上述した第1乃至第3の実施の形態における信号処理部18の画素信号の演算処理について説明する。
{Calculation of pixel signal}
Next, pixel signal calculation processing of the signal processing unit 18 in the first to third embodiments described above will be described.
(画素信号の演算処理の処理例1)
 まず、画素信号の演算処理の処理例1について説明する。
(Processing Example 1 of Pixel Signal Calculation Processing)
First, processing example 1 of pixel signal calculation processing will be described.
 例えば、信号処理部18は、高感度差分信号SNH2が所定の範囲内となったときに、高感度差分信号SNH2と高感度差分信号SNH1の比を画素毎、複数画素毎、色毎、共有画素単位内の特定画素毎、もしくは全画素一律にゲインとして算出してゲインテーブルを生成する。そして、信号処理部18は、高感度差分信号SNH2と当該ゲインテーブルの積を高感度差分信号SNH2の補正値として算出する。 For example, when the high sensitivity difference signal SNH2 falls within a predetermined range, the signal processing unit 18 sets the ratio of the high sensitivity difference signal SNH2 to the high sensitivity difference signal SNH1 for each pixel, for each pixel, for each color, A gain table is generated by calculating as a gain for every specific pixel in the unit or for all pixels uniformly. Then, the signal processing unit 18 calculates the product of the high sensitivity difference signal SNH2 and the gain table as a correction value for the high sensitivity difference signal SNH2.
 ここで、ゲインをG1、高感度差分信号SNH2の補正値(以下、補正高感度差分信号と称する)をSNH2’とすると、ゲインG及び補正高感度差分信号SNH2’は、次式(1)、(2)に基づいて求めることができる。 Here, when the gain is G1 and the correction value of the high sensitivity difference signal SNH2 (hereinafter referred to as a correction high sensitivity difference signal) is SNH2 ′, the gain G and the correction high sensitivity difference signal SNH2 ′ are expressed by the following equation (1): It can be determined based on (2).
 G1=SNH1/SNH2=(Cfd1+Cfd2)/Cfd1 ・・・(1)
 SNH2’=G1×SNH2 ・・・(2)
G1 = SNH1 / SNH2 = (Cfd1 + Cfd2) / Cfd1 (1)
SNH2 ′ = G1 × SNH2 (2)
 ここで、Cfd1は第1FD部105aの容量値、Cfd2は第2FD部105bの容量値である。従って、ゲインG1は、高感度データ信号SH2及び高感度リセット信号NH2の読み出し時と、高感度データ信号SH1及び高感度リセット信号NH1の読み出し時における電荷電圧変換の容量比と等価である。 Here, Cfd1 is a capacitance value of the first FD unit 105a, and Cfd2 is a capacitance value of the second FD unit 105b. Therefore, the gain G1 is equivalent to the capacitance ratio of charge-voltage conversion when the high sensitivity data signal SH2 and the high sensitivity reset signal NH2 are read and when the high sensitivity data signal SH1 and the high sensitivity reset signal NH1 are read.
 次に、信号処理部18は、低感度差分信号SNLが所定の範囲内となったときに、低感度差分信号SNLと高感度差分信号SNH1の比を画素毎、複数画素毎、色毎、共有画素単位内の特定画素毎、もしくは全画素一律にゲインとして算出してゲインテーブルを生成する。そして、信号処理部18は、低感度差分信号SNLと当該ゲインテーブルの積を低感度差分信号SNLの補正値として算出する。 Next, when the low sensitivity difference signal SNL falls within a predetermined range, the signal processing unit 18 shares the ratio of the low sensitivity difference signal SNL and the high sensitivity difference signal SNH1 for each pixel, for each pixel, for each color. A gain table is generated by calculating as a gain for each specific pixel in a pixel unit or for all pixels uniformly. Then, the signal processing unit 18 calculates the product of the low sensitivity difference signal SNL and the gain table as a correction value for the low sensitivity difference signal SNL.
 ここで、ゲインをG2、低感度差分信号SNLの補正値(以下、補正低感度差分信号と称する)をSNL’とすると、ゲインG及び補正低感度差分信号SNL’は、次式(3)、(4)に基づいて求めることができる。 Here, when the gain is G2 and the correction value of the low sensitivity difference signal SNL (hereinafter referred to as a corrected low sensitivity difference signal) is SNL ′, the gain G and the corrected low sensitivity difference signal SNL ′ are expressed by the following equation (3): It can be determined based on (4).
 G2=SNH1/SNL=(Cfd1+Cfd2+Cfc)/Cfd1
                            ・・・(3)
 SNL’=G2×SNL ・・・(4)
G2 = SNH1 / SNL = (Cfd1 + Cfd2 + Cfc) / Cfd1
... (3)
SNL ′ = G2 × SNL (4)
 ここで、Cfcは電荷蓄積部104の容量値である。従って、ゲインG2は、低感度データ信号SL及び低感度リセット信号NLの読み出し時と、高感度データ信号SH1及び高感度リセット信号NH1の読み出し時における電荷電圧変換の容量比と等価である。 Here, Cfc is a capacitance value of the charge storage unit 104. Therefore, the gain G2 is equivalent to the capacitance ratio of charge-voltage conversion when the low sensitivity data signal SL and the low sensitivity reset signal NL are read and when the high sensitivity data signal SH1 and the high sensitivity reset signal NH1 are read.
 次に、信号処理部18は、予め設定された所定の閾値Vt1及びVt2を用いる。閾値Vt1は、光応答特性において、高感度差分信号SNH1が飽和前かつ光応答特性がリニアな領域において予め設定される。閾値Vt2は、光応答特性において、高感度差分信号SNH2が飽和前かつ光応答特性がリニアな領域において予め設定される。 Next, the signal processing unit 18 uses predetermined threshold values Vt1 and Vt2 set in advance. The threshold value Vt1 is set in advance in a region where the high sensitivity difference signal SNH1 is saturated and the optical response characteristic is linear in the optical response characteristic. The threshold value Vt2 is set in advance in a region where the high sensitivity difference signal SNH2 is saturated and the light response characteristic is linear in the light response characteristic.
 そして、信号処理部18は、高感度差分信号SNH1が所定の閾値Vt1を超えない場合、当該高感度差分信号SNH1を処理対象画素の画素信号SNとして出力する。すなわち、SNH1≦Vt1の場合、画素信号SN=高感度差分信号SNH1となる。 Then, when the high sensitivity difference signal SNH1 does not exceed the predetermined threshold value Vt1, the signal processing unit 18 outputs the high sensitivity difference signal SNH1 as the pixel signal SN of the processing target pixel. That is, when SNH1 ≦ Vt1, the pixel signal SN = high sensitivity difference signal SNH1.
 一方、信号処理部18は、高感度差分信号SNH1が所定の閾値Vt1を超え、高感度差分信号SNH2が所定の閾値Vt2を超えない場合、補正高感度差分信号SNH2’を処理対象画素の画素信号SNとして出力する。すなわち、Vt1<SNH1かつSNH2≦Vt2の場合、画素信号SN=補正高感度差分信号SNH2’となる。 On the other hand, when the high sensitivity difference signal SNH1 exceeds the predetermined threshold Vt1 and the high sensitivity difference signal SNH2 does not exceed the predetermined threshold Vt2, the signal processing unit 18 uses the corrected high sensitivity difference signal SNH2 ′ as the pixel signal of the processing target pixel. Output as SN. That is, when Vt1 <SNH1 and SNH2 ≦ Vt2, the pixel signal SN = the corrected high sensitivity difference signal SNH2 ′.
 また、信号処理部18は、高感度差分信号SNH2が所定の閾値Vt2を超える場合、補正低感度差分信号SNL’を処理対象画素の画素信号SNとして出力する。すなわち、Vt2<SNH2の場合、画素信号SN=補正低感度差分信号SNL’となる。 Further, when the high sensitivity difference signal SNH2 exceeds the predetermined threshold value Vt2, the signal processing unit 18 outputs the corrected low sensitivity difference signal SNL 'as the pixel signal SN of the processing target pixel. That is, when Vt2 <SNH2, the pixel signal SN = the corrected low sensitivity difference signal SNL ′.
 図18は、高感度差分信号SNH2を使用しない場合と使用した場合の画素信号SNの切り替えの様子を示すグラフである。図18のAは、高感度差分信号SNH2を使用しない場合のグラフであり、図18のBは、高感度差分信号SNH2を使用する場合のグラフである。 FIG. 18 is a graph showing how the pixel signal SN is switched when the high-sensitivity differential signal SNH2 is not used and when it is used. 18A is a graph when the high-sensitivity difference signal SNH2 is not used, and FIG. 18B is a graph when the high-sensitivity difference signal SNH2 is used.
 高感度差分信号SNH2を使用しない場合、高感度差分信号SNH1が閾値Vt1を超えたとき、画素信号SNが低感度差分信号SNL(より正確には、補正低感度差分信号SNL’)に切り替えられる。しかし、切り替え時の光量に対する低感度差分信号SNLの値が小さいため、SN比が大幅に低下し、画質が劣化する。 When the high sensitivity difference signal SNH2 is not used, when the high sensitivity difference signal SNH1 exceeds the threshold value Vt1, the pixel signal SN is switched to the low sensitivity difference signal SNL (more precisely, the corrected low sensitivity difference signal SNL ′). However, since the value of the low-sensitivity differential signal SNL with respect to the light amount at the time of switching is small, the S / N ratio is greatly reduced and the image quality is deteriorated.
 一方、高感度差分信号SNH2を使用する場合、高感度差分信号SNH1が閾値Vt1を超えたとき、画素信号SNが高感度差分信号SNH2(より正確には、補正高感度差分信号SNH2’)に切り替えられる。ここで、切り替え時の光量に対する高感度差分信号SNH2の値は、同じ光量に対する低感度差分信号SNLの値より大きく、SN比の低下が抑制され、画質が良好に保たれる。また、高感度差分信号SNH2が閾値Vt2を超えたとき、画素信号SNが低感度差分信号SNL(より正確には、補正低感度差分信号SNL’)に切り替えられる。ここで、切り替え時の光量に対する低感度差分信号SNLの値は、高感度差分信号SNH2を用いない場合の切り替え時の光量に対する低感度差分信号SNLの値より大きく、SN比の低下が抑制され、画質が良好に保たれる。 On the other hand, when the high sensitivity difference signal SNH2 is used, when the high sensitivity difference signal SNH1 exceeds the threshold value Vt1, the pixel signal SN is switched to the high sensitivity difference signal SNH2 (more precisely, the corrected high sensitivity difference signal SNH2 ′). It is done. Here, the value of the high-sensitivity difference signal SNH2 with respect to the light amount at the time of switching is larger than the value of the low-sensitivity difference signal SNL with respect to the same light amount, so that the decrease in the SN ratio is suppressed and the image quality is kept good. Further, when the high sensitivity difference signal SNH2 exceeds the threshold value Vt2, the pixel signal SN is switched to the low sensitivity difference signal SNL (more precisely, the corrected low sensitivity difference signal SNL '). Here, the value of the low sensitivity difference signal SNL with respect to the light amount at the time of switching is larger than the value of the low sensitivity difference signal SNL with respect to the light amount at the time of switching when the high sensitivity difference signal SNH2 is not used, and the decrease in the SN ratio is suppressed. The image quality is kept good.
(画素信号の演算処理の処理例2)
 次に、画素信号の演算処理の処理例2について説明する。
(Processing example 2 of pixel signal calculation processing)
Next, a processing example 2 of pixel signal calculation processing will be described.
 具体的には、信号処理部18は、高感度差分信号SNH1が所定の範囲内において、補正高感度差分信号SNH2’、及び、高感度差分信号SNH1を予め設定された比率において合成し、画素信号SNとして出力する。また、信号処理部18は、高感度差分信号SNH2が所定の範囲内において、補正低感度差分信号SNL’、及び、補正高感度差分信号SNH2’を予め設定された比率において合成し、画素信号SNとして出力する。 Specifically, the signal processing unit 18 combines the corrected high-sensitivity difference signal SNH2 ′ and the high-sensitivity difference signal SNH1 at a preset ratio within a predetermined range, and the pixel signal Output as SN. Further, the signal processing unit 18 synthesizes the corrected low-sensitivity difference signal SNL ′ and the corrected high-sensitivity difference signal SNH2 ′ at a preset ratio so that the pixel signal SN Output as.
 例えば、信号処理部18は、上述した閾値Vt1を基準として、高感度差分信号SNH1がその前後の範囲内において、次式(5)乃至(11)のように、段階的に、補正高感度差分信号SNH2’、及び、高感度差分信号SNH1の合成比率を変化させる。また、例えば、信号処理部18は、閾値Vt2を基準として、高感度差分信号SNH2がその前後の範囲内において、次式(11)乃至(17)のように、段階的に、補正低感度差分信号SNL’、及び、補正高感度差分信号SNH2’の合成比率を変化させる。 For example, the signal processing unit 18 performs the correction high-sensitivity difference step by step as in the following formulas (5) to (11) within the range before and after the high-sensitivity difference signal SNH1 with the threshold value Vt1 as a reference. The synthesis ratio of the signal SNH2 ′ and the high sensitivity difference signal SNH1 is changed. Further, for example, the signal processing unit 18 uses the threshold value Vt2 as a reference, and the corrected low-sensitivity difference step by step as in the following formulas (11) to (17) within the range before and after the high-sensitivity difference signal SNH2 The synthesis ratio of the signal SNL ′ and the corrected high sensitivity difference signal SNH2 ′ is changed.
 SNH1<Vt1×0.90の場合
    SN=SNH1 ・・・(5)
When SNH1 <Vt1 × 0.90 SN = SNH1 (5)
 Vt1×0.90≦SNH1<Vt1×0.94の場合
    SN=0.9×SNH1+0.1×SNH2’ ・・・(6)
When Vt1 × 0.90 ≦ SNH1 <Vt1 × 0.94 SN = 0.9 × SNH1 + 0.1 × SNH2 ′ (6)
 Vt1×0.94≦SNH1<Vt1×0.98の場合
    SN=0.7×SNH1+0.3×SNH2’ ・・・(7)
When Vt1 × 0.94 ≦ SNH1 <Vt1 × 0.98 SN = 0.7 × SNH1 + 0.3 × SNH2 ′ (7)
 Vt1×0.98≦SNH1<Vt1×1.02の場合
    SN=0.5×SNH1+0.5×SNH2’ ・・・(8)
When Vt1 × 0.98 ≦ SNH1 <Vt1 × 1.02 SN = 0.5 × SNH1 + 0.5 × SNH2 ′ (8)
 Vt1×1.02≦SNH1<Vt1×1.06の場合
    SN=0.3×SNH1+0.7×SNH2’ ・・・(9)
When Vt1 × 1.02 ≦ SNH1 <Vt1 × 1.06 SN = 0.3 × SNH1 + 0.7 × SNH2 ′ (9)
 Vt×1.06≦SNH1<Vt1×1.10の場合
    SN=0.1×SNH1+0.9×SNH2’ ・・・(10)
When Vt × 1.06 ≦ SNH1 <Vt1 × 1.10. SN = 0.1 × SNH1 + 0.9 × SNH2 ′ (10)
 Vt1×1.10≦SNH1かつSNH2<Vt2×0.90の場合
    SN=SNH2’ ・・・(11)
When Vt1 × 1.10 ≦ SNH1 and SNH2 <Vt2 × 0.90 SN = SNH2 ′ (11)
 Vt2×0.90≦SNH2<Vt2×0.94の場合
    SN=0.9×SNH2’+0.1×SNL’ ・・・(12)
When Vt2 × 0.90 ≦ SNH2 <Vt2 × 0.94 SN = 0.9 × SNH2 ′ + 0.1 × SNL ′ (12)
 Vt2×0.94≦SNH2<Vt2×0.98の場合
    SN=0.7×SNH2’+0.3×SNL’ ・・・(13)
When Vt2 × 0.94 ≦ SNH2 <Vt2 × 0.98 SN = 0.7 × SNH2 ′ + 0.3 × SNL ′ (13)
 Vt2×0.98≦SNH2<Vt2×1.02の場合
    SN=0.5×SNH2’+0.5×SNL’ ・・・(14)
When Vt2 × 0.98 ≦ SNH2 <Vt2 × 1.02 SN = 0.5 × SNH2 ′ + 0.5 × SNL ′ (14)
 Vt2×1.02≦SNH2<Vt2×1.06の場合
    SN=0.3×SNH2’+0.7×SNL’ ・・・(15)
When Vt2 × 1.02 ≦ SNH2 <Vt2 × 1.06 SN = 0.3 × SNH2 ′ + 0.7 × SNL ′ (15)
 Vt2×1.06≦SNH2<Vt2×1.10の場合
    SN=0.1×SNH2’+0.9×SNL’ ・・・(16)
When Vt2 × 1.06 ≦ SNH2 <Vt2 × 1.10. SN = 0.1 × SNH2 ′ + 0.9 × SNL ′ (16)
 Vt2×1.10≦SNH2の場合
    SN=SNL’ ・・・(17)
In the case of Vt2 × 1.10 ≦ SNH2, SN = SNL ′ (17)
 なお、式(11)乃至(17)において、高感度差分信号SNH1に対する重みが0に設定され、式(5)及び式(17)において、補正高感度差分信号SNH2’に対する重みが0に設定され、式(5)及び式(11)において、補正低感度差分信号SNL’に対する重みが0に設定されていると捉えると、各式において、高感度差分信号SNH1、補正高感度差分信号SNH2’、及び、補正低感度差分信号SNL’の3つの信号を設定された比率で合成し、画素信号SNとして出力していると捉えることができる。 In Expressions (11) to (17), the weight for the high sensitivity difference signal SNH1 is set to 0, and in Expressions (5) and (17), the weight for the corrected high sensitivity difference signal SNH2 ′ is set to 0. In Equations (5) and (11), assuming that the weight for the corrected low sensitivity difference signal SNL ′ is set to 0, in each equation, the high sensitivity difference signal SNH1, the corrected high sensitivity difference signal SNH2 ′, In addition, it can be understood that the three signals of the corrected low sensitivity difference signal SNL ′ are synthesized at a set ratio and output as the pixel signal SN.
 以上のような演算処理を行うことにより、低照度時の信号から中照度時の信号、及び、中照度時の信号から高照度時の信号へより滑らかに切り替えることが出来る。 By performing the above arithmetic processing, it is possible to smoothly switch from a signal at low illuminance to a signal at medium illuminance, and from a signal at medium illuminance to a signal at high illuminance.
 また、CMOSイメージセンサ10、10A及び10Bでは、低感度の第2光電変換部101bに対して電荷蓄積部104を設けることにより、低感度データ信号SLが飽和するレベルを引き上げることができる。これにより、ダイナミックレンジの最小値を保持したまま、ダイナミックレンジの最大値を大きくすることができ、ダイナミックレンジを拡大することができる。 In the CMOS image sensors 10, 10A, and 10B, the level at which the low-sensitivity data signal SL is saturated can be raised by providing the charge storage unit 104 for the low-sensitivity second photoelectric conversion unit 101b. As a result, the maximum value of the dynamic range can be increased while the minimum value of the dynamic range is maintained, and the dynamic range can be expanded.
 例えば、車載向けのイメージセンサにおいて、LED光源のように点滅する被写体を、点滅するタイミングによって撮像できないLEDフリッカという現象が発生する場合がある。このLEDフリッカは、例えば、従来のイメージセンサのダイナミックレンジが低く、被写体毎に露光時間を調整する必要があるために生じる。 For example, in an in-vehicle image sensor, there may occur a phenomenon called LED flicker in which a blinking subject such as an LED light source cannot be imaged at the blinking timing. This LED flicker occurs, for example, because the dynamic range of a conventional image sensor is low and it is necessary to adjust the exposure time for each subject.
 すなわち、従来のイメージセンサは、様々な照度の被写体に対応するため、低照度の被写体に対しては露光時間を長く、高照度の被写体に対しては露光時間を短くしている。これにより、低いダイナミックレンジでも様々な照度の被写体に対応することが可能になる。一方、露光時間に関わらず読み出し速度は一定であるため、読み出し時間よりも短い単位で露光時間を設定する場合、露光時間以外に光電変換部に入射した光は、光電変換されて電荷になるものの、読み出されることなく破棄される。 In other words, since the conventional image sensor supports subjects with various illuminances, the exposure time is long for low-illuminance subjects and the exposure time is short for high-illuminance subjects. Thereby, it is possible to deal with subjects with various illuminances even in a low dynamic range. On the other hand, since the readout speed is constant regardless of the exposure time, when the exposure time is set in a unit shorter than the readout time, light incident on the photoelectric conversion unit other than the exposure time is photoelectrically converted into electric charges. , Discarded without being read.
 一方、CMOSイメージセンサ10、10A及び10Bでは、上述したようにダイナミックレンジを拡大することができ、露光時間を長く設定することができるため、LEDフリッカの発生を抑制することができる。 On the other hand, in the CMOS image sensors 10, 10A and 10B, the dynamic range can be expanded as described above, and the exposure time can be set long, so that the occurrence of LED flicker can be suppressed.
 また、CMOSイメージセンサ10、10A及び10Bでは、上述したように時分割方式や空間分割方式で分割数を増やした場合に発生するアーチファクトの発生や解像度の低下を防止することができる。 Further, in the CMOS image sensors 10, 10A, and 10B, as described above, it is possible to prevent the occurrence of artifacts and the reduction in resolution that occur when the number of divisions is increased by the time division method or the space division method.
 さらに、上述したように、高感度の第1光電変換部101aに対する信号の読み出しを電荷電圧変換容量を切り替えて2度行い、2種類の高感度の信号を用いることにより、信号の切り替え時のSN比の低下を抑制することができる。 Further, as described above, the signal is read twice from the high-sensitivity first photoelectric conversion unit 101a by switching the charge-voltage conversion capacitor, and by using two types of high-sensitivity signals, the SN at the time of signal switching is changed. A decrease in the ratio can be suppressed.
 なお、以上の説明では、高感度差分信号SNH1及び高感度差分信号SNH2に対して異なる閾値を用いる例を示したが、同じ閾値を用いるようにしてもよい。また、例えば、低感度差分信号SNLを閾値と比較することにより、信号の切り替えを行うようにしてもよい。 In the above description, an example in which different threshold values are used for the high sensitivity difference signal SNH1 and the high sensitivity difference signal SNH2 is shown, but the same threshold value may be used. Further, for example, the signal may be switched by comparing the low sensitivity difference signal SNL with a threshold value.
<7.変形例>
 以上の説明では、1画素内に感度が異なる2つの光電変換部を設ける例を示したが、1画素内に3つ以上の光電変換部を設けることも可能である。この場合、感度が最も高い光電変換部に電荷蓄積部を設けずに、少なくとも感度が最も低い光電変換部に電荷蓄積部を設けるようにすればよい。また、少なくとも感度が最も高い光電変換部に対する信号の読み出しを、電荷電圧変換容量を切り替えて2度行うようにすればよい。さらに、この条件を満たしていれば、感度が同じ光電変換部を2つ以上設けることも可能である。
<7. Modification>
In the above description, an example in which two photoelectric conversion units having different sensitivities are provided in one pixel is shown, but it is also possible to provide three or more photoelectric conversion units in one pixel. In this case, the charge storage unit may be provided in at least the photoelectric conversion unit having the lowest sensitivity without providing the charge storage unit in the photoelectric conversion unit having the highest sensitivity. Further, it is only necessary to read out a signal to at least the photoelectric conversion unit having the highest sensitivity by switching the charge-voltage conversion capacitor twice. Further, if this condition is satisfied, it is possible to provide two or more photoelectric conversion units having the same sensitivity.
 また、例えば、同じ光電変換部に対する信号の読み出しを、3以上の異なる電荷電圧変換容量で行うようにしてもよい。 Further, for example, the signal readout for the same photoelectric conversion unit may be performed by three or more different charge-voltage conversion capacitors.
 さらに、図6、図8、図11、図14、及び、図17のタイミングチャートにおいて、高感度リセット信号NH2、高感度リセット信号NH1、高感度データ信号SH1、及び、高感度データ信号SH2の読み出しと、低感度データ信号SL及び低感度リセット信号NLの読み出しの順序を逆にすることも可能である。 Further, in the timing charts of FIGS. 6, 8, 11, 14, and 17, the high-sensitivity reset signal NH2, the high-sensitivity reset signal NH1, the high-sensitivity data signal SH1, and the high-sensitivity data signal SH2 are read. The reading order of the low sensitivity data signal SL and the low sensitivity reset signal NL can be reversed.
 また、上記実施形態では、単位画素が行列状に配置されてなるCMOSイメージセンサに適用した場合を例に挙げて説明したが、本技術はCMOSイメージセンサへの適用に限られるものではない。すなわち、本技術は、単位画素が行列状に2次元配置されてなるX-Yアドレス方式の固体撮像装置全般に対して適用可能である。 In the above embodiment, the case where the present invention is applied to a CMOS image sensor in which unit pixels are arranged in a matrix is described as an example. However, the present technology is not limited to application to a CMOS image sensor. That is, the present technology can be applied to all XY address type solid-state imaging devices in which unit pixels are two-dimensionally arranged in a matrix.
 さらに、本技術は、可視光の入射光量の分布を検知して画像として撮像する固体撮像装置への適用に限らず、赤外線やX線、あるいは粒子等の入射量の分布を画像として撮像する固体撮像装置全般に対して適用可能である。 Furthermore, the present technology is not limited to application to a solid-state imaging device that detects the distribution of the amount of incident light of visible light and captures it as an image, but a solid-state that captures the distribution of the incident amount of infrared rays, X-rays, or particles as an image. Applicable to all imaging devices.
 なお、固体撮像装置はワンチップとして形成された形態であってもよいし、撮像部と、信号処理部又は光学系とがまとめてパッケージングされた撮像機能を有するモジュール状の形態であってもよい。 Note that the solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.
<8.固体撮像装置の使用例>
 図19は、上述の固体撮像装置の使用例を示す図である。
<8. Example of use of solid-state imaging device>
FIG. 19 is a diagram illustrating a usage example of the above-described solid-state imaging device.
 上述した固体撮像装置は、例えば、以下のように、可視光や、赤外光、紫外光、X線等の光をセンシングする様々なケースに使用することができる。 The solid-state imaging device described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows.
 ・デジタルカメラや、カメラ機能付きの携帯機器等の、鑑賞の用に供される画像を撮影する装置
 ・自動停止等の安全運転や、運転者の状態の認識等のために、自動車の前方や後方、周囲、車内等を撮影する車載用センサ、走行車両や道路を監視する監視カメラ、車両間等の測距を行う測距センサ等の、交通の用に供される装置
 ・ユーザのジェスチャを撮影して、そのジェスチャに従った機器操作を行うために、TVや、冷蔵庫、エアーコンディショナ等の家電に供される装置
 ・内視鏡や、赤外光の受光による血管撮影を行う装置等の、医療やヘルスケアの用に供される装置
 ・防犯用途の監視カメラや、人物認証用途のカメラ等の、セキュリティの用に供される装置
 ・肌を撮影する肌測定器や、頭皮を撮影するマイクロスコープ等の、美容の用に供され装置
 ・スポーツ用途等向けのアクションカメラやウェアラブルカメラ等の、スポーツの用に供される装置
 ・畑や作物の状態を監視するためのカメラ等の、農業の用に供される装置
・ Devices for taking images for viewing, such as digital cameras and mobile devices with camera functions ・ For safe driving such as automatic stop and recognition of the driver's condition, etc. Devices used for traffic, such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc. Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ・ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc. Equipment used for medical and health care ・ Security equipment such as security surveillance cameras and personal authentication cameras ・ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports, such as action cameras and wearable cameras for sports applications, etc. Equipment used for agriculture, such as cameras for monitoring the condition of fields and crops
{撮像装置}
 図20は、本技術を適用した電子機器の一例である撮像装置(カメラ装置)400の構成例を示すブロック図である。
{Imaging device}
FIG. 20 is a block diagram illustrating a configuration example of an imaging apparatus (camera apparatus) 400 that is an example of an electronic apparatus to which the present technology is applied.
 図20に示すように、撮像装置400は、レンズ群401などを含む光学系、撮像素子402、カメラ信号処理部であるDSP回路403、フレームメモリ404、表示装置405、記録装置406、操作系407、及び、電源系408等を有している。そして、DSP回路403、フレームメモリ404、表示装置405、記録装置406、操作系407、及び、電源系408がバスライン409を介して相互に接続された構成となっている。 As illustrated in FIG. 20, the imaging apparatus 400 includes an optical system including a lens group 401, an imaging element 402, a DSP circuit 403 that is a camera signal processing unit, a frame memory 404, a display device 405, a recording device 406, and an operation system 407. And a power supply system 408 and the like. The DSP circuit 403, the frame memory 404, the display device 405, the recording device 406, the operation system 407, and the power supply system 408 are connected to each other via a bus line 409.
 レンズ群401は、被写体からの入射光(像光)を取り込んで撮像素子402の撮像面上に結像する。撮像素子402は、レンズ群401によって撮像面上に結像された入射光の光量を画素単位で電気信号に変換して画素信号として出力する。 The lens group 401 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 402. The imaging element 402 converts the amount of incident light imaged on the imaging surface by the lens group 401 into an electrical signal in units of pixels and outputs it as a pixel signal.
 表示装置405は、液晶表示装置や有機EL(electro luminescence)表示装置等のパネル型表示装置から成り、撮像素子402で撮像された動画又は静止画を表示する。記録装置406は、撮像素子402で撮像された動画又は静止画を、メモリカードやビデオテープやDVD(Digital Versatile Disk)等の記録媒体に記録する。 The display device 405 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image sensor 402. The recording device 406 records the moving image or still image captured by the image sensor 402 on a recording medium such as a memory card, a video tape, or a DVD (Digital Versatile Disk).
 操作系407は、ユーザによる操作の下に、本撮像装置400が持つ様々な機能について操作指令を発する。電源系408は、DSP回路403、フレームメモリ404、表示装置405、記録装置406、及び、操作系407の動作電源となる各種の電源を、これら供給対象に対して適宜供給する。 The operation system 407 issues operation commands for various functions of the imaging apparatus 400 under the operation of the user. The power supply system 408 appropriately supplies various power supplies serving as operation power supplies for the DSP circuit 403, the frame memory 404, the display device 405, the recording device 406, and the operation system 407 to these supply targets.
 このような撮像装置400は、ビデオカメラやデジタルスチルカメラ、更には、スマートフォン、携帯電話機等のモバイル機器向けカメラモジュールに適用される。そして、この撮像装置400において、撮像素子402として、上述した各実施形態に係る固体撮像装置を用いることができる。これにより、撮像装置400の画質を向上させることができる。 Such an imaging apparatus 400 is applied to a camera module for a mobile device such as a video camera, a digital still camera, and a smartphone or a mobile phone. In the imaging apparatus 400, the solid-state imaging apparatus according to each of the above-described embodiments can be used as the imaging element 402. Thereby, the image quality of the imaging device 400 can be improved.
{移動体への応用例}
 また、例えば、本開示に係る技術(本技術)は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。
{Application examples to mobile objects}
In addition, for example, the technology according to the present disclosure (present technology) is mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, and a robot. It may be realized as a device.
 図21は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。 FIG. 21 is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a mobile control system to which the technology according to the present disclosure can be applied.
 車両制御システム12000は、通信ネットワーク12001を介して接続された複数の電子制御ユニットを備える。図21に示した例では、車両制御システム12000は、駆動系制御ユニット12010、ボディ系制御ユニット12020、車外情報検出ユニット12030、車内情報検出ユニット12040、及び統合制御ユニット12050を備える。また、統合制御ユニット12050の機能構成として、マイクロコンピュータ12051、音声画像出力部12052、及び車載ネットワークI/F(interface)12053が図示されている。 The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example illustrated in FIG. 21, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. As a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.
 駆動系制御ユニット12010は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット12010は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。 The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 includes a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism that adjusts and a braking device that generates a braking force of the vehicle.
 ボディ系制御ユニット12020は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット12020は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット12020には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット12020は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。 The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a blinker, or a fog lamp. In this case, the body control unit 12020 can be input with radio waves transmitted from a portable device that substitutes for a key or signals from various switches. The body system control unit 12020 receives input of these radio waves or signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle.
 車外情報検出ユニット12030は、車両制御システム12000を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット12030には、撮像部12031が接続される。車外情報検出ユニット12030は、撮像部12031に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット12030は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。 The vehicle outside information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The vehicle outside information detection unit 12030 may perform an object detection process or a distance detection process such as a person, a car, an obstacle, a sign, or a character on a road surface based on the received image.
 撮像部12031は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部12031は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部12031が受光する光は、可視光であっても良いし、赤外線等の非可視光であっても良い。 The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging unit 12031 can output an electrical signal as an image, or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared rays.
 車内情報検出ユニット12040は、車内の情報を検出する。車内情報検出ユニット12040には、例えば、運転者の状態を検出する運転者状態検出部12041が接続される。運転者状態検出部12041は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット12040は、運転者状態検出部12041から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。 The vehicle interior information detection unit 12040 detects vehicle interior information. For example, a driver state detection unit 12041 that detects a driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver is asleep.
 マイクロコンピュータ12051は、車外情報検出ユニット12030又は車内情報検出ユニット12040で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット12010に対して制御指令を出力することができる。例えば、マイクロコンピュータ12051は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むADAS(Advanced Driver Assistance System)の機能実現を目的とした協調制御を行うことができる。 The microcomputer 12051 calculates a control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside / outside the vehicle acquired by the vehicle outside information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, following traveling based on inter-vehicle distance, vehicle speed maintenance traveling, vehicle collision warning, or vehicle lane departure warning. It is possible to perform cooperative control for the purpose.
 また、マイクロコンピュータ12051は、車外情報検出ユニット12030又は車内情報検出ユニット12040で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 Further, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of automatic driving that autonomously travels without depending on the operation.
 また、マイクロコンピュータ12051は、車外情報検出ユニット12030で取得される車外の情報に基づいて、ボディ系制御ユニット12020に対して制御指令を出力することができる。例えば、マイクロコンピュータ12051は、車外情報検出ユニット12030で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。 Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare, such as switching from a high beam to a low beam. It can be carried out.
 音声画像出力部12052は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図21の例では、出力装置として、オーディオスピーカ12061、表示部12062及びインストルメントパネル12063が例示されている。表示部12062は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。 The sound image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying information to a vehicle occupant or the outside of the vehicle. In the example of FIG. 21, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.
 図22は、撮像部12031の設置位置の例を示す図である。 FIG. 22 is a diagram illustrating an example of an installation position of the imaging unit 12031.
 図22では、車両12100は、撮像部12031として、撮像部12101,12102,12103,12104,12105を有する。 In FIG. 22, the vehicle 12100 includes imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.
 撮像部12101,12102,12103,12104,12105は、例えば、車両12100のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部12101及び車室内のフロントガラスの上部に備えられる撮像部12105は、主として車両12100の前方の画像を取得する。サイドミラーに備えられる撮像部12102,12103は、主として車両12100の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部12104は、主として車両12100の後方の画像を取得する。撮像部12101及び12105で取得される前方の画像は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。 The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper part of a windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The imaging units 12102 and 12103 provided in the side mirror mainly acquire an image of the side of the vehicle 12100. The imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used for detection of a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
 なお、図22には、撮像部12101ないし12104の撮影範囲の一例が示されている。撮像範囲12111は、フロントノーズに設けられた撮像部12101の撮像範囲を示し、撮像範囲12112,12113は、それぞれサイドミラーに設けられた撮像部12102,12103の撮像範囲を示し、撮像範囲12114は、リアバンパ又はバックドアに設けられた撮像部12104の撮像範囲を示す。例えば、撮像部12101ないし12104で撮像された画像データが重ね合わせられることにより、車両12100を上方から見た俯瞰画像が得られる。 FIG. 22 shows an example of the shooting range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively, and the imaging range 12114 The imaging range of the imaging part 12104 provided in the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image when the vehicle 12100 is viewed from above is obtained.
 撮像部12101ないし12104の少なくとも1つは、距離情報を取得する機能を有していてもよい。例えば、撮像部12101ないし12104の少なくとも1つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。 At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
 例えば、マイクロコンピュータ12051は、撮像部12101ないし12104から得られた距離情報を基に、撮像範囲12111ないし12114内における各立体物までの距離と、この距離の時間的変化(車両12100に対する相対速度)を求めることにより、特に車両12100の進行路上にある最も近い立体物で、車両12100と略同じ方向に所定の速度(例えば、0km/h以上)で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ12051は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御(追従停止制御も含む)や自動加速制御(追従発進制御も含む)等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 For example, the microcomputer 12051, based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object in the imaging range 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100). In particular, it is possible to extract, as a preceding vehicle, a three-dimensional object that travels at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100, particularly the closest three-dimensional object on the traveling path of the vehicle 12100. it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Thus, cooperative control for the purpose of autonomous driving or the like autonomously traveling without depending on the operation of the driver can be performed.
 例えば、マイクロコンピュータ12051は、撮像部12101ないし12104から得られた距離情報を元に、立体物に関する立体物データを、2輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ12051は、車両12100の周辺の障害物を、車両12100のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ12051は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ12061や表示部12062を介してドライバに警報を出力することや、駆動系制御ユニット12010を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。 For example, the microcomputer 12051 converts the three-dimensional object data related to the three-dimensional object to other three-dimensional objects such as a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and a utility pole based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 is connected via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration or avoidance steering via the drive system control unit 12010, driving assistance for collision avoidance can be performed.
 撮像部12101ないし12104の少なくとも1つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ12051は、撮像部12101ないし12104の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部12101ないし12104の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ12051が、撮像部12101ないし12104の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部12052は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部12062を制御する。また、音声画像出力部12052は、歩行者を示すアイコン等を所望の位置に表示するように表示部12062を制御してもよい。 At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is, for example, whether or not the user is a pedestrian by performing a pattern matching process on a sequence of feature points indicating the outline of an object and a procedure for extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras. It is carried out by the procedure for determining. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 has a rectangular contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to be superimposed and displayed. Moreover, the audio | voice image output part 12052 may control the display part 12062 so that the icon etc. which show a pedestrian may be displayed on a desired position.
 以上、本開示に係る技術が適用され得る車両制御システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、例えば、撮像部12031に適用され得る。具体的には、例えば、図1乃至図3のCMOSイメージセンサ10乃至CMOSイメージセンサ10Bは、撮像部12031に適用することができる。撮像部12031に本開示に係る技術を適用することにより、例えば、撮像部12031のダイナミックレンジを拡大することができる。その結果、例えば、LEDフリッカの発生、アーチファクトの発生、解像度の低下等を抑制することができる。 Heretofore, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. Of the configurations described above, the technology according to the present disclosure may be applied to the imaging unit 12031, for example. Specifically, for example, the CMOS image sensor 10 to the CMOS image sensor 10B in FIGS. 1 to 3 can be applied to the imaging unit 12031. By applying the technique according to the present disclosure to the imaging unit 12031, for example, the dynamic range of the imaging unit 12031 can be expanded. As a result, for example, generation of LED flicker, generation of artifacts, reduction in resolution, and the like can be suppressed.
 なお、本技術の実施の形態は、上述した実施の形態に限定されるものではなく、本技術の要旨を逸脱しない範囲において種々の変更が可能である。 Note that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.
 また、例えば、本技術は以下のような構成も取ることができる。 Also, for example, the present technology can take the following configurations.
(1)
 複数の単位画素が配置されている画素アレイ部と、
 前記単位画素の動作を制御する駆動部と
 を備え、
 前記単位画素は、
  第1の光電変換部と、
  前記第1の光電変換部より感度が低い第2の光電変換部と、
  前記第2の光電変換部が生成した電荷を蓄積する電荷蓄積部と、
  第1の電荷電圧変換部と、
  第2の電荷電圧変換部と、
  前記第1の光電変換部から前記第1の電荷電圧変換部に電荷を転送する第1の転送ゲート部と、
  前記第2の電荷電圧変換部と前記電荷蓄積部のポテンシャルを結合する第2の転送ゲート部と、
  前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合する第3の転送ゲート部と
 を備え、
 前記駆動部は、前記第1の光電変換部が生成した第1の電荷を前記第1の電荷電圧変換部に蓄積した状態における第1のデータ信号、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域に前記第1の電荷を蓄積した状態における第2のデータ信号、並びに、前記第2の光電変換部が生成した第2の電荷に基づく第3のデータ信号を読み出すように制御する
 固体撮像装置。
(2)
 前記駆動部は、前記第1の電荷電圧変換部をリセットした状態における第1のリセット信号、並びに、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域をリセットした状態における第2のリセット信号を読み出すように制御する
 前記(1)に記載の固体撮像装置。
(3)
 前記駆動部は、前記第1の電荷電圧変換部、前記第2の電荷電圧変換部、及び、前記電荷蓄積部のポテンシャルを結合した領域に前記第2の電荷を蓄積した状態において前記第3のデータ信号を読み出すとともに、前記第1の電荷電圧変換部、前記第2の電荷電圧変換部、及び、前記電荷蓄積部のポテンシャルを結合した領域をリセットした状態における第3のリセット信号を読み出すように制御する
 前記(2)に記載の固体撮像装置。
(4)
 前記第1のデータ信号と前記第1のリセット信号との差分である第1の差分信号、前記第2のデータ信号と前記第2のリセット信号との差分である第2の差分信号、及び、前記第3のデータ信号と前記第3のリセット信号との差分である第3の差分信号を生成する信号処理部を
 さらに備える前記(3)に記載の固体撮像装置。
(5)
 前記信号処理部は、前記第1の差分信号の値が所定の第1の閾値以下の場合、前記第1の差分信号を前記単位画素の画素信号に用い、前記第1の差分信号の値が前記第1の閾値を超え、前記第2の差分信号の値が所定の第2の閾値以下の場合、前記第2の差分信号を前記単位画素の画素信号に用い、前記第2の差分信号の値が前記第2の閾値を超える場合、前記第3の差分信号を前記単位画素の画素信号に用いる
 前記(4)に記載の固体撮像装置。
(6)
 前記信号処理部は、前記第1の差分信号、前記第2の差分信号、及び、前記第3の差分信号のうち少なくとも1つの値に基づいて設定した合成比率で前記第1の差分信号、前記第2の差分信号、及び、前記第3の差分信号を合成することにより、前記単位画素の画素信号を生成する
 前記(4)に記載の固体撮像装置。
(7)
 前記駆動部は、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域をリセットした状態において、前記第2のリセット信号を読み出し、次に、前記第3の転送ゲート部を非導通状態にした状態において、前記第1のリセット信号を読み出し、次に、前記第1の転送ゲート部を導通状態にし、前記第1の電荷を前記第1の電荷電圧変換部に転送した状態において、前記第1のデータ信号を読み出し、次に、前記第3の転送ゲート部を導通状態にした状態において、前記第2のデータ信号を読み出すように制御する
 前記(2)乃至(6)のいずれかに記載の固体撮像装置。
(8)
 前記駆動部は、前記第1の電荷電圧変換部、前記第2の電荷電圧変換部、及び、前記電荷蓄積部のポテンシャルを結合した領域に前記第2の電荷を蓄積した状態において前記第3のデータ信号を読み出すように制御する
 前記(1)又は(2)に記載の固体撮像装置。
(9)
 前記単位画素は、
  前記第2の光電変換部から前記電荷蓄積部に電荷を転送する第4の転送ゲート部と、
  前記第4の転送ゲート部のゲート電極の下部に形成され、前記第2の光電変換部から溢れた電荷を前記電荷蓄積部に転送するオーバーフローパスと
 をさらに備える前記(1)乃至(8)のいずれかに記載の固体撮像装置。
(10)
 前記第2の光電変換部と前記電荷蓄積部とが転送ゲート部を介さずに接続されている
 前記(1)乃至(8)のいずれかに固体撮像装置。
(11)
 前記電荷蓄積部の対向電極を可変電圧電源に接続し、
 前記駆動部は、前記電荷蓄積部に電荷を蓄積する期間において、前記電荷蓄積部に蓄積された電荷に基づく信号を読み出す期間より、前記電荷蓄積部の対向電極に印加される電圧を低くする
 前記(1)乃至(10)のいずれかに記載の固体撮像装置。
(12)
 所定の電圧の電源と前記第2の電荷電圧変換部との間に接続されているリセットゲート部を
 さらに備える前記(1)乃至(11)のいずれかに記載の固体撮像装置。
(13)
 複数の単位画素が配置されている画素アレイ部と、
 前記単位画素の動作を制御する駆動部と
 を備え、
 前記単位画素は、
  第1の光電変換部と、
  前記第1の光電変換部より感度が低い第2の光電変換部と、
  前記第2の光電変換部が生成した電荷を蓄積する電荷蓄積部と、
  第1の電荷電圧変換部と、
  第2の電荷電圧変換部と、
  前記第1の光電変換部から前記第1の電荷電圧変換部に電荷を転送する第1の転送ゲート部と、
  前記第2の電荷電圧変換部と前記電荷蓄積部のポテンシャルを結合する第2の転送ゲート部と、
  前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合する第3の転送ゲート部と
 を備える固体撮像装置が、
 前記第1の光電変換部が生成した第1の電荷を前記第1の電荷電圧変換部に蓄積した状態における第1のデータ信号、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域に前記第1の電荷を蓄積した状態における第2のデータ信号、並びに、前記第2の光電変換部が生成した第2の電荷に基づく第3のデータ信号を読み出すように制御する
 固体撮像装置の駆動方法。
(14)
 複数の単位画素が配置されている画素アレイ部と、
 前記単位画素の動作を制御する駆動部と
 を備え、
 前記単位画素は、
  第1の光電変換部と、
  前記第1の光電変換部より感度が低い第2の光電変換部と、
  前記第2の光電変換部が生成した電荷を蓄積する電荷蓄積部と、
  第1の電荷電圧変換部と、
  第2の電荷電圧変換部と、
  前記第1の光電変換部から前記第1の電荷電圧変換部に電荷を転送する第1の転送ゲート部と、
  前記第2の電荷電圧変換部と前記電荷蓄積部のポテンシャルを結合する第2の転送ゲート部と、
  前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合する第3の転送ゲート部と
 を備え、
 前記第1の光電変換部が生成した第1の電荷を前記第1の電荷電圧変換部に蓄積した状態における第1のデータ信号、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域に前記第1の電荷を蓄積した状態における第2のデータ信号、並びに、前記第2の光電変換部が生成した第2の電荷に基づく第3のデータ信号を読み出すように制御する固体撮像装置と、
 前記固体撮像装置からの信号を処理する信号処理装置と
 を備える電子機器。
(1)
A pixel array unit in which a plurality of unit pixels are arranged;
A drive unit for controlling the operation of the unit pixel,
The unit pixel is
A first photoelectric conversion unit;
A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit;
A charge storage section for storing the charge generated by the second photoelectric conversion section;
A first charge-voltage converter,
A second charge-voltage converter,
A first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge-voltage conversion unit;
A second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
A third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter;
The driving unit includes a first data signal in a state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge voltage conversion unit, the first charge voltage conversion unit, and the first charge voltage conversion unit. A second data signal in a state where the first charge is accumulated in a region where the potentials of the two charge-voltage conversion units are combined, and a third charge based on the second charge generated by the second photoelectric conversion unit. A solid-state imaging device that controls to read data signals.
(2)
The drive unit includes a first reset signal in a state where the first charge voltage conversion unit is reset, and a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined. The solid-state imaging device according to (1), wherein control is performed so as to read a second reset signal in a reset state.
(3)
The driving unit is configured to store the second charge in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined. A data signal is read out, and a third reset signal in a state in which a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined is reset is read out. The solid-state imaging device according to (2).
(4)
A first difference signal that is a difference between the first data signal and the first reset signal; a second difference signal that is a difference between the second data signal and the second reset signal; and The solid-state imaging device according to (3), further including a signal processing unit that generates a third differential signal that is a difference between the third data signal and the third reset signal.
(5)
The signal processing unit uses the first difference signal as a pixel signal of the unit pixel when the value of the first difference signal is equal to or less than a predetermined first threshold, and the value of the first difference signal is When the first threshold value is exceeded and the value of the second difference signal is less than or equal to a predetermined second threshold value, the second difference signal is used as a pixel signal of the unit pixel, and the second difference signal The solid-state imaging device according to (4), wherein when the value exceeds the second threshold, the third difference signal is used as a pixel signal of the unit pixel.
(6)
The signal processing unit includes the first difference signal, the first difference signal at a combination ratio set based on at least one value of the first difference signal, the second difference signal, and the third difference signal, The solid-state imaging device according to (4), wherein a pixel signal of the unit pixel is generated by combining the second difference signal and the third difference signal.
(7)
The drive unit reads the second reset signal in a state where the region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined is reset, and then the third charge voltage conversion unit In a state where the transfer gate portion is in a non-conducting state, the first reset signal is read, then the first transfer gate portion is brought into a conducting state, and the first charge is converted into the first charge-voltage converting portion The first data signal is read in the state transferred to, and then the second data signal is read in the state where the third transfer gate portion is turned on. (6) The solid-state imaging device according to any one of (6).
(8)
The driving unit is configured to store the second charge in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined. The solid-state imaging device according to (1) or (2), wherein control is performed so as to read out a data signal.
(9)
The unit pixel is
A fourth transfer gate section for transferring charges from the second photoelectric conversion section to the charge storage section;
An overflow path formed under the gate electrode of the fourth transfer gate portion and transferring the charge overflowing from the second photoelectric conversion portion to the charge storage portion; The solid-state imaging device according to any one of the above.
(10)
The solid-state imaging device according to any one of (1) to (8), wherein the second photoelectric conversion unit and the charge storage unit are connected without a transfer gate unit.
(11)
Connecting the counter electrode of the charge storage unit to a variable voltage power supply;
The drive unit lowers a voltage applied to the counter electrode of the charge storage unit in a period in which charges are stored in the charge storage unit, compared to a period in which a signal based on charges stored in the charge storage unit is read (1) The solid-state imaging device according to any one of (10).
(12)
The solid-state imaging device according to any one of (1) to (11), further including a reset gate unit connected between a power source having a predetermined voltage and the second charge-voltage conversion unit.
(13)
A pixel array unit in which a plurality of unit pixels are arranged;
A drive unit for controlling the operation of the unit pixel,
The unit pixel is
A first photoelectric conversion unit;
A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit;
A charge storage section for storing the charge generated by the second photoelectric conversion section;
A first charge-voltage converter,
A second charge-voltage converter,
A first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge-voltage conversion unit;
A second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
A solid-state imaging device comprising: a first transfer voltage unit that combines a potential of the first charge voltage conversion unit and a potential of the second charge voltage conversion unit.
The first data signal in the state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first charge-voltage conversion unit, and the second charge-voltage conversion A second data signal in a state where the first charge is accumulated in a region where the potentials of the first and second parts are combined, and a third data signal based on the second charge generated by the second photoelectric conversion unit. A method for driving the solid-state imaging device.
(14)
A pixel array unit in which a plurality of unit pixels are arranged;
A drive unit for controlling the operation of the unit pixel,
The unit pixel is
A first photoelectric conversion unit;
A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit;
A charge storage section for storing the charge generated by the second photoelectric conversion section;
A first charge-voltage converter,
A second charge-voltage converter,
A first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge-voltage conversion unit;
A second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
A third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter;
The first data signal in the state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first charge-voltage conversion unit, and the second charge-voltage conversion A second data signal in a state where the first charge is accumulated in a region where the potentials of the first and second parts are combined, and a third data signal based on the second charge generated by the second photoelectric conversion unit. A solid-state imaging device to be controlled
An electronic device comprising: a signal processing device that processes a signal from the solid-state imaging device.
 10,10A,10B CMOSイメージセンサ, 11 画素アレイ部, 12 垂直駆動部, 13 カラム処理部, 14 水平駆動部, 15 システム制御部, 16 画素駆動線, 17 垂直信号線, 18 信号処理部, 19 データ格納部, 100A乃至100D 単位画素, 101a 第1光電変換部, 101b 第2光電変換部, 102a乃至102d 第1乃至第4転送ゲート部, 103 リセットゲート部, 104 電荷蓄積部, 105a 第1FD部, 105b 第2FD部, 106 増幅トランジスタ, 107 選択トランジスタ, 400 撮像装置, 402 撮像素子, 403 DSP回路 10, 10A, 10B CMOS image sensor, 11 pixel array unit, 12 vertical drive unit, 13 column processing unit, 14 horizontal drive unit, 15 system control unit, 16 pixel drive line, 17 vertical signal line, 18 signal processing unit, 19 Data storage unit, 100A to 100D unit pixel, 101a first photoelectric conversion unit, 101b second photoelectric conversion unit, 102a to 102d first to fourth transfer gate unit, 103 reset gate unit, 104 charge storage unit, 105a first FD unit , 105b 2nd FD section, 106 amplification transistor, 107 selection transistor, 400 image pickup device, 402 image pickup device, 403 DSP circuit

Claims (14)

  1.  複数の単位画素が配置されている画素アレイ部と、
     前記単位画素の動作を制御する駆動部と
     を備え、
     前記単位画素は、
      第1の光電変換部と、
      前記第1の光電変換部より感度が低い第2の光電変換部と、
      前記第2の光電変換部が生成した電荷を蓄積する電荷蓄積部と、
      第1の電荷電圧変換部と、
      第2の電荷電圧変換部と、
      前記第1の光電変換部から前記第1の電荷電圧変換部に電荷を転送する第1の転送ゲート部と、
      前記第2の電荷電圧変換部と前記電荷蓄積部のポテンシャルを結合する第2の転送ゲート部と、
      前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合する第3の転送ゲート部と
     を備え、
     前記駆動部は、前記第1の光電変換部が生成した第1の電荷を前記第1の電荷電圧変換部に蓄積した状態における第1のデータ信号、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域に前記第1の電荷を蓄積した状態における第2のデータ信号、並びに、前記第2の光電変換部が生成した第2の電荷に基づく第3のデータ信号を読み出すように制御する
     固体撮像装置。
    A pixel array unit in which a plurality of unit pixels are arranged;
    A drive unit for controlling the operation of the unit pixel,
    The unit pixel is
    A first photoelectric conversion unit;
    A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit;
    A charge storage section for storing the charge generated by the second photoelectric conversion section;
    A first charge-voltage converter,
    A second charge-voltage converter,
    A first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge-voltage conversion unit;
    A second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
    A third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter;
    The driving unit includes a first data signal in a state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge voltage conversion unit, the first charge voltage conversion unit, and the first charge voltage conversion unit. A second data signal in a state where the first charge is accumulated in a region where the potentials of the two charge-voltage conversion units are combined, and a third charge based on the second charge generated by the second photoelectric conversion unit. A solid-state imaging device that controls to read data signals.
  2.  前記駆動部は、前記第1の電荷電圧変換部をリセットした状態における第1のリセット信号、並びに、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域をリセットした状態における第2のリセット信号を読み出すように制御する
     請求項1に記載の固体撮像装置。
    The drive unit includes a first reset signal in a state where the first charge voltage conversion unit is reset, and a region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined. The solid-state imaging device according to claim 1, wherein control is performed so that a second reset signal in a reset state is read out.
  3.  前記駆動部は、前記第1の電荷電圧変換部、前記第2の電荷電圧変換部、及び、前記電荷蓄積部のポテンシャルを結合した領域に前記第2の電荷を蓄積した状態において前記第3のデータ信号を読み出すとともに、前記第1の電荷電圧変換部、前記第2の電荷電圧変換部、及び、前記電荷蓄積部のポテンシャルを結合した領域をリセットした状態における第3のリセット信号を読み出すように制御する
     請求項2に記載の固体撮像装置。
    The driving unit is configured to store the second charge in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined. A data signal is read out, and a third reset signal in a state in which a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined is reset is read out. The solid-state imaging device according to claim 2 to be controlled.
  4.  前記第1のデータ信号と前記第1のリセット信号との差分である第1の差分信号、前記第2のデータ信号と前記第2のリセット信号との差分である第2の差分信号、及び、前記第3のデータ信号と前記第3のリセット信号との差分である第3の差分信号を生成する信号処理部を
     さらに備える請求項3に記載の固体撮像装置。
    A first difference signal that is a difference between the first data signal and the first reset signal; a second difference signal that is a difference between the second data signal and the second reset signal; and The solid-state imaging device according to claim 3, further comprising a signal processing unit that generates a third difference signal that is a difference between the third data signal and the third reset signal.
  5.  前記信号処理部は、前記第1の差分信号の値が所定の第1の閾値以下の場合、前記第1の差分信号を前記単位画素の画素信号に用い、前記第1の差分信号の値が前記第1の閾値を超え、前記第2の差分信号の値が所定の第2の閾値以下の場合、前記第2の差分信号を前記単位画素の画素信号に用い、前記第2の差分信号の値が前記第2の閾値を超える場合、前記第3の差分信号を前記単位画素の画素信号に用いる
     請求項4に記載の固体撮像装置。
    The signal processing unit uses the first difference signal as a pixel signal of the unit pixel when the value of the first difference signal is equal to or less than a predetermined first threshold, and the value of the first difference signal is When the first threshold value is exceeded and the value of the second difference signal is less than or equal to a predetermined second threshold value, the second difference signal is used as a pixel signal of the unit pixel, and the second difference signal The solid-state imaging device according to claim 4, wherein when the value exceeds the second threshold, the third difference signal is used as a pixel signal of the unit pixel.
  6.  前記信号処理部は、前記第1の差分信号、前記第2の差分信号、及び、前記第3の差分信号のうち少なくとも1つの値に基づいて設定した合成比率で前記第1の差分信号、前記第2の差分信号、及び、前記第3の差分信号を合成することにより、前記単位画素の画素信号を生成する
     請求項4に記載の固体撮像装置。
    The signal processing unit includes the first difference signal, the first difference signal at a combination ratio set based on at least one value of the first difference signal, the second difference signal, and the third difference signal, The solid-state imaging device according to claim 4, wherein a pixel signal of the unit pixel is generated by combining the second difference signal and the third difference signal.
  7.  前記駆動部は、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域をリセットした状態において、前記第2のリセット信号を読み出し、次に、前記第3の転送ゲート部を非導通状態にした状態において、前記第1のリセット信号を読み出し、次に、前記第1の転送ゲート部を導通状態にし、前記第1の電荷を前記第1の電荷電圧変換部に転送した状態において、前記第1のデータ信号を読み出し、次に、前記第3の転送ゲート部を導通状態にした状態において、前記第2のデータ信号を読み出すように制御する
     請求項2に記載の固体撮像装置。
    The drive unit reads the second reset signal in a state where the region where the potentials of the first charge voltage conversion unit and the second charge voltage conversion unit are combined is reset, and then the third charge voltage conversion unit In a state where the transfer gate portion is in a non-conducting state, the first reset signal is read, and then the first transfer gate portion is brought into a conducting state, and the first charge is converted into the first charge-voltage converting portion. 3. The control is performed so that the first data signal is read in a state where the second data signal is transferred, and then the second data signal is read in a state where the third transfer gate unit is in a conductive state. Solid-state imaging device.
  8.  前記駆動部は、前記第1の電荷電圧変換部、前記第2の電荷電圧変換部、及び、前記電荷蓄積部のポテンシャルを結合した領域に前記第2の電荷を蓄積した状態において前記第3のデータ信号を読み出すように制御する
     請求項1に記載の固体撮像装置。
    The driving unit is configured to store the second charge in a region where the potentials of the first charge voltage conversion unit, the second charge voltage conversion unit, and the charge storage unit are combined. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is controlled to read a data signal.
  9.  前記単位画素は、
      前記第2の光電変換部から前記電荷蓄積部に電荷を転送する第4の転送ゲート部と、
      前記第4の転送ゲート部のゲート電極の下部に形成され、前記第2の光電変換部から溢れた電荷を前記電荷蓄積部に転送するオーバーフローパスと
     をさらに備える請求項1に記載の固体撮像装置。
    The unit pixel is
    A fourth transfer gate section for transferring charges from the second photoelectric conversion section to the charge storage section;
    2. The solid-state imaging device according to claim 1, further comprising: an overflow path formed below the gate electrode of the fourth transfer gate unit and transferring the charge overflowing from the second photoelectric conversion unit to the charge storage unit. .
  10.  前記第2の光電変換部と前記電荷蓄積部とが転送ゲート部を介さずに接続されている
     請求項1に記載の固体撮像装置。
    The solid-state imaging device according to claim 1, wherein the second photoelectric conversion unit and the charge storage unit are connected without a transfer gate unit.
  11.  前記電荷蓄積部の対向電極を可変電圧電源に接続し、
     前記駆動部は、前記電荷蓄積部に電荷を蓄積する期間において、前記電荷蓄積部に蓄積された電荷に基づく信号を読み出す期間より、前記電荷蓄積部の対向電極に印加される電圧を低くする
     請求項1に記載の固体撮像装置。
    Connecting the counter electrode of the charge storage unit to a variable voltage power supply;
    The drive unit lowers a voltage applied to the counter electrode of the charge storage unit in a period in which charges are stored in the charge storage unit, compared to a period in which a signal based on the charges stored in the charge storage unit is read. Item 2. The solid-state imaging device according to Item 1.
  12.  所定の電圧の電源と前記第2の電荷電圧変換部との間に接続されているリセットゲート部を
     さらに備える請求項1に記載の固体撮像装置。
    The solid-state imaging device according to claim 1, further comprising a reset gate unit connected between a power source having a predetermined voltage and the second charge voltage conversion unit.
  13.  複数の単位画素が配置されている画素アレイ部と、
     前記単位画素の動作を制御する駆動部と
     を備え、
     前記単位画素は、
      第1の光電変換部と、
      前記第1の光電変換部より感度が低い第2の光電変換部と、
      前記第2の光電変換部が生成した電荷を蓄積する電荷蓄積部と、
      第1の電荷電圧変換部と、
      第2の電荷電圧変換部と、
      前記第1の光電変換部から前記第1の電荷電圧変換部に電荷を転送する第1の転送ゲート部と、
      前記第2の電荷電圧変換部と前記電荷蓄積部のポテンシャルを結合する第2の転送ゲート部と、
      前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合する第3の転送ゲート部と
     を備える固体撮像装置が、
     前記第1の光電変換部が生成した第1の電荷を前記第1の電荷電圧変換部に蓄積した状態における第1のデータ信号、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域に前記第1の電荷を蓄積した状態における第2のデータ信号、並びに、前記第2の光電変換部が生成した第2の電荷に基づく第3のデータ信号を読み出すように制御する
     固体撮像装置の駆動方法。
    A pixel array unit in which a plurality of unit pixels are arranged;
    A drive unit for controlling the operation of the unit pixel,
    The unit pixel is
    A first photoelectric conversion unit;
    A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit;
    A charge storage section for storing the charge generated by the second photoelectric conversion section;
    A first charge-voltage converter,
    A second charge-voltage converter,
    A first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge-voltage conversion unit;
    A second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
    A solid-state imaging device comprising: a first transfer voltage unit that combines a potential of the first charge voltage conversion unit and a potential of the second charge voltage conversion unit.
    The first data signal in the state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first charge-voltage conversion unit, and the second charge-voltage conversion A second data signal in a state where the first charge is accumulated in a region where the potentials of the first and second parts are combined, and a third data signal based on the second charge generated by the second photoelectric conversion unit. A method for driving the solid-state imaging device.
  14.  複数の単位画素が配置されている画素アレイ部と、
     前記単位画素の動作を制御する駆動部と
     を備え、
     前記単位画素は、
      第1の光電変換部と、
      前記第1の光電変換部より感度が低い第2の光電変換部と、
      前記第2の光電変換部が生成した電荷を蓄積する電荷蓄積部と、
      第1の電荷電圧変換部と、
      第2の電荷電圧変換部と、
      前記第1の光電変換部から前記第1の電荷電圧変換部に電荷を転送する第1の転送ゲート部と、
      前記第2の電荷電圧変換部と前記電荷蓄積部のポテンシャルを結合する第2の転送ゲート部と、
      前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合する第3の転送ゲート部と
     を備え、
     前記第1の光電変換部が生成した第1の電荷を前記第1の電荷電圧変換部に蓄積した状態における第1のデータ信号、前記第1の電荷電圧変換部と前記第2の電荷電圧変換部のポテンシャルを結合した領域に前記第1の電荷を蓄積した状態における第2のデータ信号、並びに、前記第2の光電変換部が生成した第2の電荷に基づく第3のデータ信号を読み出すように制御する固体撮像装置と、
     前記固体撮像装置からの信号を処理する信号処理装置と
     を備える電子機器。
    A pixel array unit in which a plurality of unit pixels are arranged;
    A drive unit for controlling the operation of the unit pixel,
    The unit pixel is
    A first photoelectric conversion unit;
    A second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit;
    A charge storage section for storing the charge generated by the second photoelectric conversion section;
    A first charge-voltage converter,
    A second charge-voltage converter,
    A first transfer gate unit that transfers charges from the first photoelectric conversion unit to the first charge-voltage conversion unit;
    A second transfer gate unit that couples the potential of the second charge-voltage converter and the charge storage unit;
    A third transfer gate unit that couples the potentials of the first charge voltage converter and the second charge voltage converter;
    The first data signal in the state where the first charge generated by the first photoelectric conversion unit is accumulated in the first charge-voltage conversion unit, the first charge-voltage conversion unit, and the second charge-voltage conversion A second data signal in a state where the first charge is accumulated in a region where the potentials of the first and second parts are combined, and a third data signal based on the second charge generated by the second photoelectric conversion unit. A solid-state imaging device to be controlled
    An electronic device comprising: a signal processing device that processes a signal from the solid-state imaging device.
PCT/JP2017/009366 2016-03-23 2017-03-09 Solid state imaging apparatus, method for driving solid state imaging apparatus, and electronic device WO2017163890A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016058434A JP2017175345A (en) 2016-03-23 2016-03-23 Solid-state imaging device, method of driving the same, and electronic equipment
JP2016-058434 2016-03-23

Publications (1)

Publication Number Publication Date
WO2017163890A1 true WO2017163890A1 (en) 2017-09-28

Family

ID=59900192

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/009366 WO2017163890A1 (en) 2016-03-23 2017-03-09 Solid state imaging apparatus, method for driving solid state imaging apparatus, and electronic device

Country Status (2)

Country Link
JP (1) JP2017175345A (en)
WO (1) WO2017163890A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111164964A (en) * 2017-10-27 2020-05-15 索尼半导体解决方案公司 Image pickup apparatus and image pickup method
EP4109888A1 (en) * 2021-06-21 2022-12-28 Samsung Electronics Co., Ltd. Unit pixel circuit and image sensor including the same

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6474014B1 (en) 2017-07-05 2019-02-27 パナソニックIpマネジメント株式会社 Imaging device
US12075173B2 (en) 2019-12-17 2024-08-27 Sony Semiconductor Solutions Corporation Imaging element and electronic device with light shielding portion between pixels
JP7064537B2 (en) 2020-07-29 2022-05-10 ソニーセミコンダクタソリューションズ株式会社 Solid-state image sensor and its control method
JPWO2022172714A1 (en) * 2021-02-09 2022-08-18
JPWO2023026565A1 (en) 2021-08-26 2023-03-02

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010283573A (en) * 2009-06-04 2010-12-16 Nikon Corp Electronic camera
US20130256510A1 (en) * 2012-03-29 2013-10-03 Omnivision Technologies, Inc. Imaging device with floating diffusion switch
JP2014112760A (en) * 2012-12-05 2014-06-19 Sony Corp Solid-state image pickup device and electronic apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010283573A (en) * 2009-06-04 2010-12-16 Nikon Corp Electronic camera
US20130256510A1 (en) * 2012-03-29 2013-10-03 Omnivision Technologies, Inc. Imaging device with floating diffusion switch
JP2014112760A (en) * 2012-12-05 2014-06-19 Sony Corp Solid-state image pickup device and electronic apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111164964A (en) * 2017-10-27 2020-05-15 索尼半导体解决方案公司 Image pickup apparatus and image pickup method
CN111164964B (en) * 2017-10-27 2022-08-16 索尼半导体解决方案公司 Image pickup apparatus and image pickup method
EP4109888A1 (en) * 2021-06-21 2022-12-28 Samsung Electronics Co., Ltd. Unit pixel circuit and image sensor including the same
US11743610B2 (en) 2021-06-21 2023-08-29 Samsung Electronics Co., Ltd. Pixel and image sensor including the same
US12047696B2 (en) 2021-06-21 2024-07-23 Samsung Electronics Co., Ltd. Pixel and image sensor including the same

Also Published As

Publication number Publication date
JP2017175345A (en) 2017-09-28

Similar Documents

Publication Publication Date Title
TWI846754B (en) Solid-state imaging devices, signal processing chips, and electronic devices
JP7047166B2 (en) Solid-state image sensor
KR102552755B1 (en) Solid-state imaging devices and electronic devices
WO2017163890A1 (en) Solid state imaging apparatus, method for driving solid state imaging apparatus, and electronic device
KR20200112839A (en) Solid-state imaging device, imaging device, and control method of solid-state imaging device
CN111886857B (en) Solid-state image pickup device
JP2018148541A (en) Imaging device, control method therefor, and electronic apparatus
WO2020105314A1 (en) Solid-state imaging element and imaging device
WO2018190126A1 (en) Solid-state imaging device and electronic apparatus
JP2019012968A (en) Solid-state imaging device and electronic device
TW202103486A (en) Solid-state imaging device, electronic apparatus, and method for controlling solid-state imaging device
WO2018207666A1 (en) Imaging element, method for driving same, and electronic device
WO2019193801A1 (en) Solid-state imaging element, electronic apparatus, and method for controlling solid-state imaging element
WO2019239887A1 (en) Imaging element, control method, and electronic apparatus
WO2018139187A1 (en) Solid-state image capturing device, method for driving same, and electronic device
WO2020183809A1 (en) Solid-state imaging device, electronic apparatus, and method for controlling solid-state imaging device
WO2021157263A1 (en) Imaging device and electronic apparatus
WO2021095560A1 (en) Event detection device
WO2024004377A1 (en) Solid-state imaging element, imaging device, and method for controlling solid-state imaging element
WO2022201802A1 (en) Solid-state imaging device and electronic device
US12088942B2 (en) Imaging device and electronic device
WO2022201898A1 (en) Imaging element, and imaging device
WO2023276199A1 (en) Solid-state imaging element, electronic device, and method for controlling solid-state imaging element
WO2022158246A1 (en) Imaging device
TW202431859A (en) Solid-state imaging device

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17769935

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 17769935

Country of ref document: EP

Kind code of ref document: A1