TW202431859A - Solid-state imaging device - Google Patents

Abstract

The present technology relates to a solid-state imaging device that makes it possible to obtain an image with increased quality. This solid-state imaging device comprises a pixel array unit that has a plurality of unit pixels, the unit pixels including a first pixel, a second pixel having a lower sensitivity than the first pixel, and four charge storage capacitances provided between the first pixel and the second pixel. A switch transistor for coupling charge storage capacitances adjacent to each other are provided between the charge storage capacitances. The present technology can be applied to a CMOS image sensor.

Description

Solid-state imaging device

The present technology relates to a solid-state imaging device, and more particularly to a solid-state imaging device capable of obtaining higher quality images.

For example, in a solid-state imaging device for automotive use, it is required to ensure a wide dynamic range based on HDR (High Dynamic Range) and suppress LED (Light Emitting Diode) flicker.

To this end, the industry has proposed a technology that uses a sub-pixel structure in which a large pixel with high sensitivity, a small pixel with low sensitivity, and a capacitor within the pixel are provided within one pixel (for example, refer to Patent Document 1).

In this technology, for one exposure, the conversion efficiency is changed to read the signal from the large pixel twice, and the signal is also read from the small pixel, and the three signals (images) obtained in this way are synthesized to produce one image. In this way, LED flicker suppression can be achieved and a wide dynamic range can be ensured. [Prior technical literature] [Patent literature]

[Patent Document 1] Japanese Patent Application Publication No. 2017-163010

[The problem the invention is trying to solve]

However, in the above-mentioned technologies, sometimes it is not possible to obtain high-quality images.

Specifically, in the light intensity at the synthesis boundary between the signal of the large pixel and the signal of the small pixel, the SNR (Signal to Noise Ratio) of the image (signal) decreases sharply, so the image is blurred under the light intensity falling on the synthesis boundary. In other words, the image quality is reduced.

This technology was developed based on this situation and can obtain higher quality images. [Technical means to solve the problem]

A solid-state imaging device according to one aspect of the present technology includes a pixel array section having a plurality of unit pixels, wherein the unit pixels include: a first pixel, a second pixel having a lower sensitivity than the first pixel, and four charge storage capacitors disposed between the first pixel and the second pixel, and a switching transistor for coupling the charge storage capacitors is disposed between adjacent charge storage capacitors.

In one aspect of the present technology, a pixel array section is provided in a solid-state imaging device, and the pixel array section is provided with a plurality of unit pixels, and the unit pixels are provided with: a first pixel, a second pixel having a lower sensitivity than the first pixel, and four charge storage capacitors provided between the first pixel and the second pixel. Furthermore, a switching transistor for coupling the charge storage capacitors adjacent to each other is provided between the charge storage capacitors.

Hereinafter, an implementation form will be described by applying the present technology with reference to the drawings.

<First embodiment> <Structure example of CMOS image sensor> This technology can obtain higher quality images by setting up four or more charge storage capacitors in a pixel and configuring a switching transistor between adjacent charge storage capacitors.

FIG. 1 is a diagram showing a configuration example of a solid-state imaging element (solid-state imaging device) to which the present technology is applied, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor which is a type of X-Y address imaging device.

The CMOS image sensor 11 shown in FIG1 is, for example, a back-illuminated CMOS image sensor, and includes a pixel array section 21 formed on a semiconductor substrate (not shown), and a peripheral circuit section integrated on the same semiconductor substrate as the pixel array section 21. The peripheral circuit section is composed of, for example, a vertical driver section 22, a row processing section 23, a horizontal driver section 24, and a system control section 25.

The CMOS image sensor 11 further includes a signal processing unit 26 and a data storage unit 27. In addition, the signal processing unit 26 and the data storage unit 27 may be disposed on the same semiconductor substrate as the pixel array unit 21, or may be disposed on a semiconductor substrate different from the pixel array unit 21.

The pixel array section 21 is a structure in which unit pixels (hereinafter sometimes simply referred to as "pixels") of a photoelectric conversion section that generates and stores electric charge corresponding to the amount of received light are arranged two-dimensionally in the column direction and the row direction, that is, in a matrix shape.

Here, the row direction is the arrangement direction of pixels in the pixel row (horizontal direction), that is, the transverse direction in the figure, and the row direction is the arrangement direction of pixels in the pixel row (vertical direction), that is, the longitudinal direction in the figure.

In the pixel array section 21, for the matrix pixel arrangement, a pixel drive line 28 is wired in the column direction for each pixel column, and a vertical signal line 29 is wired in the row direction for each pixel row. The pixel drive line 28 is a signal line for supplying a drive signal (control signal) for driving the pixel, such as when reading a signal from the pixel. One end of the pixel drive line 28 is connected to an output end corresponding to each column of the vertical drive section 22.

In addition, here, in order to facilitate viewing of the figure, one pixel driving line 28 is drawn for one pixel column, but in fact, a plurality of pixel driving lines 28 are wired for one pixel column.

The vertical driving unit 22 is composed of, for example, a shift register or an address decoder, and drives each pixel of the pixel array unit 21 simultaneously or in row units.

For example, the vertical drive unit 22 is composed of two scanning systems: a readout scanning system and an exclusion scanning system.

The readout scanning system selects and scans the unit pixels of the pixel array section 21 in order in row units in order to read out the signal from the unit pixel. The signal read out from the unit pixel is an analog signal.

The exclusion scanning system performs exclusion scanning at a predetermined timing on the readout row scanned by the readout scanning system. By the exclusion scanning performed by the exclusion scanning system, unnecessary charges are eliminated from the photoelectric conversion part of the unit pixel of the readout row, thereby resetting the photoelectric conversion part.

The elimination (resetting) of unnecessary charges by the elimination scanning system realizes the so-called electronic shutter operation. The electronic shutter operation is an operation to reset the photoelectric conversion unit and restart exposure (start charge accumulation).

The signal read out by the readout operation of the readout scanning system corresponds to the amount of light received after the immediately preceding readout operation or the electronic shutter operation. Furthermore, the period from the readout timing of the immediately preceding readout operation or the rejection timing of the electronic shutter operation to the readout timing of the subsequent (this time) readout operation is the exposure period of the charge of the unit pixel.

The signal output from each unit pixel of the pixel row selected and scanned by the vertical driving section 22 is input to the row processing section 23 via the vertical signal line 29 for each pixel row.

The row processing unit 23 performs predetermined signal processing on the signals supplied from each pixel in the selected row via the vertical signal line 29 for each pixel row of the pixel array unit 21, and temporarily holds the pixel signals after the signal processing.

For example, the row processing unit 23 performs noise removal processing, CDS (Correlated Double Sampling) processing, DDS (Double Data Sampling) processing, AD (Analog to Digital) conversion processing, etc. as signal processing. For example, through CDS processing, reset noise and pixel-specific fixed pattern noise such as the threshold deviation of the amplifier transistor in the pixel are removed.

The horizontal driving section 24 is composed of a shift register or an address decoder, etc., and sequentially selects the unit circuits corresponding to the pixel rows of the row processing section 23. By the selection scanning performed by the horizontal driving section 24, the pixel signals processed by each unit circuit in the row processing section 23 are sequentially output.

The system control unit 25 is composed of a timing generator that generates various timing signals, and performs drive control of the vertical drive unit 22, the row processing unit 23, and the horizontal drive unit 24 based on the generated timing signals.

The signal processing unit 26 has at least a calculation processing function, and performs various signal processing such as calculation processing on the pixel signal output by the self-processing unit 23. When the signal processing is performed in the signal processing unit 26, the data storage unit 27 temporarily stores the data required for the processing.

<Other configuration examples of CMOS image sensor> In addition, the configuration of the CMOS image sensor to which this technology is applied is not limited to that shown in FIG. 1, and may also be configured as shown in FIG. 2 or FIG. 3. In addition, the same symbol is given to the parts corresponding to the situation in FIG. 1 in FIG. 2 and FIG. 3, and the description thereof is omitted as appropriate.

In the CMOS image sensor 51 shown in FIG. 2 , the data storage unit 27 is disposed at the rear stage of the row processing unit 23 , and the pixel signal outputted from the row processing unit 23 is supplied to the signal processing unit 26 via the data storage unit 27 .

In the CMOS image sensor 81 shown in FIG. 3 , the row processing unit 23 has an AD conversion function for performing AD conversion processing on each row of the pixel array unit 21 or on each plurality of rows, and a data storage unit 27 and a signal processing unit 26 are provided in parallel with the row processing unit 23.

In the following, it is assumed that the CMOS image sensor to which the present technology is applied has the structure shown in FIG. 1 and the description will continue.

<Unit pixel configuration example> The plurality of unit pixels constituting the pixel array section 21 are configured as shown in FIG. 4, for example. That is, FIG. 4 shows the circuit configuration of one unit pixel 101 constituting the pixel array section 21.

The unit pixel 101 includes a first photoelectric conversion unit 121, a second photoelectric conversion unit 122, a transfer transistor 123, an FD (floating diffusion unit) unit 124, a first switching transistor 125, a second switching transistor 126, a third switching transistor 127, a reset transistor 128, an amplifying transistor 129, and a selecting transistor 130.

In the unit pixel 101, the reset transistor 128 and the amplifier transistor 129 are connected to a predetermined power source VDD. In addition, hereinafter, the voltage of the power source VDD is also described as the power source voltage VDD.

The first photoelectric conversion unit 121 is composed of, for example, a so-called buried photodiode in which an N-type impurity region is formed inside a P-type impurity region formed in a silicon semiconductor substrate.

The first photoelectric conversion section 121 generates electric charge according to the amount of the incident light by performing photoelectric conversion on the light incident (received) from the outside, and accumulates the generated electric charge to a certain amount.

The second photoelectric conversion unit 122 is composed of, for example, a so-called buried photodiode in which an N-type impurity region is formed inside a P-type impurity region formed in a silicon semiconductor substrate.

The second photoelectric conversion section 122 generates electric charge according to the amount of incident light by photoelectrically converting light incident (received) from the outside.

When the semiconductor substrate provided with the pixel array section 21 is viewed from a direction perpendicular to the semiconductor substrate, the area of the first photoelectric conversion section 121 (light-receiving surface) is larger than the area of the second photoelectric conversion section 122. That is, the first photoelectric conversion section 121 is formed so that the area of the light-receiving surface and the overall volume are larger than those of the second photoelectric conversion section 122.

Therefore, when a subject is photographed at a predetermined illumination with the same exposure time, more charge is generated in the first photoelectric conversion section 121 than in the second photoelectric conversion section 122 .

For example, consider the case where the charge generated in the first photoelectric conversion section 121 and the charge generated in the second photoelectric conversion section 122 are respectively transferred to the FD section 124 and the charge-voltage conversion is performed. In this case, the voltage change before and after the charge generated by the first photoelectric conversion section 121 is transferred to the FD section 124 is larger than the voltage change before and after the charge generated by the second photoelectric conversion section 122 is transferred to the FD section 124. Therefore, the first photoelectric conversion section 121 can be said to have a higher sensitivity than the second photoelectric conversion section 122.

Thus, the first photoelectric conversion unit 121 that functions as a high-sensitivity pixel with higher sensitivity and the second photoelectric conversion unit 122 that functions as a low-sensitivity pixel with lower sensitivity are provided in the unit pixel 101. A high-sensitivity pixel can also be called a large pixel with a larger light-receiving surface, and a low-sensitivity pixel can also be called a small pixel with a smaller light-receiving surface.

Furthermore, in the unit pixel 101 , a transfer transistor 123 , a first switching transistor 125 , a second switching transistor 126 , and a third switching transistor 127 are connected in series between the first photoelectric conversion section 121 and the second photoelectric conversion section 122 .

The floating diffusion layer connected between the transfer transistor 123 and the first switch transistor 125 is the FD portion 124. The FD portion 124 is connected to the first photoelectric conversion portion 121 via the transfer transistor 123.

The FD portion 124 has a parasitic capacitance that becomes the first capacitor FD1. In other words, the FD portion 124 functions as the first capacitor FD1 that is a charge storage capacitor. For example, the first capacitor FD1 is formed of an N-type diffusion layer (floating diffusion layer).

The portion of the floating diffusion layer connected between the first switching transistor 125 and the second switching transistor 126 has a parasitic capacitance of the second capacitor FD2 which is a charge storage capacitor. For example, the second capacitor FD2 is formed by an N-type diffusion layer (floating diffusion layer). The second capacitor FD2 is connected to the first capacitor FD1 via the first switching transistor 125.

A third capacitor FD3 of a charge storage capacitor is provided between the second switching transistor 126 and the third switching transistor 127. For example, the third capacitor FD3 may be a wiring capacitor, or may be a MOS (Metal Oxide Semiconductor) capacitor or a MIM (Metal-Insulator-Metal) capacitor. The third capacitor FD3 is connected to the second capacitor FD2 via the second switching transistor 126.

A fourth capacitor FD4 as a charge storage capacitor is provided between the second photoelectric conversion unit 122 and the third switching transistor 127. In particular, the fourth capacitor FD4 is directly connected to the second photoelectric conversion unit 122, and is connected to the third capacitor FD3 via the third switching transistor 127.

Therefore, the charge generated by the second photoelectric conversion unit 122 is stored in the fourth capacitor FD4. The fourth capacitor FD4 may be a wiring capacitor, a MOS capacitor, or a MIM capacitor.

One end of the fourth capacitor FD4 is connected to a variable power source FCVDD different from the power source VDD. For example, the voltage of the power source FCVDD is set to be substantially the same as the voltage of the power source VDD, but the voltage is set to be lower than the voltage of the power source VDD during the accumulation of charges in the fourth capacitor FD4.

The structure of the unit pixel 101 can also be said to be a structure in which four charge storage capacitors, namely the first capacitor FD1 to the fourth capacitor FD4, are provided between the high-sensitivity pixel (the first photoelectric conversion unit 121) and the low-sensitivity pixel (the second photoelectric conversion unit 122), and switching transistors are provided between the charge storage capacitors for electrically coupling the adjacent charge storage capacitors. In particular, the switching transistors mentioned here are the first switching transistor 125 to the third switching transistor 127.

For the unit pixel 101, a plurality of signal lines are arranged for each pixel row as the pixel driving line 28 shown in FIG. 1 and the like.

A driving signal TGL, a driving signal FDG, a driving signal ODG, a driving signal FCG, a driving signal RST, and a driving signal SEL are supplied from the vertical driving section 22 to the unit pixel 101 via a plurality of signal lines serving as pixel driving lines 28 .

For example, assume that each transistor in the unit pixel 101 is an NMOS transistor. In this case, the driving signal supplied to the transistor in the unit pixel 101 is set to a high level (such as power voltage VDD) as a valid state, and a low level (such as negative potential) as an ineffective pulse signal.

The transfer transistor 123 is disposed between the first photoelectric conversion section 121 and the FD section 124 , and a driving signal TGL is supplied (applied) to a gate electrode of the transfer transistor 123 from the vertical driving section 22 .

When the driving signal TGL is in an active state, the transfer transistor 123 is in an on state (turned on state) and the charge accumulated in the first photoelectric conversion unit 121 is transferred to the FD unit 124 via the transfer transistor 123. That is, the transfer transistor 123 transfers the charge generated by the first photoelectric conversion unit 121 to the first capacitor FD1.

In addition, when the driving signal TGL is in an inactive state, that is, during the exposure period in which charges are stored in the first photoelectric conversion portion 121, an overflow path is formed by the transfer transistor 123.

Therefore, when the result of photoelectric conversion in the first photoelectric conversion section 121 is to generate a charge exceeding the saturated charge amount of the first photoelectric conversion section 121, the charge exceeding the saturated charge amount overflows to the FD section 124 through the overflow path, that is, the transfer transistor 123.

In other words, the charge exceeding the saturated charge amount overflows from the first photoelectric conversion section 121 to the FD section 124 through the overflow path, and the overflowed charge is accumulated in the FD section 124 .

The driving signal FDG is supplied (applied) to the gate electrode of the first switching transistor 125. When the driving signal FDG is in an active state, the first switching transistor 125 is in an on state (turned on state).

Thus, the floating diffusion layer between the first switching transistor 125 and the second switching transistor 126 and the FD portion 124 are electrically coupled to form a charge storage region. That is, the first capacitor FD1 and the second capacitor FD2 are electrically coupled to form a charge storage capacitor.

When the driving signal ODG is supplied (applied) to the gate electrode of the second switching transistor 126 and the driving signal ODG is in an effective state, the second switching transistor 126 is in an on state (open state).

For example, when the first switching transistor 125 and the second switching transistor 126 are in the on state, the potential of the portion from the FD portion 124 to the third capacitor FD3 is coupled to form a charge storage region. In other words, the first capacitor FD1, the second capacitor FD2, and the third capacitor FD3 are electrically coupled.

When the drive signal FCG is supplied (applied) to the gate electrode of the third switching transistor 127 and the drive signal FCG is in a valid state, the third switching transistor 127 is in a conducting state (open state).

For example, when the first switching transistor 125, the second switching transistor 126, and the third switching transistor 127 are in the on state, the potential of the portion from the FD portion 124 to the fourth capacitor FD4 is coupled to form a charge storage region. In other words, the first capacitor FD1, the second capacitor FD2, the third capacitor FD3, and the fourth capacitor FD4 are electrically coupled.

Not only the third capacitor FD3 but also the reset transistor 128 is connected between the second switching transistor 126 and the third switching transistor 127.

In more detail, one end of the reset transistor 128 is connected to the second switch transistor 126 and the third switch transistor 127, and the other end of the reset transistor 128 is connected to the power source VDD.

The driving signal RST is supplied (applied) to the gate electrode of the reset transistor 128. When the driving signal RST is in an effective state, the reset transistor 128 is in a conductive state (turned on state), and the potential of the portion from the second switching transistor 126 to the third switching transistor 127, that is, the potential of the third capacitor FD3, is reset to the level of the power supply voltage VDD.

In addition, when the reset transistor 128 is set to the on state to reset the potential, by appropriately setting the drive signal FDG or the drive signal ODG, the drive signal FCG is also set to the effective state, and not only the third capacitor FD3, but also the potential of the first capacitor FD1 or the second capacitor FD2, the fourth capacitor FD4 can be reset to the level of the power supply voltage VDD.

The floating diffusion layer, i.e., the FD portion 124, is a charge-voltage conversion portion that converts the stored charge into a voltage (voltage signal). When charge is transferred to the FD portion 124, the potential of the FD portion 124 changes according to the amount of the transferred charge.

The amplifier transistor 129 outputs a signal having a voltage corresponding to the potential of the FD portion 124.

A constant current source connected to one end of the vertical signal line 29 is connected to the source side of the amplifying transistor 129, a power source VDD is connected to the drain side of the amplifying transistor 129, and an FD section 124 is connected to the gate electrode of the amplifying transistor 129. The amplifying transistor 129, the constant current source, and the power source VDD constitute a source follower circuit, and the gate electrode of the amplifying transistor 129 is the input of the source-source follower circuit.

The selection transistor 130 is connected between the source of the amplifying transistor 129 and the vertical signal line 29. When the drive signal SEL is supplied (applied) to the gate electrode of the selection transistor 130 and the drive signal SEL is in an effective state, the selection transistor 130 is in a conducting state (open state), and the unit pixel 101 is in a selected state.

When the charge generated by the first photoelectric conversion section 121 or the second photoelectric conversion section 122 is transferred to the FD section 124, more specifically, the charge storage region (charge storage capacitor) including at least the first capacitor FD1, the potential of the FD section 124 changes according to the amount of the transferred charge. Furthermore, the changed potential of the FD section 124 is input to the source-source follower circuit, that is, the gate electrode of the amplifier transistor 129.

When the drive signal SEL is in a valid state, a voltage signal of a level corresponding to the potential of the FD portion 124, that is, the amount of charge held (stored) in the charge storage capacitor, is output from the amplifier transistor 129 through the selection transistor 130 and the vertical signal line 29 to the row processing portion 23 as the output of the source-source follower circuit.

<Example of Planar Configuration of Unit Pixel> When the CMOS image sensor 11 is set as a back-illuminated CMOS image sensor, the planar configuration of the unit pixel 101 is shown in FIG5, for example. In addition, the same symbol is given to the part corresponding to the situation in FIG4 in FIG5, and its description is omitted as appropriate.

In the example shown in FIG5 , the portion of the octagonal area surrounded by the area with diagonal lines is the light-receiving surface of the first photoelectric conversion section 121. In addition, the portion of the quadrangular (diamond) area adjacent to the upper right side of the first photoelectric conversion section 121 and surrounded by the area with diagonal lines is the light-receiving surface of the second photoelectric conversion section 122. In this example, it can be seen that the light-receiving surface of the first photoelectric conversion section 121 is larger than the light-receiving surface of the second photoelectric conversion section 122.

Furthermore, the transmission transistor 123, the first switching transistor 125, and the second switching transistor 126 are arranged in the longitudinal direction in the figure so as to overlap with the substantially central portion of the light receiving surface of the first photoelectric conversion unit 121.

On the left side of the transmission transistor 123 to the second switch transistor 126 in the figure, the reset transistor 128, the amplification transistor 129, and the selection transistor 130 are arranged in the vertical direction in the figure.

Furthermore, near the light receiving surface of the second photoelectric conversion unit 122, the third switching transistor 127 and the fourth capacitor FD4 are arranged in the vertical direction in the figure.

<About pixel signal reading> As described above, the unit pixel 101 is a pixel having a sub-pixel structure including a first photoelectric conversion unit 121 which is a high-sensitivity pixel and a second photoelectric conversion unit 122 which is a low-sensitivity pixel.

In addition, four first to fourth capacitors FD1 to FD4 are provided between the first photoelectric conversion unit 121 and the second photoelectric conversion unit 122 in the unit pixel 101 as charge storage capacitors for storing (maintaining) the charge generated by the first photoelectric conversion unit 121 or the second photoelectric conversion unit 122.

Furthermore, a switching transistor for coupling the adjacent charge storage capacitors (first capacitor FD1 to fourth capacitor FD4) in the unit pixel 101 is provided. That is, in the unit pixel 101, a first switching transistor 125, a second switching transistor 126, and a third switching transistor 127 are provided as switching transistors.

The second switching transistor 126 and the second capacitor FD2 are not provided in the pixel of the general sub-pixel structure. In view of this, the characteristic of the unit pixel 101 applying the present technology is that the second switching transistor 126 and the second capacitor FD2 are provided in order to obtain a higher quality image. The characteristics of the present technology are described below.

In the unit pixel 101 , the second switching transistor 126 is provided between the first switching transistor 125 , the third switching transistor 127 , and the reset transistor 128 .

Thus, when reading the signal corresponding to the charge generated by the first photoelectric conversion section 121 (hereinafter also referred to as the signal SP1), the charge-to-voltage conversion efficiency can be switched in three stages. Hereinafter, the charge-to-voltage conversion efficiency is also referred to as the conversion efficiency.

Specifically, for example, the signal SP1 is read out with three different conversion efficiencies, namely, HCG with the highest conversion efficiency, MCG with the second highest conversion efficiency, and LCG with the lowest conversion efficiency.

For example, in the unit pixel 101, exposure operation, that is, photoelectric conversion in the first photoelectric conversion section 121 and the second photoelectric conversion section 122, or reading of the reset level, etc. is appropriately performed. And then, the signal SP1 corresponding to the charge generated by the first photoelectric conversion section 121 and the signal corresponding to the charge generated by the second photoelectric conversion section 122 (hereinafter also referred to as the signal SP2) are read.

At this time, first, the conversion efficiency is switched in the order of conversion efficiency HCG, conversion efficiency MCG, and conversion efficiency LCG, and the signal SP1 is read out with each of these conversion efficiencies, and then the signal SP2 is read out.

At the conversion efficiency HCG, the drive signal FDG is set to an inactive state, and the signal SP1 is read when the first switching transistor 125 is in an off state (non-conducting state).

At this time, the driving signal ODG can be set to either a valid state or an inactive state. For example, when the driving signal ODG is set to a valid state, the second switching transistor 126 is set to a conductive state.

When the signal SP1 is read at the conversion efficiency HCG, the transfer transistor 123 is set to the on state (conductive state), and the charge generated by the first photoelectric conversion unit 121 is transferred to the FD unit 124, that is, the first capacitor FD1, and is maintained.

Furthermore, a signal SP1 corresponding to the charge held in the first capacitor FD1 is output from the amplifying transistor 129 to the row processing unit 23 via the selecting transistor 130 and the vertical signal line 29 .

Hereinafter, the pixel signal obtained by the row processing unit 23 by reading the signal SP1 at the conversion efficiency HCG is also specifically referred to as the signal SP1H. For example, the row processing unit 23 generates the signal SP1H by performing CDS processing.

After reading out the conversion efficiency HCG, read out the signal SP1 under the conversion efficiency MCG.

At the conversion efficiency MCG, the driving signal FDG is set to the effective state, and the first switching transistor 125 is set to the on state (conductive state). At this time, the driving signal ODG is set to the ineffective state, and the second switching transistor 126 is set to the off state (non-conductive state).

Thereby, the first capacitor FD1 and the second capacitor FD2 are coupled, and the charge generated by the first photoelectric conversion unit 121 is maintained in a charge storage capacitor (charge storage region) composed of the first capacitor FD1 and the second capacitor FD2.

In this way, the signal SP1 corresponding to the charge stored in the charge storage capacitor composed of the first capacitor FD1 and the second capacitor FD2 is output from the amplifying transistor 129 to the row processing unit 23 via the selecting transistor 130 and the vertical signal line 29.

Hereinafter, the pixel signal obtained by the row processing unit 23 by reading the signal SP1 at the conversion efficiency MCG is also specifically referred to as the signal SP1M. For example, the row processing unit 23 generates the signal SP1M by performing CDS processing.

After reading out the conversion efficiency MCG, read out the signal SP1 under the conversion efficiency LCG.

At the conversion efficiency LCG, the driving signal FDG is set to the effective state, the first switching transistor 125 is set to the on state (conduction state), and the driving signal ODG is also set to the effective state, the second switching transistor 126 is set to the on state (conduction state). At this time, the driving signal FCG is set to the ineffective state, and the third switching transistor 127 is set to the off state (non-conduction state).

Thereby, the first capacitor FD1, the second capacitor FD2, and the third capacitor FD3 are coupled, and the charge generated by the first photoelectric conversion unit 121 is maintained in a charge storage capacitor (charge storage area) composed of the first capacitor FD1 to the third capacitor FD3.

In this way, the signal SP1 corresponding to the charge stored in the charge storage capacitor composed of the first capacitor FD1 to the third capacitor FD3 is output from the amplifying transistor 129 to the row processing unit 23 via the selecting transistor 130 and the vertical signal line 29.

Hereinafter, the pixel signal obtained by the row processing unit 23 by reading the signal SP1 at the conversion efficiency LCG will be specifically referred to as the signal SP1L.

At the conversion efficiency LCG, not only the signal SP1 corresponding to the charge transferred from the first photoelectric conversion section 121 to the FD section 124 is read, but also the signal corresponding to the charge overflowing (leaking) from the first photoelectric conversion section 121 to the FD section 124 during the exposure operation is read. The row processing section 23 generates a signal SP1L by performing DDS processing based on the read signal.

After reading the signal SP1 at the conversion efficiency HCG, the conversion efficiency MCG, and the conversion efficiency LCG in this way, the signal SP2 is then read.

When the signal SP2 is read, for example, the first switching transistor 125, the second switching transistor 126, and the third switching transistor 127 are set to an on state (conductive state), and the first capacitor FD1, the second capacitor FD2, the third capacitor FD3, and the fourth capacitor FD4 are coupled.

Thereby, the charge generated by the second photoelectric conversion unit 122 is maintained in a charge storage capacitor (charge storage area) composed of the first capacitor FD1 to the fourth capacitor FD4.

When the charge storage capacitor composed of the first capacitor FD1 to the fourth capacitor FD4 holds a charge, a signal SP2 corresponding to the charge is output from the amplifying transistor 129 to the row processing unit 23 via the selecting transistor 130 and the vertical signal line 29. In the unit pixel 101, the reset level of the signal SP2 is also read at an appropriate timing.

The row processing unit 23 generates a pixel signal by performing DDS processing based on the read signal SP2. Hereinafter, the pixel signal based on the signal SP2 will also be appropriately referred to as the signal SP2.

When the signal SP1H, the signal SP1M, the signal SP1L, and the signal SP2 are obtained as described above, in the signal processing unit 26 or the signal processing unit of the later stage of the CMOS image sensor 11, an image (hereinafter also referred to as an HDR image) is generated based on the signals SP1H to SP2.

In other words, wide dynamic range image synthesis processing is performed to synthesize a total of four images, namely, an image composed of signal SP1H, an image composed of signal SP1M, an image composed of signal SP1L, and an image composed of signal SP2, to generate one HDR image.

In the CMOS image sensor 11, by using four images, a high-quality HDR image with a wide dynamic range and less blur can be obtained.

For example, when the second switching transistor 126 is not provided in the unit pixel 101, an HDR image is generated based on signals equivalent to the above-mentioned signal SP1H, signal SP1L, and signal SP2.

In this case, the SNR curve of the HDR image is shown, for example, by arrow Q11 in Fig. 6. In addition, in Fig. 6, the vertical axis represents SNR, and the horizontal axis represents illumination, that is, the amount of incident light.

In the example shown by arrow Q11 in FIG. 6 , the signal SP1H is used in the low illumination interval T11 , the signal SP1L is used in the medium illumination interval T12 , and the signal SP2 is used in the high illumination interval T13 , thereby generating an HDR image.

In this case, for example, at the illuminance (light intensity) of the boundary portion between the intervals T12 and T13 (hereinafter also referred to as the synthesis boundary), the HDR image is generated using the signal SP1L and the signal SP2, but the SNR is drastically and significantly reduced at the synthesis boundary. Therefore, the image is blurred under the light intensity (illuminance) falling on the synthesis boundary, and the quality of the HDR image is reduced.

In view of this, when the CMOS image sensor 11 is used to generate an HDR image, the SNR curve of the HDR image is shown by the arrow Q12 in FIG. 6 .

In this example, signal SP1H is used in interval T21 with the lowest illumination, signal SP1M is used in interval T22 with the second lowest illumination, signal SP1L is used in interval T23 with higher illumination than interval T22, and signal SP2 is used in interval T24 with the highest illumination, to generate an HDR image.

For example, the signal SP1M and the signal SP1L are used at the illumination of the boundary portion (synthesized boundary) between the interval T22 and the interval T23, and the signal SP1L and the signal SP2 are used at the illumination of the boundary portion (synthesized boundary) between the interval T23 and the interval T24, to generate an HDR image.

In the example shown by arrow Q12, it can be seen that a decrease in SNR occurs at the synthesis boundaries, but compared with the example shown by arrow Q11, the decrease in SNR at the synthesis boundaries is small.

In particular, here, by switching the conversion efficiency when reading the signal SP1 in three stages, the synthesis boundary between the interval T23 using the signal SP1L and the interval T24 using the signal SP2 can be moved toward the high illumination side compared to the situation of arrow Q11. This can further reduce the reduction of SNR at the synthesis boundary.

Therefore, according to the CMOS image sensor 11, the blurring of the image can be suppressed under the light quantity (illuminance) falling on the synthesis boundary, thereby improving the quality of the HDR image. That is, a higher quality HDR image can be obtained.

The quality improvement of such HDR images can be achieved by providing the second switching transistor 126, which can perform the conversion efficiency when reading the signal SP1 in three stages. In particular, after reading the signal SP1 with the conversion efficiency HCG and the conversion efficiency MCG, in addition to the charge of the signal SP1, the signal corresponding to the charge overflowing from the first photoelectric conversion unit 121 is also read with the conversion efficiency LCG, thereby suppressing the reduction of SNR at the synthesis boundary.

In general, in image sensors, it is known that the interface energy level under the transfer transistor arranged adjacent to the FD portion is degraded due to the strong electric field in the FD portion. To address this interface energy level degradation, it is effective to reduce the potential of the FD portion when charge is accumulated.

Here, the suppression of the FD electric field during charge accumulation in the unit pixel 101, that is, the suppression of the reduction in the voltage drop rate in the FD portion 124, is considered.

For example, when the second switching transistor 126 is not provided in the unit pixel 101, as indicated by arrow Q21 in FIG. 7, the voltage drop speed in the first capacitor FD1 (FD portion 124) is reduced.

7 shows the potential of the portion from the first photoelectric conversion section 121 to the reset transistor 128 in the unit pixel 101. That is, in FIG7, the vertical direction indicates the potential (electric potential) at each position.

In particular, FIG. 7 shows a case where the second switching transistor 126 is not provided in the unit pixel 101 , and therefore the capacity (the amount of charge that can be stored) of the second capacitor FD2 shown in FIG. 7 is larger than the capacity of the actual second capacitor FD2 in the unit pixel 101 .

When the second switching transistor 126 is not provided, in other words, when the second switching transistor 126 is not used, the voltage drop speed in the first capacitor FD1 is controlled by the first switching transistor 125.

As shown by arrow Q21, for example, when the Cut_Low of the first switching transistor 125 is deep or the first switching transistor 125 is turned on during exposure, the charge overflowing from the first photoelectric conversion unit 121 during exposure is accumulated in the first capacitor FD1 and the second capacitor FD2.

7, the hatched portion indicates the charge generated in the first photoelectric conversion section 121. Cut_Low is the potential (depth of potential) in the transistor portion when the transistor, that is, the first switching transistor 125 in this example, is turned off (non-conducting).

In this case, a voltage drop occurs in the portion of the first capacitor FD1 and the second capacitor FD2 due to the charge overflowing from the first photoelectric conversion unit 121 and accumulated in the first capacitor FD1 and the second capacitor FD2. That is, the potential in the portion of the first capacitor FD1 and the second capacitor FD2 becomes shallower with time.

However, since the second capacitor FD2 has a large capacity as described above, the voltage reduction speed is slowed down, and the time when the electric field intensity is strong in the first capacitor FD1 portion is prolonged. As a result, the influence of the dark current becomes greater, or white spots are generated in the image, and the quality of the HDR image is reduced.

Furthermore, it is also considered that, as indicated by arrow Q22, the first switching transistor 125 is set to an off state during exposure to electrically disconnect the first capacitor FD1 and the second capacitor FD2.

In this case, the potential of the first switching transistor 125 portion becomes shallow, and the charge overflowing from the first photoelectric conversion unit 121 is accumulated only in the first capacitor FD1. Therefore, if the first switching transistor 125 is turned off during exposure, it is expected that the voltage drop speed in the first capacitor FD1 portion will be reduced.

However, in reality, the first switching transistor 125 is affected by the nearby transfer transistor 123, and the electric field intensity of the first switching transistor 125 increases. That is, due to the electric field rate limitation of the first switching transistor 125, it is difficult to reduce the potential of the first switching transistor 125.

As described above, when the second switching transistor 126 is not provided, it is difficult to suppress the voltage reduction rate in the first capacitor FD1 by the first switching transistor 125. As a result, it is difficult to suppress the degradation of the quality of the HDR image.

To this end, in the CMOS image sensor 11, by providing a second switching transistor 126 in the unit pixel 101 and appropriately setting the Cut_Low of each transistor, the FD electric field can be suppressed to obtain a higher quality HDR image.

Specifically, in the unit pixel 101, Cut_Low becomes darker in the order of, for example, FDG>RST>FCG>ODG.

That is, the Cut_Low of the reset transistor 128 (RST) is shallower (higher potential) than the Cut_Low of the first switch transistor 125 (FDG).

Furthermore, the Cut_Low of the third switch transistor 127 (FCG) is shallower than the Cut_Low of the reset transistor 128 (RST), and the Cut_Low of the second switch transistor 126 (ODG) is shallower than the Cut_Low of the third switch transistor 127 (FCG). In addition, without limitation to this, the Cut_Low may be deepened in the order of FDG>RST>ODG>FCG, for example.

In the CMOS image sensor 11, as shown in FIG. 8, for example, by performing charge accumulation (exposure) in the OFF state (non-conducting state) of the second switching transistor 126, the FD electric field is suppressed, that is, the reduction in the voltage drop rate in the first capacitor FD1 is suppressed.

FIG8 shows the potential of the portion from the first photoelectric conversion section 121 to the reset transistor 128 in the unit pixel 101. That is, in FIG8, the vertical direction represents the potential at each position. In FIG8, the shaded portion represents the charge generated in the first photoelectric conversion section 121.

In this example, during charge accumulation, that is, during exposure, the first switching transistor 125 and the second switching transistor 126 are set to the off state.

As described above, the Cut_Low of the second switch transistor 126 (ODG) is shallower (higher potential) than the Cut_Low of the first switch transistor 125 (FDG). In other words, for example, the N-type channel concentration of the first switch transistor 125 connected between the first capacitor FD1 and the second capacitor FD2 is higher than the N-type channel concentration of the second switch transistor 126 connected between the second capacitor FD2 and the third capacitor FD3.

In this example, the second switching transistor 126 is disposed at a certain distance (more than a specified distance) away from the transmission transistor 123, and no electric field rate limitation occurs, so the Cut_Low of the second switching transistor 126 can be shallowed.

Therefore, when a large amount of charge overflows from the first photoelectric conversion unit 121, the overflowed charge is accumulated in the first capacitor FD1 and the second capacitor FD2, and the charge can be suppressed from overflowing to the third capacitor FD3.

Furthermore, the capacity of the second capacitor FD2 can be made smaller. That is, since the capacity of the second capacitor FD2 is smaller than the example shown in FIG. 7 , the voltage reduction speed in the portion of the first capacitor FD1 can be suppressed. In other words, the voltage reduction speed in the portion of the first capacitor FD1 can be made faster. This can suppress the generation of white spots, etc., and obtain a higher quality HDR image.

In this way, in the unit pixel 101, by providing the second switching transistor 126, the Cut_Low of the second switching transistor 126 is shallowed, thereby suppressing the reduction in the voltage drop speed.

In addition, the second switching transistor 126, which is set to the off state during exposure, is set to the on state, for example, before the signal SP1 under the conversion efficiency LCG is read (sampling), that is, before the signal level (D phase) under the conversion efficiency LCG is read.

Furthermore, in the unit pixel 101, the Cut_Low of the third switch transistor 127 (FCG) is shallower (higher potential) than the Cut_Low of the reset transistor 128 (RST). In other words, for example, the N-type channel concentration of the reset transistor 128 is higher than the N-type channel concentration of the third switch transistor 127 of the fourth capacitor FD4 connected to the low-sensitivity pixel capacitor.

Therefore, when the charge accumulated in the third capacitor FD3 increases, the charge exceeding the saturated charge overflows to the power source VDD via the reset transistor 128 having a deeper potential. Thus, the charge accumulated in the third capacitor FD3 can be suppressed from overflowing to the fourth capacitor FD4 via the third switching transistor 127. That is, the charge overflowing in the high-sensitivity pixel (first photoelectric conversion unit 121) can be prevented from overflowing to the fourth capacitor FD4 and mixing with the charge obtained in the low-sensitivity pixel (second photoelectric conversion unit 122).

As described above, the third capacitor FD3 can be, for example, a wiring capacitor, a MOS capacitor, or a MIM capacitor. Similarly, the fourth capacitor FD4 can also be, for example, a wiring capacitor, a MOS capacitor, or a MIM capacitor.

Furthermore, the third capacitor FD3 and the fourth capacitor FD4 may be set to have a large capacity. For example, the capacity (the amount of charge that can be stored) of the third capacitor FD3 and the fourth capacitor FD4 may be larger than the capacity of the first capacitor FD1 and the second capacitor FD2. That is, the third capacitor FD3 and the fourth capacitor FD4 may have a larger capacity than the first capacitor FD1 and the second capacitor FD2.

At this time, the size relationship between the capacitance of the third capacitor FD3 and the fourth capacitor FD4 can be any relationship, but for example, the capacitance of the fourth capacitor FD4 can be larger than the capacitance of the third capacitor FD3.

By making the capacitance of the third capacitor FD3 and the fourth capacitor FD4 larger than the capacitance of the first capacitor FD1 and the capacitance of the second capacitor FD2, overexposure in HDR images for automotive applications can be suppressed, or a longer exposure time can be ensured to suppress LED flicker.

If the fourth capacitor FD4 is set to a large capacitance, the second photoelectric conversion unit 122 functioning as a low-sensitivity pixel can receive more light than the first photoelectric conversion unit 121 functioning as a high-sensitivity pixel.

For example, the amount of charge that can be stored in the second photoelectric conversion unit 122 and the fourth capacitor FD4 (total amount) is greater than the amount of charge that can be stored in the first photoelectric conversion unit 121, the first capacitor FD1, and the second capacitor FD2. In the unit pixel 101, due to the difference in sensitivity between the low-sensitivity pixel and the high-sensitivity pixel, the saturated light amount of the signal SP2 of the low-sensitivity pixel is greater than the saturated light amount of the signal SP1 of the high-sensitivity pixel. For example, the capacitance of the fourth capacitor FD4 is greater (larger) than the total capacitance of the first capacitor FD1 and the second capacitor FD2.

<Second embodiment> <Unit pixel configuration example> In the example shown in FIG. 4 , a second switching transistor 126 is provided between the first switching transistor 125 and the third switching transistor 127.

However, the present invention is not limited thereto, and two or more N switching transistors may be disposed between the first switching transistor 125 and the third switching transistor 127, and the conversion efficiency may be switched in four or more stages.

In this case, the unit pixel 101 is configured as shown in Fig. 9, for example. In Fig. 9, the same symbols are given to the parts corresponding to those in Fig. 4, and their description is omitted as appropriate.

The structure of the unit pixel 101 shown in FIG. 9 is different from the structure shown in FIG. 4 in that N switching transistors 161 - 1 to 161 -N are provided instead of the second switching transistor 126, but is the same as the structure shown in FIG. 4 in other points.

In this example, the unit pixel 101 is a multi-stage LOFIC (Lateral Overflow Integration Capacitor) structure in which the switching transistors 161-1 to 161-N are connected in series between the first switching transistor 125 and the third switching transistor 127.

Hereinafter, when there is no need to specifically distinguish the switching transistors 161 - 1 to 161 -N, they are also referred to as the switching transistor 161 for short.

The first switching transistor 125 is connected to the switching transistor 161 - 1 , and a second capacitor FD2 is provided between the first switching transistor 125 and the switching transistor 161 - 1 .

Furthermore, a switch transistor 161-N is connected to the third switch transistor 127 and the reset transistor 128. A third capacitor FD3 is formed between the third switch transistor 127 and the reset transistor 128 and the switch transistor 161-N.

Furthermore, a charge storage capacitor is provided between each switching transistor 161.

Specifically, a second capacitor FD2'-k of a charge storage capacitor is provided between the switching transistors 161-k (where k=1, 2, ...N-1) and the switching transistor 161-(k+1) connected to each other.

The second capacitors FD2'-1 to FD2'-(N-1) are formed of, for example, an N-type diffusion layer (floating diffusion layer). Moreover, the capacitance of the second capacitors FD2'-1 to FD2'-(N-1) is smaller than, for example, the capacitance of the third capacitor FD3 and the fourth capacitor FD4.

Hereinafter, when there is no need to particularly distinguish between the second capacitor FD2’-1 to the second capacitor FD2’-(N-1), they are also referred to as the second capacitor FD2’.

In the unit pixel 101, by appropriately setting the switch transistor 161 to an open state (conductive state), the first capacitor FD1 and the second capacitor FD2 and any number of second capacitors FD2' can be coupled, thereby switching the conversion efficiency in (N+2) stages.

In this case, the more levels of conversion efficiency that can be switched, the greater the effect of suppressing the reduction in SNR and the reduction in the buck rate at the synthesis boundary, and higher quality HDR images can be obtained.

The structure of the unit pixel 101 shown in FIG9 can also be regarded as the structure in which a plurality of second switching transistors 126 are arranged between the second capacitor FD2 and the third capacitor FD3 in the unit pixel 101 shown in FIG4, and a charge storage capacitor (second capacitor FD2') is arranged between the second switching transistors 126 adjacent to each other.

<Third embodiment> <Unit pixel configuration example> When the CMOS image sensor 11 is used to capture an image, the pixel value (pixel signal) of one pixel on the image is sometimes obtained based on, for example, pixel signals obtained from a plurality of unit pixels adjacent to each other.

In this case, the second capacitors FD2 of adjacent pixels can be connected to each other through a switching transistor, and the second capacitors FD2 can be shared.

For example, when the second capacitor FD2 is shared between two adjacent unit pixels, a switching transistor is provided between the unit pixels as shown in Fig. 10. In Fig. 10, the same symbols are given to the parts corresponding to those in Fig. 4, and their description is omitted as appropriate.

In FIG. 10 , a unit pixel 101 and a unit pixel 201 are shown as two unit pixels provided in the pixel array section 21 and are arranged adjacent to each other.

In particular, the structure of the unit pixel 101 shown in FIG. 10 is the same as the structure shown in FIG. 4 , and the structure of the unit pixel 201 is also set to be the same as the structure of the unit pixel 101 .

That is, the first photoelectric conversion unit 221 to the selection transistor 230 are provided in the unit pixel 201 as a structure corresponding to the first photoelectric conversion unit 121 to the selection transistor 130 in the unit pixel 101.

In addition, the first capacitor FD1’ to the fourth capacitor FD4’ are provided in the unit pixel 201 as charge storage capacitors corresponding to the first capacitor FD1 to the fourth capacitor FD4 in the unit pixel 101.

Two switching transistors 251 and 252 are connected in series between the second capacitor FD2 of the unit pixel 101 and the second capacitor FD2' of the unit pixel 201. That is, the second capacitor FD2 of the unit pixel 101 is connected to the second capacitor FD2' of the adjacent unit pixel 201 via the switching transistor 251 and the switching transistor 252.

When the switching transistors 251 and 252 are set to an on state (non-conducting state), the second capacitor FD2 and the second capacitor FD2' are electrically coupled.

In this way, the second capacitor FD2 and the second capacitor FD2' can be connected by the switching transistor 251 and the switching transistor 252, thereby substantially making the capacity of the second capacitor FD2 variable, thereby making the capacity of the second capacitor FD2 larger.

In addition, the number of the switching transistors disposed between the second capacitor FD2 and the second capacitor FD2' may be one or more. In the example of FIG10 , two switching transistors are disposed between the second capacitor FD2 and the second capacitor FD2' from the viewpoint of configuration. That is, a switching transistor is disposed for each unit pixel, thereby making the configuration of the components in the unit pixel 101 and the unit pixel 201 symmetrical.

<Use example of image sensor> Figure 11 is a diagram showing a use example of the above-mentioned CMOS image sensor 11.

The CMOS image sensor 11 can be used in various situations such as sensing visible light, infrared light, ultraviolet light, X-rays, etc., as follows.

・Digital cameras or portable devices with camera functions that take images for viewing ・In-vehicle sensors that take images of the front or rear, surroundings, or interior of a car for safe driving such as automatic stop or driver identification, surveillance cameras that monitor moving vehicles or roads, and distance sensors that measure distances between vehicles, etc., for traffic purposes ・Device for home appliances such as TVs, refrigerators, and air conditioners that takes images of the user's gestures and operates the device in accordance with the gestures ・Device for medical or health care purposes such as devices that perform blood vessel photography using an endoscope or infrared light reception ・Security devices such as surveillance cameras for crime prevention or cameras for person identification ・Device for beauty use such as skin measuring devices for photographing skin or microscopes for photographing scalp ・Device for sports such as action cameras or wearable cameras for sports ・Device for agricultural use such as cameras for monitoring the status of fields or crops

<Application examples for mobile objects> Thus, the technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein can be implemented as a device mounted on any type of mobile object such as a car, an electric car, a hybrid vehicle, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, a robot, etc.

FIG12 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology disclosed herein can be applied.

The vehicle control system 12000 has a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG12 , the vehicle control system 12000 has a drive system control unit 12010, a body system control unit 12020, an external vehicle information detection unit 12030, an internal vehicle information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network I/F (interface) 12053 are shown.

The drive system control unit 12010 controls the operation of devices associated with the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor for generating a drive force for the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.

The vehicle system control unit 12020 controls the actions of various devices installed on the vehicle body according to various programs. For example, the vehicle system control unit 12020 functions as a control device for a keyless access control system, a smart key system, a power window device, or various lights such as headlights, taillights, brake lights, direction indicator lights, or fog lights. In this case, the vehicle system control unit 12020 can be input with radio waves or signals of various switches from a portable device that replaces the key. The vehicle system control unit 12020 receives the input of such radio waves or signals and controls the door lock device, power window device, lights, etc. of the vehicle.

The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to a camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to take images outside the vehicle and receive the taken images. The vehicle exterior information detection unit 12030 can perform object detection processing or distance detection processing of people, vehicles, obstacles, signs, or text on the road surface based on the received images.

The imaging unit 12031 is a photo sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

The in-vehicle information detection unit 12040 detects information in the vehicle. For example, a driver status detection unit 12041 for detecting the driver's status is connected to the in-vehicle information detection unit 12040. The driver status detection unit 12041 includes, for example, a camera for photographing the driver. The in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration based on the detection information input from the driver status detection unit 12041, and can also determine whether the driver is dozing off.

The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information inside and outside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for the purpose of realizing ADAS (Advanced Driver Assistance Systems) functions including collision avoidance or impact mitigation of the vehicle, following driving based on vehicle distance, speed maintenance driving, collision warning of the vehicle, or lane departure warning of the vehicle.

Furthermore, the microcomputer 12051 controls the driving force generating device, the steering mechanism or the braking device based on the information about the surroundings of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can perform coordinated control for the purpose of automatic driving that is independent of the driver's operation.

Furthermore, the microcomputer 12051 can output control instructions to the vehicle system control unit 12020 based on the information outside the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of the vehicle in front or the oncoming vehicle detected by the vehicle outside information detection unit 12030, and can perform coordinated control for the purpose of anti-glare, such as switching the high beam to the low beam.

The audio and video output unit 12052 sends an output signal of at least one of audio and video to an output device that can visually or auditorily notify information to the passengers of the vehicle or outside the vehicle. In the example of FIG. 12 , the output device includes an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of a vehicle-mounted display and a head-up display.

FIG. 13 is a diagram showing an example of the installation position of the imaging unit 12031. FIG.

In FIG. 13 , a vehicle 12100 includes imaging units 12101 , 12102 , 12103 , 12104 , and 12105 as an imaging unit 12031 .

Cameras 12101, 12102, 12103, 12104, 12105 are provided, for example, at the front bumper, rear mirror, rear bumper, tailgate, and upper portion of the windshield in the vehicle 12100. Camera 12101 provided at the front bumper and camera 12105 provided at the upper portion of the windshield in the vehicle mainly obtain images in front of the vehicle 12100. Cameras 12102 and 12103 provided at the rear mirror mainly obtain images at the side of the vehicle 12100. Camera 12104 provided at the rear bumper or tailgate mainly obtains images at the rear of the vehicle 12100. The images in front obtained by the camera units 12101 and 12105 are mainly used for detecting the vehicle or pedestrian in front, obstacles, signal machines, traffic signs or lane lines, etc.

In addition, an example of the photographing range of the camera units 12101 to 12104 is shown in FIG13 . The photographing range 12111 indicates the photographing range of the camera unit 12101 disposed on the front bumper, the photographing ranges 12112 and 12113 indicate the photographing ranges of the camera units 12102 and 12103 disposed on the rear mirror, respectively, and the photographing range 12114 indicates the photographing range of the camera unit 12104 disposed on the rear bumper or the tailgate. For example, by overlaying the image data captured by the camera units 12101 to 12104, a bird's-eye view image of the vehicle 12100 observed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer 12051 obtains the distance to each solid object within the imaging range 12111 to 12114 and the temporal change of the distance (relative speed of the vehicle 12100) based on the distance information obtained from the self-photographing units 12101 to 12104, and can capture the solid object closest to the vehicle 12100 on the path of the vehicle 12100 and traveling at a specific speed (e.g., 0 km/h or more) in the same direction as the vehicle 12100 as the front vehicle. Furthermore, the microcomputer 12051 can set the distance to be ensured in advance for the front vehicle, and perform automatic braking control (including stop-following control), automatic acceleration control (including follow-up start control), etc. In this way, coordinated control for the purpose of autonomous driving, etc., can be performed without relying on the driver's operation.

For example, the microcomputer 12051 can classify the 3D data related to the 3D object into motorcycles, ordinary vehicles, large vehicles, pedestrians, telephone poles and other 3D objects based on the distance information obtained from the cameras 12101 to 12104 and capture them for automatic obstacle avoidance. For example, the microcomputer 12051 can identify the obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Furthermore, the microcomputer 12051 determines the collision risk indicating the danger of collision with each obstacle. When the collision risk is above a set value and a collision is likely to occur, the microcomputer 12051 outputs an alarm to the driver via the audio speaker 12061 or the display unit 12062, or performs forced deceleration or evasive steering via the drive system control unit 12010, thereby providing driving support for avoiding collision.

At least one of the imaging units 12101 to 12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 may identify pedestrians by determining whether there are pedestrians in the images captured by the imaging units 12101 to 12104. The identification of pedestrians is performed by, for example, capturing feature points of the images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether the pedestrian is a step sequence. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio and video output unit 12052 controls the display unit 12062 to display a square outline for emphasis on the recognized pedestrian. In addition, the audio and video output unit 12052 can also control the display unit 12062 to display an icon showing the pedestrian at a desired position.

An example of a vehicle control system to which the technology disclosed herein can be applied has been described above. The technology disclosed herein can be applied to the imaging unit 12031 in the above-described configuration. Specifically, for example, the CMOS image sensor 11 shown in FIG. 1 can be used as the imaging unit 12031 to obtain a higher quality image.

In addition, this technology is not limited to application to solid-state imaging devices that detect the distribution of incident visible light and capture it as an image, but can be applied to all solid-state imaging devices (physical quantity distribution detection devices) such as solid-state imaging devices that capture the distribution of incident infrared rays, X-rays, or particles as an image, or fingerprint detection sensors that detect the distribution of other physical quantities such as pressure or electrostatic capacitance in a broad sense and capture it as an image.

The implementation form of this technology is not limited to the above-mentioned implementation form, and various changes can be made within the scope of the gist of this technology.

For example, a form in which all or part of the above-mentioned plural embodiments are combined may be adopted.

Furthermore, the effects described in this specification are merely illustrative and non-limiting effects, and effects other than those described in this specification may also be present.

Furthermore, this technology can also adopt the following structure.

(1) A solid-state imaging device comprises a pixel array section having a plurality of unit pixels; and the unit pixels have: a first pixel; a second pixel having a lower sensitivity than the first pixel; and four charge storage capacitors disposed between the first pixel and the second pixel; between the adjacent charge storage capacitors, a switching transistor for coupling the charge storage capacitors is disposed. (2) A solid-state imaging device as in (1), wherein the unit pixel serves as the four charge storage capacitors, and comprises: a first charge storage capacitor connected to the first pixel; a second charge storage capacitor connected to the first charge storage capacitor via a first switching transistor; a third charge storage capacitor connected to the second charge storage capacitor via a second switching transistor; a fourth charge storage capacitor connected to the second pixel and connected to the third charge storage capacitor via a third switching transistor. (3) A solid-state imaging device as in (2), wherein a transfer transistor for transferring the charge generated by the first pixel to the first charge storage capacitor is provided between the first pixel and the first charge storage capacitor. (4) A solid-state imaging device as in (2) or (3), wherein a gate electrode of an amplifier transistor is connected to the first charge storage capacitor, and the amplifier transistor outputs a signal of a voltage corresponding to the potential of the first charge storage capacitor. (5) A solid-state imaging device as in any one of (2) to (4), wherein the N-type channel concentration of the reset transistor connected to the third charge storage capacitor is higher than the N-type channel concentration of the third switch transistor. (6) A solid-state imaging device as in any one of (2) to (5), wherein the N-type channel concentration of the first switching transistor is higher than the N-type channel concentration of the second switching transistor. (7) A solid-state imaging device as in any one of (2) to (6), wherein the first charge storage capacitor and the second charge storage capacitor are formed by an N-type diffusion layer. (8) A solid-state imaging device as in any one of (2) to (7), wherein the second charge storage capacitor is connected to the second charge storage capacitor of the other unit pixels adjacent to the unit pixel via a switching transistor. (9) A solid-state imaging device as described in any one of (2) to (8), wherein the capacity of the third charge storage capacitor is larger than the capacity of the first charge storage capacitor and the second charge storage capacitor. (10) A solid-state imaging device as described in any one of (2) to (9), wherein the third charge storage capacitor is a MOS capacitor. (11) A solid-state imaging device as described in any one of (2) to (9), wherein the third charge storage capacitor is a wiring capacitor. (12) A solid-state imaging device as described in any one of (2) to (9), wherein the third charge storage capacitor is a MIM capacitor. (13) A solid-state imaging device as in any one of (2) to (12), wherein a plurality of the second switching transistors are disposed between the second charge storage capacitor and the third charge storage capacitor; and a charge storage capacitor is disposed between adjacent second switching transistors. (14) A solid-state imaging device as in any one of (2) to (13), wherein the capacity of the fourth charge storage capacitor is larger than the capacity of the first charge storage capacitor and the second charge storage capacitor. (15) A solid-state imaging device as in (14), wherein the amount of charge that can be stored in the second pixel and the fourth charge storage capacitor is greater than the amount of charge that can be stored in the first pixel, the first charge storage capacitor, and the second charge storage capacitor. (16) A solid-state imaging device as in any one of (2) to (15), wherein the fourth charge storage capacitor is a MOS capacitor. (17) A solid-state imaging device as in any one of (2) to (15), wherein the fourth charge storage capacitor is a wiring capacitor. (18) A solid-state imaging device as in any one of (2) to (15), wherein the fourth charge storage capacitor is a MIM capacitor.

11: CMOS image sensor 21: Pixel array section 22: Vertical drive section 23: Row processing section 24: Horizontal drive section 25: System control section 26: Signal processing section 27: Data storage section 28: Pixel drive line 29: Vertical signal line 51: MOS image sensor 81: CMOS image sensor 101, 201: Unit pixel 121, 221: First photoelectric conversion section 122: Second photoelectric conversion section 123: Transmission transistor 124: FD section 125: First switch transistor 126: Second switch transistor 127: Third switch transistor 128: Reset transistor 129: Amplification transistor 130: Select transistor 161-1~161-N: Switch transistor 230: Select transistor 251, 252: Switch transistor 12000: Vehicle control system 12001: Communication network 12010: Drive system control unit 12020: Body system control unit 12030: External information detection unit 12031, 12101, 12102, 12103, 12104, 12105: Camera unit 12040: Internal information detection unit 12041: Driver status detection unit 12050: Integrated control unit 12051: Microcomputer 12052: Audio and video output unit 12053: In-vehicle network I/F 12061: Audio speaker 12062: Display unit 12063: Instrument panel 12100: Vehicle 12111, 12112, 12113, 12114: Imaging range FCG, FDG, ODG, RST, SEL, TGL: Drive signal FCVDD: Power supply FD1, FD1’: 1st capacitor FD2, FD2’, FD2’-1~FD2’-(N-1): 2nd capacitor FD3, FD3’: 3rd capacitor FD4, FD4’: 4th capacitor Q11, Q12, Q21, Q22: Arrows SP1, SP1H, SP1L, SP1M, SP2: signal T11, T12, T13, T21, T22, T23, T24: interval VDD: power supply/power supply voltage

FIG. 1 is a diagram showing a configuration example of a CMOS image sensor. FIG. 2 is a diagram showing a configuration example of a CMOS image sensor. FIG. 3 is a diagram showing a configuration example of a CMOS image sensor. FIG. 4 is a diagram showing a configuration example of a unit pixel. FIG. 5 is a diagram showing a planar configuration example of a unit pixel. FIG. 6 is a diagram showing an SNR curve. FIG. 7 is a diagram for explaining the reduction of the voltage reduction rate. FIG. 8 is a diagram for explaining the suppression of the reduction of the voltage reduction rate. FIG. 9 is a diagram showing another configuration example of a pixel. FIG. 10 is a diagram showing another configuration example of a pixel. FIG. 11 is a diagram for explaining an example of the use of a CMOS image sensor. FIG. 12 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 13 is an explanatory diagram showing an example of the installation position of the vehicle external information detection unit and the camera unit.

29: Vertical signal line

101: Unit pixel

121: 1st photoelectric conversion unit

122: Second photoelectric conversion unit

123: Transmitting transistor

124: FD Department

125: 1st switch transistor

126: Second switch transistor

127: 3rd switch transistor

128: Reset transistor

129: Amplifier transistor

130: Select transistor

FCG, FDG, ODG, RST, SEL, TGL: drive signal

FCVDD: Power supply

FD1: 1st capacitor

FD2: Second capacitor

FD3: The third capacitor

FD4: 4th capacitor

SP1,SP2:Signal

VDD: power supply/power supply voltage

Claims (18)

A solid-state imaging device includes a pixel array section having a plurality of unit pixels; and the unit pixels include: a first pixel; a second pixel having a lower sensitivity than the first pixel; and four charge storage capacitors disposed between the first pixel and the second pixel; and a switching transistor for coupling the charge storage capacitors disposed between the adjacent charge storage capacitors. A solid-state imaging device as claimed in claim 1, wherein the unit pixel serves as the four charge storage capacitors, and has: A first charge storage capacitor connected to the first pixel; A second charge storage capacitor connected to the first charge storage capacitor via a first switching transistor; A third charge storage capacitor connected to the second charge storage capacitor via a second switching transistor; and A fourth charge storage capacitor connected to the second pixel and connected to the third charge storage capacitor via a third switching transistor. A solid-state imaging device as claimed in claim 2, wherein a transfer transistor for transferring charge generated by the first pixel to the first charge storage capacitor is provided between the first pixel and the first charge storage capacitor. In the solid-state imaging device of claim 2, a gate electrode of an amplifier transistor is connected to the first charge storage capacitor, and the amplifier transistor outputs a signal having a voltage corresponding to the potential of the first charge storage capacitor. A solid-state imaging device as claimed in claim 2, wherein the N-type channel concentration of the reset transistor connected to the third charge storage capacitor is higher than the N-type channel concentration of the third switch transistor. A solid-state imaging device as claimed in claim 2, wherein the N-type channel concentration of the first switching transistor is higher than the N-type channel concentration of the second switching transistor. A solid-state imaging device as claimed in claim 2, wherein the first charge storage capacitor and the second charge storage capacitor are formed by an N-type diffusion layer. A solid-state imaging device as claimed in claim 2, wherein the second charge storage capacitor is connected to the second charge storage capacitor of other unit pixels adjacent to the unit pixel via a switching transistor. A solid-state imaging device as claimed in claim 2, wherein the capacity of the third charge storage capacitor is larger than the capacity of the first charge storage capacitor and the second charge storage capacitor. A solid-state imaging device as claimed in claim 2, wherein the third charge storage capacitor is a MOS capacitor. A solid-state imaging device as claimed in claim 2, wherein the third charge storage capacitor is a wiring capacitor. A solid-state imaging device as claimed in claim 2, wherein the third charge storage capacitor is a MIM capacitor. A solid-state imaging device as claimed in claim 2, wherein a plurality of the second switching transistors are disposed between the second charge storage capacitor and the third charge storage capacitor; and charge storage capacitors are disposed between adjacent second switching transistors. A solid-state imaging device as claimed in claim 2, wherein the capacity of the fourth charge storage capacitor is larger than the capacity of the first charge storage capacitor and the second charge storage capacitor. A solid-state imaging device as claimed in claim 14, wherein the amount of charge that can be stored in the aforementioned second pixel and the aforementioned fourth charge storage capacitor is greater than the amount of charge that can be stored in the aforementioned first pixel, the aforementioned first charge storage capacitor, and the aforementioned second charge storage capacitor. A solid-state imaging device as claimed in claim 2, wherein the fourth charge storage capacitor is a MOS capacitor. A solid-state imaging device as claimed in claim 2, wherein the fourth charge storage capacitor is a wiring capacitor. A solid-state imaging device as claimed in claim 2, wherein the fourth charge storage capacitor is a MIM capacitor.