WO2011113414A2 - Method for sintering a semiconductor device using a low-temperature joining technique - Google Patents

Method for sintering a semiconductor device using a low-temperature joining technique Download PDF

Info

Publication number
WO2011113414A2
WO2011113414A2 PCT/DE2011/000231 DE2011000231W WO2011113414A2 WO 2011113414 A2 WO2011113414 A2 WO 2011113414A2 DE 2011000231 W DE2011000231 W DE 2011000231W WO 2011113414 A2 WO2011113414 A2 WO 2011113414A2
Authority
WO
WIPO (PCT)
Prior art keywords
sintering
ntv
layer
plasma deposition
nanopowder
Prior art date
Application number
PCT/DE2011/000231
Other languages
German (de)
French (fr)
Other versions
WO2011113414A3 (en
WO2011113414A4 (en
Inventor
Mathias Kock
Original Assignee
Danfoss Silicon Power Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Danfoss Silicon Power Gmbh filed Critical Danfoss Silicon Power Gmbh
Publication of WO2011113414A2 publication Critical patent/WO2011113414A2/en
Publication of WO2011113414A3 publication Critical patent/WO2011113414A3/en
Publication of WO2011113414A4 publication Critical patent/WO2011113414A4/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates to a method for NTV sintering of a semiconductor device according to the preamble of the main claim.
  • a modern method of bonding semiconductors to substrates is low temperature pressure sintering (NTV low temperature bonding) with silver.
  • NTV low temperature bonding low temperature pressure sintering
  • the semiconductor is pressed onto the substrate with a compound layer of silver using temperature (180 ° C to 350 ° C) and pressure (3-30 MPa).
  • Such an advantageous compound has a particularly high thermal and current carrying capacity if the porosity of the sintered compound is particularly low (for example less than 15%).
  • the sintering pressure is set correspondingly high.
  • the initial silver layer before pressing is usually a dried suspension of particulate silver. If the silver particles are nanoscale (ie they are l-100nm in diameter), a lower pressure is required (3-10 MPa). For macroscale suspensions (1 ⁇ - 20 ⁇ ) a pressure of 10- 30 MPa is required. The best results are obtained when the pressure is transferred to the semiconductor device and the surrounding substrate by a press with heatable lower punch and an upper punch with a flexible or deformable pressure plate.
  • the semiconductors to be sintered are also pressed into the silver suspension with hard (eg ceramic stamp surfaces) and the sintering is initiated. Subsequently, the sintered semiconductors are electrically contacted, for example, by ultrasonic wire bonding or tape bonding.
  • the relatively high relative pressure also generates local stress peaks with a yielding upper punch layer which lead to shear and tensile stresses, in particular in the semiconductor and its structures.
  • the particularly exposed elevations on the semiconductor as points of maximum force transmission are at risk.
  • These geometrically towering structures on the predominantly planar semiconductors are the isolation edges around contact surfaces.
  • an IGBT transistor is provided on its upper side with isolation structures around the gate contact for isolation between gate and emitter.
  • diodes are isolated in the same way between the contact surfaces of the anode and cathode by a raised against the remaining semiconductor surfaces insulating wall.
  • Such insulation walls consist for example of brittle layers, such as S13N4, Si0 2 or glasses. Typical for these isolation walls are heights of 2 - ⁇ ⁇ . Furthermore, insulating walls of polymers (especially polyimides) are also common. These have a low brittleness, but are characterized by the sintering pressure. drlindbar. Cracks, destructions and / or delaminations occur in the area of the insulation walls due to the pressure of the sintering punch, even in cases where you do not come into direct contact with the sintering punch. Such damage is also occasionally observed after the wire (ribbon) bonding cutoff when the cut wire or ribbon end is pulled over the edges of the insulation walls.
  • the contact surface or contact surfaces of the semiconductor are first provided with an electrically conductive additional layer which has at least the thickness of the highest insulation walls, but preferably is significantly higher to ensure relief of the insulation walls.
  • an electrically conductive additional layer which has at least the thickness of the highest insulation walls, but preferably is significantly higher to ensure relief of the insulation walls.
  • a particularly advantageous effect has been found in about three to five times the layer thickness compared to the height of the insulation walls.
  • the layer should also be bondable so that the typical contacts obtained by ultrasonic bonding of contact wires and tapes to conduct electricity can be.
  • preferably good conductive materials such as Al, Cu or Ag or their alloys are used.
  • the additional metal layer according to the invention additionally acts advantageously as a pressure transmitter to avoid mechanical stress peaks over the semiconductor surface and thus solves a further problem.
  • a further preferred improvement results from the use of thermally highly conductive layer materials by the thermal spreading and buffering effect of the thick metal layer.
  • the application of the layer is preferably to produce in the wafer composite and can be done selectively by masked chemical, electroplating or physical deposition technique.
  • the selective spraying of metal powders (nanoscale) by a low-temperature plasma has proven to be particularly economical.
  • layer thicknesses up to several ⁇ be produced.
  • This method can also be used for already sawn wafers on film and for already sintered chips on substrates. Further advantages and features will become apparent from the following description of a preferred embodiment. Showing:
  • Fig. 1 shows a cross section of a power semiconductor (the example of an IGBT) sintered on a ceramic substrate with the protective layers according to the invention against destructive consequences of the sintering pressure.
  • the inventive method for NTV sintering of a semiconductor device 5 for the power electronics under which a sintered layer 6 is provided, which provides the heat dissipation and which is provided with the metallic contact areas, insulating, over the flat contact areas protruding edges or insulating walls 3, draws by the following steps: 1.) over the above insulating walls 3, the contact areas are filled by the application of at least one further, planar, electrically and thermally conductive, preferably metallic layer 4, 2.) Sinterstkov then act on these applied (n ) further layer 4 during sintering and 3) bonding wires 1a, 1b are bonded to this applied further electrically and thermally conductive layer (s), preferably metallic layer (s).
  • bonding wires 1a, 1b are, after sintering for contacting e.g. made of an IBGT transistor with gate or emitter contact.
  • At least one of the further layers is formed by vacuum plasma deposition.
  • one of the further layers consists of copper and / or one of the further layers is made thick as a second heat sink with a total thickness of the layers of 30 ⁇ m.
  • the metallic contact areas consist of an aluminum compound and / or the copper layer (s) of nanoparticles are sprayed on (N anopowder plasma deposition).
  • the nanopowder plasma deposition is carried out without preparatory etching and etching steps on the semiconductor components before they are separated by sawing a wafer.
  • temperatures of 60 to 140 ° C for nanopowder plasma deposition suggest, the temperatures of 130 ° C to 140 ° C are reserved for thinner layers and thicker preferably at temperatures between 95 ° and 115 ° C. become. Nanopowder plasma deposition will already be successful at atmospheric pressure.
  • nanopowder plasma deposition is preferred in which pure powdered copper with grain diameters of 0.05 to 0.5 ⁇ m is sprayed without further admixtures.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Powder Metallurgy (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)

Abstract

The invention relates to a method for sintering a semiconductor component (5), which is suitable for power electronics and provided with contact areas, using a low-temperature joining technique. A sintering layer (6) that dissipates heat is arranged under the semiconductor component. The semiconductor component is provided with a further electrically and thermally conductive flat layer (4), to which bonding wires or bonding strips (1a, 1b) are bonded. In the method, the at least one further layer (4) is applied to the contact areas beyond insulating projecting edges (3), and sintering dies act on the applied at least one further layer (4) during sintering.

Description

Verfahren zum NTV-Sintern eines Halbleiterbausteins  Method for NTV sintering of a semiconductor device
Die Erfindung betrifft ein Verfahren zum NTV-Sintern eines Halbleiterbausteins nach dem Oberbegriff des Hauptanspruches. The invention relates to a method for NTV sintering of a semiconductor device according to the preamble of the main claim.
Ein modernes Verbindungsverfahren von Halbleitern auf Substraten (Keramik- Metall-Substraten oder Metallsubstraten oder Keramiksubstraten) ist das Niedertemperatur-Drucksintern (NTV-NiederTemperaturVerbinden) mit Silber. Hierbei wird der Halbleiter mit einer Verbindungsschicht aus Silber unter Anwendung von Temperatur (180°C bis 350°C) und Druck (3-30 MPa) auf das Substrat gepresst. A modern method of bonding semiconductors to substrates (ceramic metal substrates or metal substrates or ceramic substrates) is low temperature pressure sintering (NTV low temperature bonding) with silver. Here, the semiconductor is pressed onto the substrate with a compound layer of silver using temperature (180 ° C to 350 ° C) and pressure (3-30 MPa).
Dabei erfolgt eine Verdichtung des porösen Silbers und eine temperaturgetriebene Diffusion des Silber in die Kontaktflächen der Chipmetallisierung und der Metallschicht des Substrates und umgekehrt. Die Höhe des Sinterdruckes bestimmt den Grad der Restporosität der verbindenden Silberschicht. In this case, a compression of the porous silver and a temperature-driven diffusion of silver into the contact surfaces of the chip metallization and the metal layer of the substrate and vice versa. The height of the sintering pressure determines the degree of residual porosity of the connecting silver layer.
Eine derartige vorteilhafte Verbindung weist eine besonders hohe Wärme- und Stromtragfähigkeit auf, wenn die Porosität der Sinterverbindung besonders gering (z.B. geringer als 15%) ist. Dazu ist der Sinterdruck entsprechend hoch einzustellen. Such an advantageous compound has a particularly high thermal and current carrying capacity if the porosity of the sintered compound is particularly low (for example less than 15%). For this purpose, the sintering pressure is set correspondingly high.
Die initiale Silberschicht vor dem Verpressen ist meist eine getrocknete Suspension partikulären Silbers. Sind die Silberpartikel nanoskalig (d.h. haben sie l-100nm Durchmesser), so ist ein geringerer Druck erforderlich (3-10 MPa). Für makroskalige Suspensionen (1μ - 20μιη) ist ein Druck von 10- 30 MPa erforderlich. Die besten Ergebnisse werden erzielt wenn der Druck durch eine Presse mit heizbarem Unterstempel und einem Oberstempel mit flexibler oder verformbarer Anpressplatte auf das Halbleiterbauelement und das umgebende Substrat übertragen wird. Teilweise werden die zu sinternden Halbleiter auch mit harten (z.B. keramischen Stempelflächen) in die Silbersuspension gedrückt und die Sinterung eingeleitet. Anschließend werden die gesinterten Halbleiter z.B. durch Ultraschall-Drahtbonden o- der Bändchenbonden elektrisch kontaktiert. Dabei ergeben sich folgende Nachteile : Der relativ relative hohe Druck erzeugt auch mit einer nachgiebigen Oberstempelschicht lokale Spannungsspitzen, die zu Scher- und Zugspannungen insbesondere im Halbleiter und seinen Strukturen führen. Dabei sind die besonders exponierten Erhöhungen auf dem Halbeiter als Punkte höchster Krafteinleitung gefährdet. The initial silver layer before pressing is usually a dried suspension of particulate silver. If the silver particles are nanoscale (ie they are l-100nm in diameter), a lower pressure is required (3-10 MPa). For macroscale suspensions (1μ - 20μιη) a pressure of 10- 30 MPa is required. The best results are obtained when the pressure is transferred to the semiconductor device and the surrounding substrate by a press with heatable lower punch and an upper punch with a flexible or deformable pressure plate. In some cases, the semiconductors to be sintered are also pressed into the silver suspension with hard (eg ceramic stamp surfaces) and the sintering is initiated. Subsequently, the sintered semiconductors are electrically contacted, for example, by ultrasonic wire bonding or tape bonding. This results in the following disadvantages: The relatively high relative pressure also generates local stress peaks with a yielding upper punch layer which lead to shear and tensile stresses, in particular in the semiconductor and its structures. The particularly exposed elevations on the semiconductor as points of maximum force transmission are at risk.
Diese geometrisch aufragenden Strukturen auf den überwiegend ebenen Halbleitern sind die Isolationsränder rund um Kontaktierungsflächen. Zum Beispiel ist ein IGBT-Transistor auf seiner Oberseite mit Isolationsstrukturen rund um den Gatekontakt zur Isolation zwischen Gate und Emitter versehen. These geometrically towering structures on the predominantly planar semiconductors are the isolation edges around contact surfaces. For example, an IGBT transistor is provided on its upper side with isolation structures around the gate contact for isolation between gate and emitter.
Des Weiteren besteht eine erhöhte Isolationskante rund um den Emitterkontakt zur Erhöhung der Isolation zwischen Emitter und Kollektor entlang der Sägekante. Dies findet sich analog auch bei MOSFET-Halbleitern, die eine gleichartige Isolation zwischen Gate- und Source- Kontakten und zwischen Source- und umseitiger Drainflä- che besitzen. Furthermore, there is an increased insulation edge around the emitter contact for increasing the insulation between emitter and collector along the saw edge. This also applies analogously to MOSFET semiconductors which have a similar insulation between gate and source contacts and between source and reverse drain surfaces.
Weiter werden Dioden auf gleiche Weise zwischen den Kontaktflächen von Anode und Kathode durch einen gegenüber der restlichen Halbleiterflächen erhabenen Isolationswall isoliert. Further, diodes are isolated in the same way between the contact surfaces of the anode and cathode by a raised against the remaining semiconductor surfaces insulating wall.
Derartige Isolationswälle bestehen zum Beispiel aus spröden Schichten, wie z.B. S13N4, Si02 oder Gläsern. Typisch sind für diese Isolationswälle dabei Höhen von 2 - ΙΟ μπι. Weiter sind auch Isolationswälle aus Polymeren (speziell Polyimiden) gebräuchlich. Diese weisen eine geringe Sprödigkeit auf, sind aber durch den Sinterdruck ver- drängbar. Es entstehen Anrisse, Zerstörungen und/oder Delaminationen im Bereich der Isolationswälle durch den Druck des Sinterstempels auch in den Fällen, in denen Sie gar nicht direkt in Kontakt mit dem Sinterstempel kommen. Derartige Beschädigungen werden auch gelegentlich nach dem Abschneidevorgang beim Draht- (Bändchen-) -Bonden beobachtet, wenn das geschnittene Draht- bzw. Bändchenende über die Kanten der Isolationswälle gezogen wird. Such insulation walls consist for example of brittle layers, such as S13N4, Si0 2 or glasses. Typical for these isolation walls are heights of 2 - ΙΟ μπι. Furthermore, insulating walls of polymers (especially polyimides) are also common. These have a low brittleness, but are characterized by the sintering pressure. drängbar. Cracks, destructions and / or delaminations occur in the area of the insulation walls due to the pressure of the sintering punch, even in cases where you do not come into direct contact with the sintering punch. Such damage is also occasionally observed after the wire (ribbon) bonding cutoff when the cut wire or ribbon end is pulled over the edges of the insulation walls.
Eine Beeinträchtigung der Isolationswälle durch Beschädigungen beim Drucksintern und / oder Bonden führt zu Isolationstestausfällen oder erhöhten Leckstromwerten beim End-of-Line-Test der Halbleiter-Packages in der Fertigung. Impairment of the insulation walls due to damage during pressure sintering and / or bonding leads to insulation test failures or increased leakage current values during the end-of-line test of the semiconductor packages in production.
Aus der US 2009/0244868 AI ist ein Halbleiterelement mit den Merkmalen des Oberbegriffs des Anspruchs 1 bekannt. From US 2009/0244868 Al a semiconductor element having the features of the preamble of claim 1 is known.
Es ist Aufgabe der Erfindung, diese genannten Beschädigungen bei dem Sintern zu vermeiden. It is an object of the invention to avoid these mentioned damage during sintering.
Diese Aufgabe wird erfindungsgemäß durch ein Verfahren mit den Merkmalen des Anspruchs 1 überwunden. Die Unteransprüche geben bevorzugte Ausgestaltungen der Erfindung an. This object is achieved by a method having the features of claim 1. The subclaims specify preferred embodiments of the invention.
Bei dem vorgeschlagenen Verfahren werden die Kontaktfläche bzw. Kontaktflächen des Halbleiters (Kathode oder Anode bei Dioden und Emitter oder Source, sowie die Gate-Kontaktfläche bei IGBT und MOSFET) zunächst mit einer elektrisch leitfähigen Zusatzschicht versehen, die mindestens die Dicke der höchsten Isolationswälle besitzt, vorzugsweise aber deutlich höher ist, um eine Entlastung der Isolationswälle zu gewährleisten. Eine besonders vorteilhafte Wirkung hat sich bei ca. der drei bis fünffachen Schichtdicke im Vergleich zur Höhe der Isolationswälle gezeigt. Mit steigender Härte der flexiblen Schicht des Oberstempels der Sinterpresse ist die Höhe der Metallschicht zu steigern. Die Schicht sollte zudem bondbar sein, damit die typischen Kontaktierungen durch Ultraschallbonden von Kontaktdrähten und -bändern zur Stromführung erhalten werden kann. Hierzu kommen bevorzugt gut leitfähige Stoffe wie AI, Cu oder Ag oder deren Legierungen zum Einsatz. In the proposed method, the contact surface or contact surfaces of the semiconductor (cathode or anode in the case of diodes and emitter or source, and the gate contact area in IGBT and MOSFET) are first provided with an electrically conductive additional layer which has at least the thickness of the highest insulation walls, but preferably is significantly higher to ensure relief of the insulation walls. A particularly advantageous effect has been found in about three to five times the layer thickness compared to the height of the insulation walls. With increasing hardness of the flexible layer of the upper punch of the sintering press, the height of the metal layer is to be increased. The layer should also be bondable so that the typical contacts obtained by ultrasonic bonding of contact wires and tapes to conduct electricity can be. For this purpose, preferably good conductive materials such as Al, Cu or Ag or their alloys are used.
Die erfindungsgemäße zusätzliche Metallschicht wirkt durch ihre Dicke zusätzlich vorteilhaft als Druckmittler zur Vermeidung von mechanischen Spannungsspitzen über die Halbleiterfläche und löst damit ein weiteres Problem. Due to its thickness, the additional metal layer according to the invention additionally acts advantageously as a pressure transmitter to avoid mechanical stress peaks over the semiconductor surface and thus solves a further problem.
Eine weitere bevorzugte Verbesserung ergibt sich bei der Verwendung von thermisch gut leitenden Schichtmaterialien durch die thermische Spreiz- und Pufferwir- kung der dicken Metallschicht. A further preferred improvement results from the use of thermally highly conductive layer materials by the thermal spreading and buffering effect of the thick metal layer.
Die Aufbringung der Schicht ist vorzugsweise im Waferverbund herzustellen und kann durch maskierte chemische, galvanische oder physikalische Aufbringungstechnik selektiv geschehen. Als besonders wirtschaftlich hat sich das selektive Spritzen von Metallpulvern (nanoskalig) durch ein Niedertemperatur-Plasma erwiesen. Hierbei sind Schichtdicken bis zu mehreren ΙΟΟμπι herstellbar. Dieses Verfahren ist auch für bereits gesägte Wafer auf Folie und für bereits gesinterte Chips auf Substraten einsetzbar. Weiter Vorteile und Merkmale ergeben sich aus nachfolgender Beschreibung eines bevorzugten Ausführungsbeispiels. Dabei zeigt : The application of the layer is preferably to produce in the wafer composite and can be done selectively by masked chemical, electroplating or physical deposition technique. The selective spraying of metal powders (nanoscale) by a low-temperature plasma has proven to be particularly economical. Here, layer thicknesses up to several ΙΟΟμπι be produced. This method can also be used for already sawn wafers on film and for already sintered chips on substrates. Further advantages and features will become apparent from the following description of a preferred embodiment. Showing:
Fig. 1 einen Querschnitt eines Leistungshalbleiters (am Beispiel eines IGBT) gesintert auf ein Keramik-Substrat mit den erfindungsgemäßen Schutz- schichten gegen zerstörerische Folgen des Sinterdrucks. Fig. 1 shows a cross section of a power semiconductor (the example of an IGBT) sintered on a ceramic substrate with the protective layers according to the invention against destructive consequences of the sintering pressure.
Das erfindungsgemäße Verfahren zum NTV-Sintern eines Halbleiterbauelementes 5 für die Leistungselektronik unter dem eine Sinterschicht 6 vorgesehen ist, die für die Wärmeabfuhr sorgt und das mit um die metallischen Kontaktbereiche ausgebildeten, isolierenden, über die ebenen Kontaktbereiche vorstehenden Rändern oder Isolationswällen 3 versehen ist, zeichnet sich durch die folgenden Schritte aus : 1.) über die vorstehenden Isolationswälle 3 hinaus werden die Kontaktbereiche durch das Aufbringen wenigstens einer weiteren, ebenen, elektrisch und thermisch leitenden, vorzugsweise metallischen Schicht 4 angefüllt, 2.) Sinterstempel wirken dann auf diese aufgebrachte(n) weitere(n) Schicht 4 während des Sinterns und 3.) Bonddrähte la, lb werden auf diese aufgebrachte(n) weitere(n) elektrisch und thermisch leitende^), vorzugsweise metallischen Schicht(en) gebondet. The inventive method for NTV sintering of a semiconductor device 5 for the power electronics under which a sintered layer 6 is provided, which provides the heat dissipation and which is provided with the metallic contact areas, insulating, over the flat contact areas protruding edges or insulating walls 3, draws by the following steps: 1.) over the above insulating walls 3, the contact areas are filled by the application of at least one further, planar, electrically and thermally conductive, preferably metallic layer 4, 2.) Sinterstempel then act on these applied (n ) further layer 4 during sintering and 3) bonding wires 1a, 1b are bonded to this applied further electrically and thermally conductive layer (s), preferably metallic layer (s).
Diese Bonddrähte la, lb werden nach dem Sintern zur Kontaktierung z.B. eines IBGT-Transistors mit Gate bzw. Emitterkontakt gefertigt. These bonding wires 1a, 1b are, after sintering for contacting e.g. made of an IBGT transistor with gate or emitter contact.
In einer bevorzugten Variante wird beim vorgeschlagenen Verfahren zum NTV- Sintern wenigstens eine der weiteren Schichten durch Vakuum-Plasma- Abscheidung gebildet. In a preferred variant, in the proposed method for NTV sintering, at least one of the further layers is formed by vacuum plasma deposition.
Weiter wird vorgeschlagen, dass eine der weiteren Schichten aus Kupfer besteht und/oder eine der weiteren Schichten als zweite Wärmesenke mit einer Gesamtdicke der Schichten von 30 μπι dick ausgebildet wird. Bevorzugt ist weiter, dass die metallischen Kontaktbereiche aus einer Aluminiumverbindung bestehen und/oder die Kupferschicht(en) aus Nanopartikeln aufgesprüht werden (N anopo wder-Plasma-Deposition) . It is further proposed that one of the further layers consists of copper and / or one of the further layers is made thick as a second heat sink with a total thickness of the layers of 30 μm. It is further preferred that the metallic contact areas consist of an aluminum compound and / or the copper layer (s) of nanoparticles are sprayed on (N anopowder plasma deposition).
Dabei wird weiter bevorzugt, dass die Nanopowder-Plasma-Deposition ohne vorbe- reitende Ätz- und Beizschritte auf den Halbleiterbauelementen durchgeführt wird bevor diese durch Zersägen eines Wafers vereinzelt werden. In this case, it is further preferred that the nanopowder plasma deposition is carried out without preparatory etching and etching steps on the semiconductor components before they are separated by sawing a wafer.
Schließlich werden durch die Erfindung Temperaturen von 60 bis 140°C für die Nanopowder-Plasma-Deposition vorschlagen, wobei die Temperaturen von 130°C bis 140°C für dünnere Schichten vorbehalten sind und dickere bevorzugt bei Temperaturen zwischen 95° und 115° C gefertigt werden. Die Nanopowder-Plasma-Deposition wird dabei schon bei Atmosphärendruck erfolgreich sein können. Finally, by the invention, temperatures of 60 to 140 ° C for nanopowder plasma deposition suggest, the temperatures of 130 ° C to 140 ° C are reserved for thinner layers and thicker preferably at temperatures between 95 ° and 115 ° C. become. Nanopowder plasma deposition will already be successful at atmospheric pressure.
Es wird dabei eine Nanopowder-Plasma-Deposition bevorzugt, bei der reines pulvri- ges Kupfer mit Korndurchmessern von 0,05 bis 0,5 μπι ohne weitere Beimengungen versprüht wird. In this case, a nanopowder plasma deposition is preferred in which pure powdered copper with grain diameters of 0.05 to 0.5 μm is sprayed without further admixtures.

Claims

Patentansprüche 1. Verfahren zum NTV-Sintern eines für eine Leistungselektronik geeigneten, mit 1. A method for NTV sintering suitable for power electronics, with
Kontaktbereichen versehen Halbleiterbauelementes (5), unter dem eine für eine Wärmeabfuhr sorgende Sinterschicht (6) angeordnet ist und die mit einer weiteren elektrisch und thermisch leitenden ebene Schicht (4) versehen ist, auf die Bonddrähten oder -bändchen (la, lb) aufgebondet sind, dadurch gekennzeichnet, dass die wenigstens eine weitere Schicht (4) auf die Kontaktbereiche über isolierende vorstehende Ränder (3) hinaus aufgebracht wird, und während des Sinterns Sinterstempeln auf die aufgebrachte wenigstens eine weitere Schicht (4) einwirken. Contact regions provided semiconductor device (5), below which is arranged for a heat dissipation sintering layer (6) and which is provided with a further electrically and thermally conductive planar layer (4), are bonded to the bonding wires or -bändchen (la, lb) , characterized in that the at least one further layer (4) is applied to the contact areas beyond insulating projecting edges (3) and, during sintering sintering, acts on the applied at least one further layer (4).
2. Verfahren zur NTV-Sintern nach Anspruch 1, gekennzeichnet durch Bilden wenigstens einer der weiteren Schichten (4) durch Vakuum-Plasma- Abscheidung. 2. Method for NTV sintering according to claim 1, characterized by forming at least one of the further layers (4) by vacuum plasma deposition.
3. Verfahren zur NTV-Sintern nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass eine der wenigstens einen weiteren Schichten (4) aus Kupfer besteht. 3. A process for NTV sintering according to one of the preceding claims, characterized in that one of the at least one further layers (4) consists of copper.
4. Verfahren zur NTV-Sintern nach einem der vorangehenden Ansprüche, gekennzeichnet durch Ausbilden einer der wenigstens einen weiteren Schichten (4) als zweite Wärmesenke mit einer Gesamtdicke der Schichten von 30 μπι. 4. A method for NTV sintering according to one of the preceding claims, characterized by forming one of the at least one further layers (4) as a second heat sink with a total thickness of the layers of 30 μπι.
5. Verfahren zur NTV-Sintern nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass die metallischen Kontaktbereiche aus einer Aluminiumverbindung bestehen und die wenigstens eine Kupferschicht (4) durch Aufsprühen von Nanopartikeln, sog. Nanopowder-Plasma-Deposition, gebildet wird. 5. A method for NTV sintering according to one of the preceding claims, characterized in that the metallic contact areas consist of an aluminum compound and the at least one copper layer (4) by spraying of nanoparticles, so-called. Nanopowder plasma deposition is formed.
6. Verfahren zur NTV-Sintern nach Anspruch 5, gekennzeichnet durch Durchführen der Nanopowder-Plasma-Deposition ohne vorbereitende Ätz und Beizschritte auf den Halbleiterbauelemente vor dem Vereinzeln durch Zersägen eines Wafers. 6. A method for NTV sintering according to claim 5, characterized by performing the nanopowder plasma deposition without preparatory etching and etching steps on the semiconductor devices prior to dicing by sawing a wafer.
7. Verfahren zur NTV-Sintern nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass die Nanopowder-Plasma-Deposition bei Temperaturen unterhalb von 115° C erfolgt. 7. A process for NTV sintering according to one of the preceding claims, characterized in that the nanopowder plasma deposition takes place at temperatures below 115 ° C.
8. Verfahren zur NTV-Sintern nach einem der Ansprüche 5 - 7, dadurch gekennzeichnet, dass die Nanopowder-Plasma-Deposition bei Atmosphärendruck erfolgt. 8. A method for NTV sintering according to any one of claims 5-7, characterized in that the nanopowder plasma deposition takes place at atmospheric pressure.
9. Verfahren zur NTV-Sintern nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass die Nanopowder-Plasma-Deposition durch Versprühen reinen pulvrigen Kupfers mit Korndurchmessern von 0,05 bis 0,5 μπι ohne weitere Beimengungen er- folgt. 9. A method for NTV sintering according to one of the preceding claims, characterized in that the nanopowder plasma deposition by spraying pure powdery copper with grain diameters of 0.05 to 0.5 μπι without further admixtures follows.
PCT/DE2011/000231 2010-03-19 2011-03-02 Method for sintering a semiconductor device using a low-temperature joining technique WO2011113414A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102010012231.9 2010-03-19
DE102010012231A DE102010012231A1 (en) 2010-03-19 2010-03-19 Method for NTV sintering of a semiconductor device

Publications (3)

Publication Number Publication Date
WO2011113414A2 true WO2011113414A2 (en) 2011-09-22
WO2011113414A3 WO2011113414A3 (en) 2012-03-15
WO2011113414A4 WO2011113414A4 (en) 2012-05-03

Family

ID=44390904

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2011/000231 WO2011113414A2 (en) 2010-03-19 2011-03-02 Method for sintering a semiconductor device using a low-temperature joining technique

Country Status (2)

Country Link
DE (1) DE102010012231A1 (en)
WO (1) WO2011113414A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102394235A (en) * 2011-11-15 2012-03-28 株洲南车时代电气股份有限公司 Insulated gate bipolar transistor (IGBT) module and manufacturing method thereof
CN102881589B (en) * 2012-09-24 2015-05-13 株洲南车时代电气股份有限公司 Crimping IGBT (insulated gate bipolar transistor) module and method for manufacturing same
JP6436247B2 (en) 2015-12-14 2018-12-12 三菱電機株式会社 Semiconductor device and manufacturing method thereof
DE102020202845A1 (en) 2020-03-05 2021-09-09 Volkswagen Aktiengesellschaft Process for the production of an electrical module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090244868A1 (en) 2008-03-31 2009-10-01 Toshiaki Morita Semiconductor device and bonding material

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE58908749D1 (en) * 1988-03-03 1995-01-26 Siemens Ag Method for fixing electronic components on substrates and arrangement for carrying them out.
JP4930894B2 (en) * 2005-05-13 2012-05-16 サンケン電気株式会社 Semiconductor device
US7754533B2 (en) * 2008-08-28 2010-07-13 Infineon Technologies Ag Method of manufacturing a semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090244868A1 (en) 2008-03-31 2009-10-01 Toshiaki Morita Semiconductor device and bonding material

Also Published As

Publication number Publication date
WO2011113414A3 (en) 2012-03-15
DE102010012231A1 (en) 2011-09-22
WO2011113414A4 (en) 2012-05-03

Similar Documents

Publication Publication Date Title
DE102014213564B4 (en) Semiconductor device and method for manufacturing the same
DE102009000587B4 (en) A method of manufacturing a module having a sintered connection between a semiconductor chip and a copper surface
DE3036128C2 (en) Process for direct bonding of copper foils to oxide ceramic substrates
DE102010003533B4 (en) Substrate arrangement, method for producing a substrate arrangement, method for producing a power semiconductor module and method for producing a power semiconductor module arrangement
DE102012222791A1 (en) Method for contacting a semiconductor and semiconductor device with increased stability to thermomechanical influences
WO1994027319A1 (en) Power semiconductor device with stress buffer layer
DE112018001053T5 (en) SEMICONDUCTOR UNIT AND METHOD FOR PRODUCING A SEMICONDUCTOR UNIT
WO2013013964A1 (en) Carrier device, electrical device having a carrier device and method for producing same
DE102013102540B4 (en) Metal-ceramic substrate, module arrangement and method for producing a metal-ceramic substrate
DE112015006112T5 (en) SEMICONDUCTOR DEVICE
AT525618B1 (en) Process for coating and bonding substrates
WO2011113414A2 (en) Method for sintering a semiconductor device using a low-temperature joining technique
DE102013205138A1 (en) Semiconductor device, semiconductor module and method for producing a semiconductor device and a semiconductor module
DE102009001028B4 (en) Method for producing a bond connection
WO2007036208A1 (en) Method for connecting layers, corresponding component and organic light-emitting diode
DE102014119386B4 (en) Method for producing a metal-ceramic substrate and associated metal-ceramic substrate
DE102013113464A1 (en) Chip module, insulating material and method for producing a chip module
DE102015114521B4 (en) Method for soldering an insulating substrate onto a carrier
DE10335155B4 (en) Method for producing an arrangement of an electrical component on a substrate
WO2015024541A1 (en) Method for producing metal-ceramic substrates, and metal-ceramic substrate
WO2008064718A1 (en) Electronic component module and method for the production thereof
DE102010025311B4 (en) Method for applying a metallic layer to a ceramic substrate, use of the method and composite material
DE10342295B4 (en) Arrangement of an electrical component with an electrical insulation film on a substrate and method for producing the arrangement
DE102015100868B4 (en) Integrated circuit and method of making an integrated circuit
DE102012208251A1 (en) Electrical contacting for semiconductors

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11735589

Country of ref document: EP

Kind code of ref document: A2

122 Ep: pct application non-entry in european phase

Ref document number: 11735589

Country of ref document: EP

Kind code of ref document: A2