WO2008038346A1

WO2008038346A1 - Semiconductor device and its manufacturing method

Info

Publication number: WO2008038346A1
Application number: PCT/JP2006/319146
Authority: WO
Inventors: Atsushi Yamada
Original assignee: Fujitsu Limited
Priority date: 2006-09-27
Filing date: 2006-09-27
Publication date: 2008-04-03
Also published as: JP5018780B2; JPWO2008038346A1

Abstract

A semiconductor device comprises a silicon substrate (11), a gate electrode (16) located across a gate insulator (13) on the silicon substrate, and ladders (15) which are located between the gate insulator and the gate electrode, have an inherent stress different from that of the gate electrode, and are arrayed in a direction perpendicular to the direction of a current flowing through a channel region immediately beneath the gate electrode.

Description

Specification

Semiconductor device and manufacturing method thereof

Technical field

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a field effect transistor capable of independently controlling biaxial strain in a plane and applying an appropriate strain to a channel region. And a manufacturing method thereof.

Background art

[0002] In order to improve the performance of field effect transistors (FETs), devices using quantum effects have been studied. In particular, in compound semiconductors, quantum well structures can be fabricated relatively easily, and various studies have been conducted. In recent years, FETs using SiZSiGe heterojunctions in the quantum effect channel region have also been developed. However, these device structures are very different from the widely used Si-insulated gate FET (Si-MOSFET) structures, so it is difficult to apply them directly to conventional MOS processes.

[0003] On the other hand, in a silicon insulated gate field effect transistor (Si-MOSFET), a strain introducing technique for improving carrier mobility is used. In this case, for nMOSFETs, tensile strain is introduced in the channel region in the gate length direction, and for pMOSFETs, compressive strain is introduced in the gate length direction.

[0004] As an example, as shown in FIG. 1, by selectively depositing a silicon nitride film 111 having a high tensile stress and a silicon nitride film 112 having a high compressive stress on an nMOSFET and a pMOSFET, respectively, A method of applying a strain to a region is known (for example, see Non-Patent Documents 1 and 2).

[0005] In the method of FIG. 1, shallow 'trench' isolation (STI) 102, gate insulating film 103, polysilicon gate 105 and mono-silicide silicide (CoSi) 106, extension 104, sidewall spacer 107, source 'Drain impurity diffusion region 108 is formed by a general CMOS process. Thereafter, a Si nitride film 111 having a high tensile stress is deposited on the entire surface, and the high tensile stress Si nitride film 111 on the pMOSFET is selectively etched to leave the high tensile stress Si nitride film 111 only on the nMOSFET. Next, Si with high compressive stress as well A nitride film 112 is deposited on the entire surface, and the high compressive stress Si nitride film 112 on the nMOSFET is selectively etched, leaving the high compressive stress Si nitride film 112 only on the pMOSFET. As described above, the tensile stress film 111 is formed on the nMOSFET, and the compressive stress film 112 is formed on the pMOSFET.

[0006] The stress film 111 introduces tensile strain in the gate length direction and compressive strain in the height direction in the channel region of the nMOSFET. On the other hand, the stress film 112 introduces compressive strain in the gate length direction and tensile strain in the height direction in the pMOSFET. Specifically, for nM OSFETs, using a tensile stress film with an intrinsic stress of 1.6 GPa, a tensile strain of about 0.3% in the gate length direction and a compressive strain of about 0.3% in the height direction were obtained. It is done. For pMOS FET, a compressive stress film with an intrinsic stress of 2 GPa can be used to obtain a compressive strain of about 0.4% in the gate length direction and a tensile strain of about 0.5% in the height direction.

[0007] FIG. 2 shows another known method of obtaining the distortion effect. In the method shown in Fig. 2, silicon germanium (SiGe) or silicon carbon (SiC), which has a different lattice constant from Si, is selectively grown in the source and drain regions to cause distortion in the channel region (for example, Non-Patent Document 3 reference). In this document, a method for introducing strain is studied using a virtual MOSFET structure. In order to produce this structure, a gate pattern 205 is formed by lithography on a Si (100) substrate, and a recess structure is formed by dry etching in the source and drain regions using the gate pattern 205 as a mask. At this time, the etching side surface is tapered. Next, the natural oxide film in the recess region is removed with dilute hydrofluoric acid, and SiC is selectively grown for the nMOSFET. As a result, tensile strain in the gate length direction and compressive strain in the height direction are introduced into the channel region of the nMOSFET, respectively. For pMOSFET, SiGe is selectively grown in the recess. This introduces compressive strain in the gate length direction and tensile strain in the height direction into the channel region of the pMOSFET.

However, in these methods, the strain in the gate length direction and the height direction can be controlled, but the strain in the gate width direction cannot be controlled. In the future, in-plane biaxial strain control will be indispensable in order to further improve carrier mobility.

FIG. 3 shows a known method using biaxial strain (for example, see Non-Patent Document 4). This method uses a relaxed virtual substrate using SiGe. First, the SiGe buffer layer 302 is epitaxially grown on the Si substrate 301 by the CVD method. The SiGe buffer layer 302 relaxes the lattice strain of SiGe by changing the Ge ratio stepwise from 0 to 20% and increasing the film thickness to 1.5 / zm or more. Next, a 600 nm relaxed Si Ge layer 303 and a 75 nm p + Si Ge layer 304 are grown. Then 23η

0. 8 0. 2 0. 8 0. 2

A thin strained Si layer 305 of m is grown. The above epitaxial growth is performed at 700-750 ° C using dichlorosilane (SiH C1) and GeH. In addition, Epitaxial layer

2 2 4

Is in-situ doped with diborane (B H). Then normal CMOS process

2 6

To manufacture MOS device 310. Note that the strained Si layer 305 is thinned to about 12 nm due to thermal oxidation in the process. This completes the device with biaxial tensile strain introduced in the in-plane direction. As the strain amount at this time, a tensile strain of about 1% is obtained in the biaxial direction.

Non-Patent Document 1: S. Pidin et al., IEDM2004 Technical Digest, pp. 213— 2 16

Non-Patent Document 2: S. Pidin et al., 2004 Symposium on VLSI Technology Digest, pp. 54-55

Non-Patent Document 3: Kah— Wee Ang et al., Appl. Phys. Lett., 86, 093102 (20 05)

Non-Patent Document 4: K. Rim et al., IEEE Trans. Electron Devices, 47, 1406 (2000)

Disclosure of the invention

Problems to be solved by the invention

[0011] With the method shown in Fig. 3, effective strain can be introduced for the nMOSFET, but the mobility is limited for the pMOSFET. Therefore, in order to improve the carrier mobility in CMOSFET, it is necessary to control the biaxial strain independently.

[0012] Therefore, the present invention provides a semiconductor device capable of independently controlling the strain in the channel length direction and the channel width direction without greatly changing the basic structure of the Si-MOSFET and applying an appropriate strain to the channel region. And it makes it a subject to provide the manufacturing method. Means for solving the problem

In the present invention, in order to solve the above problem, by inserting a ladder having a stress different from that of the gate electrode and arranged in the channel width direction between the gate insulating film and the gate electrode, A strain in the channel width direction is independently generated in the channel region.

[0014] Specifically, in the first aspect, the semiconductor device includes:

(a) a silicon substrate;

(b) a gate electrode located on the silicon substrate via a gate insulating film;

(c) a ladder located between the gate insulating film and the gate electrode, arranged in a direction orthogonal to the direction of the current flowing in the channel region immediately below the gate electrode, and having a different stress from the gate electrode;

Is provided.

In a favorable configuration example, the ladder has a compressive stress, and the gate electrode has a compressive stress or a bow I tension stress that is smaller than the ladder's compressive stress.

In another configuration example, a tensile stress is inherent in the ladder, and a tensile stress or a compressive stress that is smaller than the tensile stress of the ladder is inherent in the gate electrode.

In yet another configuration example, the channel region forms an n-type channel, and the work function of the ladder is larger than the work function of the gate electrode.

In yet another configuration example, the channel region forms a p-type channel, and the work function of the ladder is smaller than the work function of the gate electrode.

In a second aspect, a method for manufacturing a semiconductor device is provided. This method

(a) forming a dummy electrode with a sidewall spacer covered with a sidewall spacer on a silicon substrate;

(b) removing the dummy electrode to form an opening between the sidewall spacers;

(c) forming a ladder extending in the first direction in the opening;

(d) forming a gate electrode covering the ladder with a material having a stress different from that of the ladder in the opening;

Process.

The invention's effect [0020] With the method described above, one-dimensional quantum confinement (quantum wire) can be realized by controlling strain in the channel width direction independently and performing band control in the channel region.

[0021] This improves the performance of the Si-MOSFET.

Brief Description of Drawings

FIG. 1 is a diagram showing an example of a known strain introduction structure.

FIG. 2 is a diagram showing another example of a known strain introduction structure.

FIG. 3 is a diagram showing another example of a known strain introduction structure.

FIG. 4 is a schematic view showing a gate structure of a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a schematic plan view showing a gate structure of the semiconductor device of the embodiment.

FIG. 6 is a schematic cross-sectional view in the channel width direction along the line AA ′ in FIG. 5, showing the stress applied in the channel width direction.

FIG. 7 is a schematic cross-sectional view in the channel length direction along the line BB ′ in FIG. 5, showing the stress applied to the nMOSFET.

FIG. 8 is a schematic cross-sectional view in the channel length direction along the line BB ′ of FIG. 5, showing the stress applied to the pMOSFET.

FIG. 9 shows a modification of the semiconductor device of the embodiment, in which a strain applying layer selectively grown in the source / drain region of the nMOSFET is used in place of the stress film covering the gate electrode or the stress film. FIG.

FIG. 10 shows a modification of the semiconductor device according to the embodiment, in which a strain application layer selectively grown in the source / drain regions of the pMOSFET is used instead of or together with the stress film covering the gate electrode. FIG.

FIG. 11A is a diagram for explaining the confinement effect in the channel region immediately below the ladder.

FIG. 11B is a diagram showing a band change due to the work function of the ladder (G1) and the metal gate (G2) in the nMOSFET in the configuration of FIG. 11A.

FIG. 11C is a diagram showing a band change due to the work function of the ladder (G1) and the metal gate (G2) in the pnMOSFET in the configuration of FIG. 11A.

FIG. 11D is a diagram showing a band change when the ladder is formed of an insulating film that applies compressive stress as a modification of FIG. 11A. [12] FIG. 12 is a view showing an example in which a ladder is made of a metal that applies compressive stress as a modification of FIG.

13A] A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention. FIG.

13B] A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.

FIG. 13C is a manufacturing process diagram of the semiconductor device according to one embodiment of the present invention.

13D] A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.

13E] A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.

13F] A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.

13G] A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.

13H] A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.

FIG. 131] A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.

13J] A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.

13K] A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.

Explanation of symbols

[0023] 10 Semiconductor device

11, 31 Semiconductor substrate

13, 53 Gate insulation film

14, 39 Source'Drain

15, 55 Ladder (G1)

16, 56 Gate electrode (G2)

17 Sidewall spacer

19, 59 Gate structure

20C, 20T, 60 Stress film (strain introduced layer)

21C, 21T strain application layer (strain introduction layer)

35 Dummy electrode

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a schematic diagram showing a gate structure of the semiconductor device 10 according to one embodiment of the present invention. is there. The semiconductor device ₁₀ is located on a semiconductor substrate 11 via a gate insulating film 13 and has a gate electrode 16 to which a gate voltage is applied, and a ladder 15 inserted between the gate insulating film 13 and the gate electrode 16. The ladder 15 is arranged in the channel width direction (y-axis direction in FIG. 4), and each stripe constituting the ladder extends in a direction parallel to the current flow (X-axis direction). The ladder structure 15 constituting the first part of the gate and the gate electrode 16 constituting the second part of the gate constitute a gate structure 19.

A source / drain impurity diffusion region (hereinafter simply referred to as “source / drain”) 14 is formed in the semiconductor substrate 11 with the gate electrode 16 interposed therebetween. A side wall spacer 17 is provided on the side wall of the gate electrode 16, and a stress film 20 is formed so as to cover the gate electrode 16 and the side wall spacer 17.

[0027] The stress film 20 mainly controls strain in the channel length direction (X-axis direction). On the other hand, the ladder 15 mainly serves to control strain in the channel width direction (y-axis direction). The stress film 20 and the ladder 15 can control the biaxial strain independently of each other.

FIG. 5 is a schematic plan view of the semiconductor device 10 of the embodiment. At least a part of the gate electrode 16 extends between the source region 14s and the drain region 14d. By applying gate voltage

A channel region (not shown in FIG. 5) is formed in the surface region of the semiconductor substrate between the source region 14s and the drain region 14d.

[0029] The ladder 15 is arranged in a direction (y-axis direction or channel width direction) orthogonal to the current flow. There is no limit to the number of stripes that make up ladder 15, but there must be at least one space between the stripes.

FIG. 6 is a schematic cross-sectional view along the line AA ′ in FIG. In the example of FIG. 6, the ladder (hereinafter referred to as “G1” as appropriate) 15 is made of a material that applies tensile stress (ie, inherently contains tensile stress), and is a gate electrode (hereinafter referred to as “G2” as appropriate). 16 is made of a material that gives compressive stress (ie, compressive stress is inherent).

For example, the ladder 15 is an electrode formed by vapor deposition of gold (Au), and a plurality of stripes are arranged in the y-axis (channel width) direction through a space 18 of lOOnm or less. The metal gate 16 is TiN formed by sputtering. [0032] The ladder region (Gl) 15 that applies tensile stress and the metal gate 16 that applies compressive stress can generate strain in the y-axis direction in the channel region. For example, when Au with an intrinsic stress of 0.5 GPa and TiN with an intrinsic stress of 2 GPa are used, a strain of about 0.5% can be applied.

[0033] For convenience of explanation, the region immediately below each ladder 15 in the channel region is referred to as a sub-channel region.

[0034] When the tensile stress of the ladder 15 is sufficiently large, the ladder 15 alone can apply sufficient strain in the channel width direction (y-axis direction). In this case, the stress applied to the metal gate 16 may be a tensile stress sufficiently smaller than that of the ladder 15, no stress, or a state of applying compressive stress!

[0035] On the contrary, when the compressive stress of the metal gate 16 is sufficiently large, the stress application state of the ladder 15 is no stress or gives a compressive stress sufficiently smaller than that of the metal gate 16. Even in the state of applying a tensile stress, it may be a deviation.

In the example of FIG. 6, the materials of the ladder 15 and the metal gate 16 are different. However, even if the same material is used, different stresses are applied by changing the film formation method and the film formation conditions, as will be described later. It can have characteristics.

FIG. 7 and FIG. 8 are schematic cross-sectional views along the line BB ′ of FIG.

It is a figure for demonstrating the structure which gives distortion to (X-axis direction). Fig. 7 shows the strain introduction of nMOSFET, and Fig. 8 shows the strain introduction of pMOSFET.

In FIG. 7, a silicon nitride film 20T, which is a stress film for applying a tensile stress, is selectively deposited on the n-type MOSFET. On the other hand, in FIG. 8, a silicon nitride film 20C, which is a stress film that applies compressive stress, is selectively deposited on the pMOSFET. These stress films function as a strain-introducing layer. In the nMOS channel region, tensile strain occurs in the X-axis direction and compressive strain in the z-axis direction. In pMOS channel regions, compressive strain in the X-axis direction, z-axis Causes tensile strain in the direction.

[0039] In these examples, due to the gate structure with the ladder 15 inserted, strain is also generated in the y-axis direction. In-plane strain in the two axes (X-axis and y-axis) and the height direction Strain is generated. [0040] Methods other than the stress film 20 may be used for applying strain in the channel length (x-axis) direction and height (z-axis) direction. For example, as shown in FIGS. 9 and 10, a strain applying layer may be provided in the source / drain region of the MOSFET instead of the stress film 20 or together with the stress film 20.

[0041] In the example of FIG. 9, a Si C strained layer 21T with a small lattice constant of SU is selectively grown in the source and drain regions of the nMOSFET, and the SiGe strain with a large lattice constant of SU is also used for the pMOSFET. The application layer 21C is selectively grown. The strain applying layers 21T and 21C function as strain introducing layers that cause strain in the channel length direction in the channel region.

In order to form the strain applying layer 21, the gate structure 19 covered with the sidewall spacer 17 is formed on the gate insulating film 13 on the Si (100) substrate 11. As described above, the gate structure 19 includes the ladder (G1) 15 and the gate electrode (metal gate: G2) 16 arranged in the channel width direction. Using this gate structure 19 as a mask, recesses are formed in the source / drain regions by dry etching, impurities are implanted, the surface is cleaned with dilute hydrofluoric acid or the like, and then a strain applying layer 21 is grown.

[0043] As shown in FIG. 9, for nMOSFET, disilane (SiH) monomethylsilane (SiHCH),

2 6 3 3 Using SiC (C1), the SiC layer 21T is selectively formed at 600 ° C by chemical vapor deposition (CVD).

2

Make it long. This forms Si C in the source / drain regions. Si C is S

0. 99 0. 01 0. 99 0. 01 Since it is 0.5% smaller than the lattice constant of i, tensile strain in the gate length direction and compressive strain in the height direction are introduced into the n-channel region. Is done.

[0044] As shown in Fig. 10, for pMOSFET, Si H, monogermane (GeH), C1 is used, and CV

2 6 4 2

Selectively grow SiGe layer 21C at 600 ° C by D method. This forms Si Ge in the source and drain regions. Si Ge is about 1% larger than the lattice constant of Si

0. 75 0. 25 0. 75 0. 25

Therefore, compressive strain in the gate length direction and tensile strain in the height direction are introduced into the p-channel region.

[0045] For nMOSFET, using a SiC layer 21T with an intrinsic stress of 1.6 GPa, a tensile strain of about 0.3% in the gate length direction and a compressive strain of about 0.2% in the height direction can be obtained. For pMOSF ET, using an intrinsic stress—2GPa SiGe layer 21C, a compressive strain of about 0.6% in the gate length direction and a tensile strain of about 0.4% in the height direction can be obtained. [0046] As described above, by using the gate structure with the ladder 15 introduced (Fig. 4) and the stress film 20 and the Z or strain applying layer 21 in combination, in-plane biaxial strain can be reduced in the channel region. It can be generated separately. That is, the ladder 15 controls the strain in the channel width direction, and the stress film 20 and the Z or strain applying layer 21 function as a strain introduction layer in the channel length direction. Can be controlled.

In the nMOS, biaxial tensile strain is applied to the subchannel region (see FIG. 6) immediately below the ladder 15 in the channel region in the x and y axis directions. On the other hand, in the region directly below the space 18 where the ladder 15 does not exist, tensile strain is applied in the X-axis direction and compressive strain is applied in the y-axis direction, so it is regarded as uniaxial tensile strain.

[0048] On the other hand, in pMOS, in the subchannel region immediately below ladder 15, compressive strain and tensile strain are applied in the x-axis and y-axis directions, respectively, so this should be regarded as uniaxial compressive strain. Can do. In the area immediately below the space 18 where the ladder 15 does not exist, a biaxial bow I tension strain is applied in the X-axis and y-axis directions.

[0049] This coincides with the strain application direction in which the carrier mobility is improved (S.E.

Thompson et al, IEEE Trans. Electron Devices, 51, 1790 (2004)).

FIG. 11A to FIG. 11C are diagrams for explaining the reason why the carrier mobility is improved in the channel region by the above-described configuration. The conduction band of Si is known to be larger than that of uniaxial due to biaxial tensile strain. That is, as shown in FIG. 11A, the conduction band (Ec) in the conduction band of the subchannel region (see FIG. 6) just below the ladder 15 is lower than the region just below the space 18. Therefore, electrons flow dominantly in the subchannel region, and biaxial tensile strain is generated in the nMOSFET, which makes it possible to confine electrons in the subchannel region.

[0051] Further, it is known that the valence band energy of Si increases the energy of the valence band due to uniaxial compressive strain. That is, as shown in FIG. 11A, the energy of the conduction band is higher in the valence band of the subchannel region than in the region immediately below the space 18. Therefore, the positive holes flow dominantly in the subchannel region, and in the pMOSFET, holes can be confined in the subchannel region where uniaxial compressive strain is generated.

[0052] As a result, the number of carriers with high mobility increases in both the n channel and p channel. Operation is possible.

[0053] In the gate structure 19 of the embodiment, the in-plane biaxial strain can be controlled independently. In the case of nMOSFET, when 0.3% tensile strain is applied in the x-axis (channel length) direction and 0.5% tensile strain is applied in the y-axis (channel width) direction, mobility is improved from the piezoresistance coefficient. When estimating the degree of mobility, the effect of improving mobility by about 1.9 times is obtained compared to the case of one axis. Also in the case of pMOSFET, when 0.6% compressive strain is applied in the X-axis direction and 0.5% tensile strain is applied in the y-axis direction, the effect of improving the mobility by about 1.8 times can be obtained ( See SE Thompson et al, IEEE Trans. Electron Devices, 51, 1790 (2004)).

FIG. 11B and FIG. 11C are diagrams for explaining the confinement of carriers in the subchannels immediately below the ladder 15. In these examples, the ladder (G1) 15 and the metal gate (G2) 16 are formed of metals having different work functions. Fig. 11B shows the band change according to the work function difference in nMOS, and Fig. 11C shows the band change according to the work function difference in pMOS.

As shown in FIG. 11B, in the nMOSFET, the ladder (G1) 15 uses a metal having a work function larger than that of the metal gate (G2) 16. For example, when Au is used for the ladder (G1) 15 and TiN is used for the metal gate (G2) 16, the conduction band of Si directly under the ladder (G1) is compared with that under the metal gate (G2) 16 due to the difference in work function. Since the energy increases, it becomes stronger than the confinement force of electrons in the channel region under the metal gate (G2) 16.

As shown in FIG. 11C, in the pMOSFET, the ladder (G1) 15 uses a metal having a work function smaller than that of the metal gate (G2) 16. For example, if aluminum (A1) is used for ladder (G1) 15 and TiN is used for metal gate (G2) 16, the valence valence band of Si just below ladder (G1) 15 due to the difference in work function (gate) Since the energy is lower than that under G2) 16, the effect is stronger than the confinement of holes in the channel region under metal gate (G2) 16.

FIG. 11D is a diagram showing carrier confinement when the ladder 15 is formed of an insulator such as a silicon nitride film. In this case, the electric field exerted directly below the insulator ladder 25 is weaker than Si just below the metal gate 26, so that the bending of the band is reduced. Thereby, the confinement of carriers in the channel region becomes stronger. Band bending is shown in Fig. 1. As indicated by ID, control is possible by the film thickness of the insulating film (ladder 15).

FIG. 12 shows a modification of FIG. In FIG. 12, the ladder 25 is formed of a metal that applies compressive stress, and then the metal gate 26 is formed of a metal that applies tensile stress. As a result, tensile strain is applied to the subchannel region immediately below the ladder 25, so that the same effect as the above structure can be obtained.

In this structure, when a metal having a different work function is used, a metal having a work function smaller than that of the metal gate (G2) 26 is used for the ladder (G1) 25 in the nMOSFET. In pMOSFE T, a metal having a larger work function than the metal gate (G2) 26 is used for the ladder (G1) 25. As a result, the effect of stronger carrier confinement in the subchannel region immediately below the ladder 25 is obtained.

[0060] When the width of the ladder or space is reduced in the gate structure into which the ladder is introduced, the strain applied to the channel region increases and the change in the band increases. This results in stronger carrier confinement. If the ladder width or space width is reduced to about 10 nm or less, carriers are confined in a very narrow region, and a quantum effect occurs. Thereby, a quantum wire FET can also be realized.

[0061] In this case, since it is not necessary to etch the channel region as in the case of conventional quantum wires, scattering due to surface roughness can be suppressed. Therefore, it leads to further FET high-speed operation.

FIG. 13A to FIG. 13K are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention. First, the Si (100) substrate 31 is used, and the 110> direction is used as the channel direction. Dummy gate removal is performed on this substrate 31 by a conventional damascene metal gate manufacturing process. Specifically, as shown in FIG. 13A, a well region (not shown) is formed in a predetermined region of the Si substrate 31, and an element isolation region (not shown) such as STI is formed. Thereafter, a silicon oxide film 32, a polysilicon film 32, and a silicon nitride film 34 are sequentially formed. The Si oxide film 32 is formed by, for example, a thermal oxidation method, and the polysilicon film 33 and the silicon nitride film 34 are respectively formed by a CVD method.

Next, as shown in FIG. 13B, the dummy gate 35 is formed by patterning the silicon nitride film 34 and the polysilicon film 33 by a normal lithography method and etching method. Dummy game Using the substrate 35 as a mask, impurities are implanted into the substrate 31 to form extensions 36.

Next, as shown in FIG. 13C, sidewall spacers 37 are formed, impurities are implanted at a high concentration using the dummy gate 35 and the sidewall spacers 37 as masks, and heat treatment is performed. Source / drain regions 39 are formed. Thereafter, a silicon nitride film 38 for an etching stopper is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 13D, a silicon oxide film 40 is deposited on the entire surface by the CVD method. Subsequently, using the silicon nitride film 38 as a stopper, the Si oxide film 40 is polished and planarized by the CMP method.

Next, as shown in FIG. 13E, the silicon nitride film 38 (34) and the polysilicon film 33 on the dummy gate are removed with, for example, hot phosphoric acid and a hydrazine solution. Further, the silicon oxide film 32 as a sacrificial gate insulating film is removed with a dilute hydrofluoric acid solution to form an opening 41.

Next, as shown in FIG. 13F, a gate insulating film 53 is formed on the surface of the silicon substrate 31 in the opening 41 by a thermal oxidation method.

Next, as shown in FIG. 13G, a ladder (G 1) 55 is formed in the opening 41. The ladder 55 is patterned by, for example, depositing TiN and performing lift-off or dry etching. The ladder interval (space width) is preferably less than lOOnm in order to effectively apply strain. The number of ladder spaces is an arbitrary number of 1 or more. TiN for Ladder 55 is adjusted to be a stress film that gives no stress or tensile stress. As a method for adjusting the stress of TiN, for example, during the deposition of TiN, a piezoelectric element is used to apply longitudinal vibration to the substrate at a predetermined excitation frequency (for example, 100 Hz), and the amplitude is adjusted by the applied voltage. By doing so, the internal stress can be adjusted in a wide range from no stress to tensile stress (for details, refer to JP-A-2004-68058).

Next, as shown in FIG. 13H, a metal film 56, for example, titanium nitride (TiN) 56 is deposited on the entire surface so as to cover the ladder (G 1) 55 by a sputtering method. TiN formed by sputtering has a large amount of compressive stress!

Next, as shown in FIG. 131, the TiN ladder film 55 and the TiN metal gate 56 remain in the opening by polishing the TiN sputtering film 56 by the CMP method. Ladder 55 and gate electrode The metal structure 56 constitutes a gate structure 59. In the channel region, tensile strain in the channel width direction (direction perpendicular to the current) is generated by the tensile stress of the TiN ladder 55 and the compressive stress of the TiN metal gate 56 by sputtering.

[0071] Next, as shown in FIG. 13J, the Si oxide film 40 is removed, for example, with a buffered hydrofluoric acid solution.

[0072] Finally, as shown in FIG. 13K, a Si nitride film 60 to be a stress film is formed by a CVD method and dry etching. A tensile stress film is selectively formed on the nMOSFET, and a compressive stress film is selectively formed on the pMOSFET. As described above, the main process is completed, and thereafter, a normal wiring process and the like are performed, and the semiconductor device 10 is completed.

[0073] Note that, when the ladder 55 is formed of an insulator instead of TiN, it can be manufactured in the same process.

[0074] (Modification 1)

As shown in FIG. 12, when the ladder 25 is made of a material that applies compressive stress, the dummy gate is removed and the gate insulating film 53 is formed in the same process as in FIGS. 13A to 13F. Thereafter, in a process corresponding to FIG. 13G, TiN is deposited by sputtering, and a ladder 55 is formed by dry etching. TiN produced by sputtering has a strong compressive stress.

Next, in a step corresponding to FIG. 13H and FIG. 131, Au is vapor-deposited and flattened by CMP to form a metal gate 56. Tensile stress is inherent in the deposited Au. As a result, tensile strain is applied to the channel region in the channel width direction perpendicular to the current (see Fig. 12). The subsequent steps are the same as those described above.

[Modification 2]

When metals with different work functions are used for nMOSFET and pMOSFET as shown in Fig. 11B, the dummy gate is removed by the steps from Fig. 13A to Fig. 13F to form the gate insulating film 53, and then to Fig. 13G. The ladder 55 is formed in a corresponding process. In the example shown in Fig. 11B, both nMO S and pMOS use TiN as the ladder, and the force that makes the work function of the metal gate different from each other. The work function of the ladder differs between nMOS and pMOS, and the metal gate is made of the same material. May be formed. [0077] For example, Au is deposited on the nMOSFET, and the ladder 55 is selectively deposited by lift-off. At this time, tensile stress is inherent in the deposited Au. On the other hand, aluminum (A1) is deposited on the pMOSFET, and a ladder 55 having a different work function is formed by lift-off. At this time, weak compressive stress is inherent in A1 by vapor deposition.

Subsequently, in a step corresponding to FIG. 13H and FIG. 131, TiN is deposited by sputtering and flattened by CMP to form a metal gate (electrode body) 56. In pMOS, the weak compressive stress of the A1 gate grid 55 is not a problem because the stress of the TiN metal gate 56 is large. Thereafter, by performing the same process as in the first embodiment, the semiconductor device 10 with a controlled work function is formed. This technique increases carrier confinement and further improves performance.

[0079] As described above, in the configuration of the semiconductor device of the present invention, band control is performed by applying an appropriate strain in directions of two or more axes, and one-dimensional quantum confinement (quantum wire) is realized. . As a result, a significant performance improvement of the Si-MOSFET can be realized.

[0080] Further, in the manufacturing process of the present invention, a quantum wire MOSFET can be realized while maintaining the basic flow of the conventional Si process, so that simplification of the process and improvement in the degree of freedom in design can be expected. .

[0081] In addition, since the channel region cannot be etched unlike the conventional quantum wire, it is possible to suppress scattering due to surface roughness, which leads to further high-speed FET operation.

[0082] Compared to conventional quantum wires using compound semiconductors and SiGeZSi high electron mobility transistors (HEMTs) by realizing Si quantum wire MOSFETs that can control strain independently in two in-plane directions. This is thought to lead to a significant cost reduction.

Claims

The scope of the claims

[1] a silicon substrate;

A gate electrode located on the silicon substrate via a gate insulating film;

A ladder located between the gate insulating film and the gate electrode, arranged in a direction orthogonal to the direction of the current flowing in the channel region immediately below the gate electrode, and having a stress different from that of the gate electrode;

A semiconductor device comprising:

[2] The ladder has inherent compressive stress,

The gate electrode has a compressive stress or tensile stress smaller than that of the ladder.

The semiconductor device according to claim 1, wherein:

[3] Tensile stress is inherent in the ladder,

The gate electrode has a tensile stress or a compressive stress smaller than that of the ladder.

The semiconductor device according to claim 1, wherein:

4. The semiconductor device according to claim 1, wherein the channel region constitutes an n-type channel, and a work function of the ladder is larger than a work function of the gate electrode.

5. The semiconductor device according to claim 1, wherein the channel region constitutes a p-type channel, and a work function of the ladder is smaller than a work function of the gate electrode.

6. The semiconductor device according to claim 1, wherein a width of a stripe constituting the ladder or a space between stripes is equal to or less than lOOnm.

[7] The semiconductor device according to any one of [1] to [3], wherein the ladder is made of metal.

[8] The semiconductor device according to any one of [1] to [3], wherein the ladder is made of an insulating film.

[9] A stress film that covers the gate electrode and strains the channel region in a direction parallel to the direction in which the current flows.

The semiconductor device according to claim 1, further comprising:

[10] A strain applying layer that is located in a source / drain region sandwiching the gate electrode and that strains the channel region in a direction parallel to the direction in which the current flows.

The semiconductor device according to claim 1, further comprising:

[11] A dummy electrode having a sidewall covered with a sidewall spacer is formed on the silicon substrate, the dummy electrode is removed, and an opening is formed between the sidewall spacers. Forming a ladder extending in the direction of 1,

A gate electrode that covers the ladder is formed in the opening with a material having a stress different from that of the ladder.

The manufacturing method of the semiconductor device characterized by including a process.

[12] A stress film that covers the gate electrode and the sidewall spacer, and that applies strain in a direction perpendicular to the first direction is formed on a surface area of the silicon substrate immediately below the gate electrode.

12. The method for manufacturing a semiconductor device according to claim 11, further comprising a step.

[13] The formation of the ladder includes a step of depositing a metal in the opening by sputtering and patterning into a ladder shape with a predetermined interval.

The gate electrode is formed by metal deposition.

12. The semiconductor device according to claim 11, wherein:

[14] The formation of the ladder includes a step of vapor-depositing a metal in the opening and forming a ladder shape with a predetermined interval.

The gate electrode is formed by sputtering metal in the opening.

12. The semiconductor device according to claim 11, wherein:

[15] The ladder includes a step of forming an insulating film in the opening by sputtering and patterning into a ladder shape with a predetermined interval.

The gate electrode is formed by metal deposition.

12. The semiconductor device according to claim 11, wherein:

[16] The method further includes the step of injecting an n-type impurity into the silicon substrate using the dummy gate and the side wall spacer as a mask.

The ladder is made of a material having a work function larger than the work function of the gate electrode! 12. The semiconductor device according to claim 11, wherein the semiconductor device is formed.

Further comprising the step of implanting p-type impurities into the silicon substrate using the dummy gate and side wall spacer as a mask.

12. The semiconductor device according to claim 11, wherein the ladder is made of a material having a work function that is smaller than a work function of the gate electrode.