JPH07202178A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a MOS transistor which is used for realizing an LSI of low power consumption, wherein the MOS transistor can be kept proper in threshold voltage as prescribed even if a substrate is low in impurity concentration. CONSTITUTION:A gate insulating film 12 of thickness 70nm or so is formed on a silicon substrate 11. A polycrystalline silicon film 13a is deposited thereon as thick as 50nm through a chemical evaporation method, and then a gate electrode 13 is formed through plasma etching. A polycrystallino silicon- germanium film 13b is selectively and epitaxially grown as thick as 0.3mum or so on the polycrystalline silicon film 13a through a low-pressure chemical vapor deposition method. As mentioned above, the gate electrode 13 has a two-layered structure composed of the polycrystalline silicon film 13a and the polycrystalline silicon-germanium film 13b, so that. a transistor whose S factor is less than 70mV/dec can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, MIS (M
et al Insulator Semiconductor
to a low power consumption LSI (Large)
It is used in Scale Integrated Circuit).

[0002]

2. Description of the Related Art For example, in order to realize an LSI for low power consumption in a MIS type semiconductor device, it is necessary to make the drain current flowing when a gate voltage is not applied to the MIS transistor as small as possible.

Conventionally, for this purpose, it is important to improve the sub-threshold characteristic of the MIS transistor, and the SOI (Silicon on Insula) is recognized.
tor) structure and SJET (Shallow-Junct)
Ion-well Transistor) structures have been proposed.

For details of the SJET structure, see, for example, "Tohomisa. Mizuno," Anal.
physical Model for High-Per
format Shallow-Junction
-Well Transistor (SJET) wi
th a Fully Depleted Chann
el Structure ”, IEEE TRANSA
CIONS ONE STRUCTRON DEVICE
S. VOL, 4, NO. 1, JANUARY 1993 "
It is described in.

According to these proposals, the S factor (the smaller the better), which is the standard of the subthreshold characteristic, is 7
Improved to 0 mV / dec (90 mV / de for conventional structure)
c) has been done.

Furthermore, in order to improve the S factor,
It is necessary to reduce the impurity concentration of the substrate.

However, when the impurity concentration of the substrate is lowered, the threshold voltage of the transistor is lowered accordingly, which causes a problem that the transistor does not cut off sufficiently.

Therefore, if P-type polycrystalline silicon is used instead of N-type polycrystalline silicon that has been conventionally used as a gate electrode material, then the threshold voltage rises too much to turn on. There is.

[0009]

As described above, in the prior art, when the impurity concentration of the substrate is lowered to improve the S factor, when the gate electrode material is N-type polycrystalline silicon, it is accompanied by it. Since the threshold voltage of the transistor is also lowered, the transistor does not cut off sufficiently, and in the case of P-type polycrystalline silicon, on the contrary, the threshold voltage rises too much to turn on.

Therefore, the present invention provides a semiconductor device capable of maintaining a predetermined threshold voltage even when the impurity concentration of a substrate is lowered and achieving lower power consumption, and a method of manufacturing the same. Has an aim.

[0011]

To achieve the above object, in a semiconductor device of the present invention, a two-layer structure comprising a polycrystalline silicon film and a polycrystalline silicon-germanium film on a gate insulating film. The gate electrode of FIG.

Further, in the method of manufacturing a semiconductor device of the present invention, a step of forming a gate insulating film on a semiconductor substrate, a step of depositing a polycrystalline silicon film on this gate insulating film, and a step of depositing this polycrystalline film. It comprises a step of processing a silicon film into a gate electrode shape and a step of depositing a polycrystalline silicon-germanium film on the gate electrode shaped polycrystalline silicon film.

Further, in the semiconductor device of the present invention,
A gate electrode having a three-layer structure including a polycrystalline silicon film, a polycrystalline silicon-germanium film, and a polycrystalline refractory metal-semiconductor alloy film is provided on the gate insulating film.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a gate insulating film on a semiconductor substrate, a step of depositing a polycrystalline silicon film on the gate insulating film, and a step of depositing the polycrystalline silicon film. A step of processing the silicon film into a gate electrode shape, a step of depositing a polycrystalline silicon-germanium film on the polycrystalline silicon film of the gate electrode shape, and a polycrystalline high melting point on the polycrystalline silicon-germanium film. Depositing a metal-silicon film.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a gate insulating film on a semiconductor substrate, a step of depositing a polycrystalline silicon film on the gate insulating film, and a step of depositing the polycrystalline film A step of processing the silicon film into a gate electrode shape, a step of depositing a polycrystalline silicon-germanium film on the polycrystalline silicon film of the gate electrode shape, and a polycrystalline high melting point on the polycrystalline silicon-germanium film. It comprises a step of depositing a metal film and a step of forming a polycrystalline refractory metal-semiconductor alloy film from the polycrystalline refractory metal film and the polycrystalline silicon-germanium film.

Further, in the method of manufacturing a semiconductor device of the present invention, a step of forming a gate insulating film on a semiconductor substrate, a step of depositing a polycrystalline silicon film on the gate insulating film, and a step of depositing the polycrystalline film The semiconductor substrate including a step of processing a silicon film into a gate electrode shape, a step of depositing a polycrystalline silicon-germanium film on the gate electrode-shaped polycrystalline silicon film, and a step of depositing on the polycrystalline silicon-germanium film. A step of depositing a polycrystalline refractory metal film on the surface of, and reacting the polycrystalline refractory metal film with the polycrystalline silicon-germanium film in contact therewith to form a polycrystalline refractory metal-semiconductor alloy film. It comprises a step of forming and a step of removing the unreacted polycrystalline refractory metal film.

[0017]

According to the present invention, since the work function value of the gate electrode material can be set in the middle of the N-type polycrystalline silicon and the P-type polycrystalline silicon by the above means, the S factor value is 70 mV / dec. The following transistors can be realized.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an M according to a first embodiment of the present invention.
OS (Metal Oxide Semiconductor)
2 shows a cross-sectional structure of a main part of a (tor) type transistor.

That is, on the silicon substrate 11, about 70
A gate electrode 13 having a two-layer structure, for example, is provided via a gate insulating film 12 having a thickness of nm.

The gate electrode 13 is composed of, for example, a polycrystalline silicon film (Si) 13a having a thickness of 50 nm, which is deposited on the gate insulating film 12, and a polycrystalline silicon-germanium film having a thickness of 300 nm, which is deposited thereon. Membrane (S
iGe) 13b.

The source / drain regions 14 and 15 are arranged on the surface regions of the silicon substrate 11 on both sides of the gate electrode 13 as in the case of a normal MOS transistor, and each electrode is formed by a metal film (not shown). Is drawn to the outside.

The conductivity type of the gate electrode 13 is selected from N type and P type depending on a desired threshold voltage.

Further, the smaller the grain size of the polycrystalline silicon film, the more stable the polycrystalline silicon-germanium film deposited on the polycrystalline silicon film can be formed. Therefore, in the limit where the grain size is small, it may be an amorphous film. .

As described above, the gate electrode 13 has a two-layer structure in which the polycrystalline silicon film 13a and the polycrystalline silicon-germanium film 13b are sequentially deposited from the gate insulating film 12 side, whereby the work of the gate electrode material is performed. It becomes possible to set the value of the function between the N-type polycrystalline silicon and the P-type polycrystalline silicon.

As a result, the threshold voltage of the transistor can be set to a predetermined value even when the impurity concentration of the silicon substrate 11 is low.

Here, conventionally, there has been an idea of using a polycrystalline silicon-germanium film for a gate electrode and changing its work function (for example, King,
T. , Et al. "A variable-work
-Function polycrystalline
-Sil-x-Gex material f
or submicrometer CMOS tec
"hology", IEEE Electron De
vice Lett. , EDL-12, no. 10, p
p. 533, Oct. 1991).

However, when an N-type polycrystalline silicon-germanium film is used as the gate electrode, the work function is the same as that of normal polycrystalline silicon because the band edge energy of the conduction band does not change.

Further, although there is a change in work function in the gate electrode of the P-type polycrystalline silicon-germanium film,
When using an nMOS transistor, the N-type gate electrode has a threshold voltage of 0.3V to 0.5V.
It is easy to set the predetermined value.

For this reason, the polycrystalline silicon-germanium film is not generally used for the gate electrode.

However, it has been found that the above reason can be solved by depositing a polycrystalline silicon-germanium film on the gate insulating film via the polycrystalline silicon film.

This is based on the fact that when silicon-germanium is epitaxially grown on silicon, the conduction band energy of silicon on the gate insulating film changes due to the mismatch of lattice constants.

Next, a method of manufacturing the MOS type transistor shown in FIG. 1 will be described with reference to FIGS.

For example, 50 Ωcm to 100 Ωcm
First, a thermal oxide film 21 having a thickness of about 0.2 μm is formed on the surface of the P-type silicon substrate 11. Then, the thermal oxide film 21 in the pMOS transistor region is selectively stripped by a normal photolithography process, and subsequently, N-type impurities are ion-implanted in the pMOS transistor region.

Thereafter, the resist (not shown) is stripped off, and the resist is removed in a mixed atmosphere of nitrogen and oxygen at 1190.degree.
By performing thermal diffusion for about 2 to 2 hours, pM
In the OS transistor region, the surface concentration is 5E16 (5 × 1
Then, the N-well diffusion layer 22 having a junction depth of about 2 μm is formed at a depth of 0 ¹⁶ ) cm ⁻² (above, FIG. 2A).

Next, the thermal oxide film 21 on the surface of the silicon substrate 11 is entirely peeled off, a thermal oxide film 23 having a thickness of about 0.1 μm is formed on the entire surface, and a polycrystalline silicon film having a thickness of about 0.15 μm is formed. 24 and a silicon nitride film 25 having a thickness of about 0.2 μm are uniformly deposited by a normal chemical vapor deposition method.

Then, the active regions of the nMOS and pMOS transistors and the substrate contact or well contact region are covered with a resist (not shown) by a photolithography process, and the silicon nitride film 25 is etched by directional plasma etching.

This etching is performed on the polycrystalline silicon film 24.
Is used as a stopper to prevent damage to the silicon substrate 11 (above, FIG. 2B).

Then, p is formed by a photolithography process.
Resist the MOS transistor area (not shown)
Then, using this resist and the silicon nitride film 25 as a mask, P-type impurity channel stopper ions are implanted into the nMOS transistor region to form an ion implantation layer 26.

The acceleration voltage and the dose amount at this time are such that the final impurity concentration of the ion implantation layer 26 is 1E17 to 5E1.
It is desirable to adjust it to 7 (1 × 10 ^{17 to} 5 × 10 ¹⁷ ) cm ⁻³ and a depth of about 1 μm.

This time, the photolithography process
Resist the MOS transistor area (not shown)
Then, using this resist and the silicon nitride film 25 as a mask, N-type impurity channel stopper ions are implanted into the pMOS transistor region to form an ion implantation layer 27.

At this time, the acceleration voltage and the dose amount are such that the final impurity concentration of the ion implantation layer 27 is 1E17 to 5E1.
It is desirable to adjust to 7 (1 × 10 ^{17 to} 5 × 10 ¹⁷ ) cm ⁻³ and a depth of about 1 μm (see FIG.
(C)).

Next, thermal oxidation is performed to form the silicon nitride film 2
Using 5 as a mask, a field insulating film 28 having a thickness of 0.5 μm to 0.9 μm is formed in the element isolation region.

Then, after the silicon nitride film 25 is peeled off, the surface of the silicon substrate 11 is further oxidized by about 0.1 μm to form a pre-oxidized film 29 (see FIG. 3).
(A)).

Next, the pre-oxidized film 29 is peeled off, and the thickness of 10 nm
After forming the sacrificial oxide film 30 before and after the thickness by thermal oxidation, n
Impurities necessary for the active regions of the MOS and pMOS transistors are ion-implanted to form the P layer 31 and the N layer 32, respectively.

The dose amount of the impurity and the accelerating voltage at this time are varied depending on the use conditions of the transistor and the like. However, when it is desired to improve the S factor, the peak concentration of the channel impurity after the manufacturing process is 1E17 (1 × 10 6).
¹⁷ ) Care should be taken not to exceed cm ^-3 .

Under this condition, the threshold voltage becomes too low in the case of a gate electrode using a normal polycrystalline silicon film, but by using the gate electrode structure according to the present invention, a desired threshold voltage can be obtained. It can be obtained (above, FIG.3 (b)).

Next, after removing the sacrificial oxide film 30 to expose a clean silicon surface, a gate insulating film 12 having a thickness of 70 nm is formed.

The thickness of the gate insulating film 12 is not limited to 70 nm, but is preferably 100 nm or less.

Then, a polycrystalline silicon film 13a having a thickness of 50 nm, for example, is deposited on the gate insulating film 12 by a chemical vapor deposition method.

The film thickness of the polycrystalline silicon film 13a should be slightly different from the thickness of 50 nm because the band structure at the position in contact with the gate insulating film 12 changes after the manufacturing process due to the difference in film quality. May be good.

Further, an insulating film 35 having a thickness of about 50 nm is deposited on the polycrystalline silicon film 13a.

As the insulating film 35, for example, a silicon nitride film is desirable (above, FIG. 3C).

Next, the insulating film 35 and the polycrystalline silicon film 13a are plasma-etched to form the first layer of the gate electrode 13 described above.

At this time, the etching of the polycrystalline silicon film 13a is performed using the gate insulating film 12 as a stopper, and the surfaces of the gate insulating film 12 and the field insulating film 28 are exposed in the region other than the gate electrode 13.

Subsequently, using the insulating film 35 and the polycrystalline silicon film 13a as a mask, a low concentration N ⁻ diffusion layer 36 for reducing the effective channel length is formed by ion implantation in the nMOS transistor region.

Normally, an acceleration voltage of 30 keV and 1E
Phosphorus is ion-implanted at a dose amount of about 13 (1 × 10 ¹³ ) cm ⁻² .

In order to prevent impurities from reaching the channel region in the silicon substrate 11 by this ion implantation, the insulating film 35 is deposited because the polycrystalline silicon film 13a alone is thin. Hereinafter, FIG. 4A).

In the above manufacturing method, the low concentration N ^- diffusion layer 36 may not be formed.

In this case, since it is not necessary to deposit the insulating film 35 on the polycrystalline silicon film 13a in the process of FIG. 3C, the process can be simplified accordingly.

Next, the insulating film 35 is peeled off with a heated phosphoric acid solution or the like to expose the silicon surface of the polycrystalline silicon film 13a.
A polycrystalline silicon-germanium film 13b having a thickness of about 0.3 .mu.m is selectively epitaxially grown thereon by low pressure chemical vapor deposition to form the second layer of the gate electrode 13 described above.

The film formation at this time is performed by using the lattice of the polycrystalline silicon-germanium film 13b and the polycrystalline silicon film 1 below the lattice.
Be careful to grow according to 3a.

Further, at the time of film formation, a gas which becomes a P-type or N-type impurity is mixed into the gas to form a polycrystalline silicon-germanium film 13b and a polycrystalline silicon film 13a thereunder.
Doping with a high concentration (for example, 1E19 (1 × 10 ¹⁹ ) cm ⁻³ or more) is performed.

The composition ratio in the polycrystalline silicon-germanium film 13b depends on the desired threshold voltage of the transistor, but germanium is necessary to obtain a remarkable effect of shifting the threshold voltage by 0.2 V or more. About 50% to 60% is required (above, FIG. 4 (b)).

Then, using the polycrystalline silicon-germanium film 13b as a mask, the source / drain regions 14, 1 are formed.
Impurities are ion-implanted in 5 and thermally diffused to form a high concentration N-type diffusion layer 37 and a P-type diffusion layer 38.

Usually, in order to form the N-type diffusion layer 37, arsenic is used at an acceleration voltage of 50 keV and 5E15 (5 × 1).
In order to form the P-type diffusion layer 38 with a dose of 0 ¹⁵ ) cm ⁻² , boron is used at an acceleration voltage of 35 keV and 5E15.
Ion implantation is performed at a dose of (5 × 10 ¹⁵ ) cm ⁻² .

The thermal diffusion step is performed at a temperature of 800 ° C. for about 1 hour (hereinafter, FIG. 4 (c)).

In the subsequent steps, the formation of the protective insulating film and the wiring of the usual MOS type transistor is performed in the same manner as in the conventional case.

Next, a second embodiment of the present invention will be described.

FIG. 5 shows n according to the second embodiment of the present invention.
1 shows a sectional structure of a main part of a MOS transistor.

In this case, on the silicon substrate 111, about 7
Through the 0 nm-thick gate insulating film 112, for example, 50
A gate electrode 113 having a two-layer structure composed of a polycrystalline silicon film 113a having a thickness of 300 nm and a polycrystalline silicon-germanium film 113b having a thickness of 300 nm is provided, and a P-type region 111a and an N-type region 111 are provided in a silicon substrate 111.
b is formed.

Silicon substrate 111 in P-type region 111a
The depth from the surface of is adjusted to be shallower than that of a normal well, for example, about 0.2 μm.

As a result, immediately below the channel, the depletion region formed by the influence of the gate electrode 113 and the depletion region generated by the PN junction between the P-type region 111a and the N-type region 111b are connected, and the S factor is excellent. It becomes a value.

Next, a method of manufacturing the nMOS type transistor shown in FIG. 5 will be described with reference to FIGS.

For example, 50 Ωcm to 100 Ωcm
First, 0.2 μm is formed on the surface of the N-type silicon substrate 111.
A thermal oxide film 121 of about thickness is formed. Then, the thermal oxide film 121 in the pMOS transistor region is selectively stripped by a normal photolithography process, and then the pM
P-type impurities are ion-implanted into the OS transistor region.

Thereafter, the resist (not shown) is stripped off, and the resist is removed in a mixed atmosphere of nitrogen and oxygen at 1190.degree.
By performing thermal diffusion for about 2 to 2 hours, pM
In the OS transistor region, the surface concentration is 5E16 (5 × 1
The P-well diffusion layer 122 having a junction depth of about 2 μm is formed at 0 ¹⁶ ) cm ⁻² (above, FIG. 6A).

Next, the thermal oxide film 121 on the surface of the silicon substrate 111 is entirely peeled off, a thermal oxide film 123 having a thickness of about 0.1 μm is formed again on the entire surface, and further 0.15 μm is formed.
A polycrystalline silicon film 124 having a thickness of about 0.2 μm and a silicon nitride film 125 having a thickness of about 0.2 μm are uniformly deposited by a normal chemical vapor deposition method.

Then, the active regions of the nMOS and pMOS transistors and the substrate contact or well contact region are covered with a resist (not shown) by a photolithography process, and the silicon nitride film 125 is etched by directional plasma etching.

This etching is performed on the polycrystalline silicon film 12
4 is used as a stopper to prevent damage to the silicon substrate 111 (see FIG. 6).
(B)).

Then, p is formed by a photolithography process.
Resist the MOS transistor area (not shown)
Then, using this resist and the silicon nitride film 125 as a mask, channel stopper ions of P-type impurities are implanted into the nMOS transistor region, and the ion implantation layer 126 is formed.
To form.

The acceleration voltage and the dose amount at this time are such that the final impurity concentration of the ion implantation layer 126 is 1E17 to 5E.
17 (1 × 10 ^{17 to} 5 × 10 ¹⁷ ) cm ⁻³ , depth 1 μm
It is desirable to adjust the degree.

This time, the photolithography process
Resist the MOS transistor area (not shown)
Then, using this resist and the silicon nitride film 125 as a mask, N-type impurity channel stopper ions are implanted into the pMOS transistor region, and the ion implantation layer 127 is formed.
To form.

The acceleration voltage and the dose amount at this time are such that the final impurity concentration of the ion implantation layer 127 is 1E17 to 5E.
17 (1 × 10 ^{17 to} 5 × 10 ¹⁷ ) cm ⁻³ , depth 1 μm
It is desirable to adjust the degree.

In this case, since the ion-implanted layer 126 is connected to the ground potential later and the ion-implanted layer 127 is connected to the power supply voltage later, when the silicon substrate 111 is connected to the ground potential, this silicon substrate 111 is connected. As shown in the drawing, it is necessary to separate the ion implantation layer 127 from the ion-implanted layer 127 by a certain distance D to achieve electrical insulation (see FIG. 6).
(C)).

Then, thermal oxidation is performed to form the silicon nitride film 1
Using 25 as a mask, a field insulating film 128 having a thickness of 0.5 μm to 0.9 μm is formed in the element isolation region.

Then, after removing the silicon nitride film 125, the surface of the silicon substrate 111 is further oxidized to a thickness of about 0.1 μm to form a pre-oxide film 129 (see FIG. 7).
(A)).

Then, the pre-oxide film 129 is peeled off, and 10n
After forming a sacrificial oxide film (not shown) having a thickness of about m by thermal oxidation, the sacrificial oxide film is once peeled to expose a clean silicon surface. And on top of that, 70 nm
A thick gate insulating film 112 is formed.

The thickness of the gate insulating film 112 is not limited to 70 nm, but is preferably 100 nm or less.

Then, a polycrystalline silicon film 113a having a thickness of 50 nm, for example, is deposited on the gate insulating film 112 by a chemical vapor deposition method.

The film thickness of the polycrystalline silicon film 113a varies depending on the film quality, and the gate insulating film 11 is formed after the manufacturing process is completed.
50n because the band structure changes in the area in contact with 2.
In some cases, it may be better to set it slightly forward or backward rather than m thickness.

Further, an insulating film 135 having a thickness of about 50 nm is deposited on the polycrystalline silicon film 113a (above,
FIG. 7B).

Next, the insulating film 135 and the polycrystalline silicon film 113a are plasma-etched to form the first layer of the gate electrode 113 described above.

Subsequently, using the insulating film 135 and the polycrystalline silicon film 113a as a mask, a low concentration N ⁻ diffusion layer 136 for reducing the effective channel length is formed in the nMOS transistor region by ion implantation.

Normally, an acceleration voltage of 30 keV and 1E
Phosphorus is ion-implanted with a dose amount of about 13 (1 × 10 ¹³ ) cm ⁻² (above, FIG. 7C).

Then, the insulating film 135 is peeled off, and the polycrystalline silicon film 113a is covered with 0.3 by a low pressure chemical vapor deposition method.
Polycrystalline silicon-germanium film 113b having a thickness of about μm
Are selectively epitaxially grown to form the second layer of the gate electrode 113 described above.

At this time, a gas which becomes a P-type or N-type impurity is mixed into the gas, and the polycrystalline silicon-germanium film 11 is formed.
3b and the polycrystalline silicon film 113a thereunder are doped at a high concentration (for example, 1E19 (1 × 10 ¹⁹ ) cm ⁻³ or more) (the above is FIG. 8A).

Next, P-type impurities are ion-implanted at a high acceleration voltage into the entire surface of the nMOS transistor region to form an nMOS transistor.
P-type region 1 in silicon substrate 111 in the transistor region
11a is formed.

At this time, ions are also implanted directly below the gate electrode 113 through the gate electrode 113.

In this case, it is necessary to adjust the acceleration voltage so that the peak of the impurity distribution due to the ion implantation is just below the gate insulating film 112.

Specifically, the acceleration voltage is, for example, 110 keV, and 2E12 (2 × 10 ¹² ) cm ⁻² to 4E.
Boron is ion-implanted with a dose amount of about 12 (4 × 10 ¹² ) cm ⁻² .

This is because after the manufacturing process is completed, the gate electrode 1
Immediately below 13, the depth is 0.2 μm and the concentration is 5E16 (5
This is in order to obtain × 10 ¹⁶ ) cm ^-3 .

The P-type region 111a is automatically connected to the ion-implanted layer 126 formed under the field insulating film 128 in the nMOS transistor region, and the substrate potential is formed by a substrate contact formed of a normal P-type diffusion layer. Can be supplied.

Subsequently, N-type impurities are ion-implanted at a high acceleration voltage into the entire surface of the pMOS transistor region, and pMO is formed.
An N-type region 111b is formed in the silicon substrate 111 in the S transistor region.

At this time, ions are also implanted directly below the gate electrode 113 through the gate electrode 113.

In this case, it is necessary to adjust the acceleration voltage so that the peak of the impurity distribution due to the ion implantation is just below the gate insulating film 112.

Specifically, the acceleration voltage is, for example, 320 keV, and 2E12 (2 × 10 ¹² ) cm ⁻² to 4E.
Phosphorus is ion-implanted at a dose of about 12 (4 × 10 ¹² ) cm ⁻² .

This is because after the manufacturing process is completed, the gate electrode 1
Immediately below 13, the depth is 0.2 μm and the concentration is 5E16 (5
This is in order to obtain × 10 ¹⁶ ) cm ^-3 .

The N-type region 111b is automatically connected to the ion-implanted layer 127 formed under the field insulating film 128 in the pMOS transistor region, and the substrate potential formed by a normal N-type diffusion layer is used as the substrate contact. Can be supplied (above, FIG. 8 (b)).

Then, using the polycrystalline silicon-germanium film 113b as a mask, the source / drain regions 11 are formed.
Impurities are ion-implanted into 4, 115 and thermally diffused to form high-concentration N-type diffusion layers 137 and P-type diffusion layers 138.

Normally, in order to form the N type diffusion layer 137,
Arsenic was accelerated at an acceleration voltage of 50 keV and 5E15 (5 × 10
^In order to form the P type diffusion layer 138 with a dose of ¹⁵ ) cm ⁻² , boron is used at an acceleration voltage of 35 keV and 5E15.
Ion implantation is performed at a dose of (5 × 10 ¹⁵ ) cm ⁻² .

The thermal diffusion process is performed at a temperature of 800 ° C. for about 1 hour (hereinafter, FIG. 8C).

In the subsequent steps, the formation of the protective insulating film and the wiring of the normal nMOS type transistor is performed in the same manner as in the conventional case.

Next, a third embodiment of the present invention will be described.

FIG. 9 shows M according to the third embodiment of the present invention.
3 shows a cross-sectional structure of a main part of an OS type transistor.

In this case, on the silicon substrate 211, about 7
For example, a gate electrode 213 having a three-layer structure is provided via a gate insulating film 212 having a thickness of 0 nm.

The gate electrode 213 is formed of, for example, a polycrystalline silicon film 213a having a thickness of 50 nm on the gate insulating film 212 and a polycrystalline silicon-germanium film 213 having a thickness of 300 nm deposited thereon.
b, and a metal film (Metal) 213c attached thereon, for example.

Since the metal film 213c has an effect of lowering the resistance value of the gate electrode 213, the switch time can be shortened by the gate electrode 213 having such a structure.

The metal film 213c can be easily formed on the polycrystalline silicon-germanium film 213b by using, for example, a self-aligned silicidation technique.

Next, referring to FIG. 10, M shown in FIG.
A method of manufacturing the OS type transistor will be described.

For example, the polycrystalline silicon-germanium film 213b, and the N-type diffusion layers 237 and P are formed by the same steps as shown in FIGS. 2A to 4C.
After forming the mold diffusion layer 238, an insulating film (not shown) having a thickness of about 0.2 μm is deposited.

Then, the side wall 24 of the insulating film is formed on the side surface of the gate electrode 213 by the normal directional plasma etching.
1 is formed.

After that, the polycrystalline silicon-germanium film 2 is formed on the gate electrode 213 by using a solution of dilute hydrofluoric acid or the like.
The surface of 13b, and the source / drain regions 214, 2
15, the surfaces of the N-type diffusion layer 237 and the P-type diffusion layer 238 are exposed, and 30 nm to 70 nm are exposed thereon.
A refractory metal film 242 having a thickness of nm is deposited.

For forming the refractory metal film 242, for example, titanium, which has the lowest resistance value after silicidation, is mainly used, but in addition to this, nickel, cobalt, platinum, palladium, or the like can also be used (above). , Fig. 10
(A)).

Then, annealing is performed at 650 ° C. in an atmosphere of argon gas or a mixed gas of argon and nitrogen for about 30 seconds to cause the refractory metal film 242 to react with silicon or silicon-germanium, and the gate electrode 213 and the source, 60 on the surface of the drain regions 214 and 215.
A silicide layer 243 having a thickness of 150 nm to 150 nm is formed.

At this time, the refractory metal film 242 that does not come into contact with silicon or silicon-germanium, that is, the field oxide film 228 and the refractory metal film 242 on the sidewall 241 remain unreacted.

Then, the unreacted refractory metal film 242.
Are selectively removed using a mixed aqueous solution of sulfuric acid and hydrogen peroxide or a mixed aqueous solution of ammonium hydroxide and hydrogen peroxide (above, FIG. 10 (b)).

Thus, the metal film 213 to be the silicide layer 243 is formed on the polycrystalline silicon-germanium film 213b.
By forming c, a gate electrode 213 having a three-layer structure is formed.

In the subsequent steps, the formation of the protective insulating film and the wiring of the ordinary MOS type transistor is performed in the same manner as in the conventional case.

The MO according to the third embodiment described above is used.
The S-type transistor can also be manufactured by selectively depositing the metal film 213c on the polycrystalline silicon-germanium film 213b by a chemical vapor deposition method.

For example, as shown in FIG. 4C, after the gate electrode 13 having a laminated structure composed of the polycrystalline silicon film 13a and the polycrystalline silicon-germanium film 13b is formed, chemical treatment at 600 ° C. to 700 ° C. is performed. The material gas may be vapor-decomposed in a vapor deposition furnace to selectively deposit a silicide film such as tungsten silicide on the gate electrode 13.

At this time, care is taken so that the silicide film is not deposited on the gate insulating film 12.

Next, a fourth embodiment of the present invention will be described.

FIG. 11 shows a sectional structure of a main part of a MOS transistor according to the fourth embodiment of the present invention.

In this case, the SOI (S
For example, a polycrystalline silicon film 313a having a thickness of 50 nm, a polycrystalline silicon-germanium film 313b having a thickness of 300 nm, and a gate insulating film 312 having a thickness of about 70 nm are formed on a substrate 311 formed by using an ilicon on insulator technique. Empty double-layered gate electrode 31
3 is provided.

It is generally known that the S factor has a good value when the substrate region directly under the channel is fully depleted, and therefore the film thickness of the substrate 311 is 0.2 μm.
The following is desirable.

In the MOS type transistor having such a structure, if the gate electrode 313 is manufactured by the same method as in the first embodiment, the conventional SOS (Silicon on) is obtained.
It can be easily produced by the Saphire technique.

As described above, the work function value of the gate electrode material can be set in the middle between the N-type polycrystalline silicon and the P-type polycrystalline silicon.

That is, the gate electrode has a laminated structure in which a polycrystalline silicon-germanium film is laminated on the polycrystalline silicon film. As a result, it becomes possible to set the work hunting acting on the gate insulating film between the silicon and the silicon-germanium due to the change in the conduction band energy of silicon on the gate insulating film, so that the value of the S factor is 70 mV / It is possible to realize a transistor having a dec or less. Therefore, the impurity concentration of the channel portion of the substrate is 5E16 (5 × 10 ¹⁶ ) cm.
^Even if the concentration is as low as ^-3 , a MOS transistor having a predetermined threshold voltage can be manufactured, and an LSI with lower power consumption can be realized.

In each of the first to fourth embodiments described above, the case where the polycrystalline silicon-germanium film is formed only on the upper surface of the polycrystalline silicon film has been described, but the present invention is not limited to this, and for example, FIG. , The polycrystalline silicon film 413a is covered with the polycrystalline silicon film 413a.
A structure including the germanium film 413b may be provided.

In short, the gate electrode 413 on the main region on the channel is made of polycrystalline silicon and polycrystalline silicon.
Any structure may be used as long as it has a stacked structure with germanium and is provided over the substrate 411 with the gate insulating film 412 interposed therebetween.

Further, the present invention can be applied to not only MOS type transistors but also semiconductor devices having various MIS structures.

In addition, it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0143]

As described above in detail, according to the present invention, a semiconductor device capable of maintaining a predetermined threshold voltage even if the impurity concentration of the substrate is lowered and achieving lower power consumption. And the manufacturing method for the same can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a main part of a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a first cross-sectional view similarly shown for explaining a method for manufacturing a MOS transistor.

FIG. 3 is a second sectional view similarly shown for explaining the method for manufacturing the MOS transistor.

FIG. 4 is a third cross-sectional view similarly shown for explaining the method for manufacturing the MOS transistor.

FIG. 5 is a sectional view showing a structure of a main part of an nMOS type transistor according to a second embodiment of the present invention.

FIG. 6 is likewise a first cross-sectional view for explaining a method for manufacturing an nMOS type transistor.

FIG. 7 is a second sectional view similarly shown for explaining a method for manufacturing an nMOS transistor.

FIG. 8 is a third cross-sectional view similarly shown for explaining the method for manufacturing the nMOS type transistor.

FIG. 9 is a sectional view showing a structure of a main part of a MOS transistor according to a third embodiment of the present invention.

FIG. 10 is a sectional view similarly shown for explaining a method for manufacturing a MOS transistor.

FIG. 11 is a sectional view showing a structure of a main part of a MOS transistor according to a fourth embodiment of the present invention.

FIG. 12 is a sectional view showing a structure of a main part of a MOS transistor according to another embodiment of the present invention.

[Explanation of symbols]

11, 111, 211 ... Silicon substrate, 12, 112,
212, 312, 412 ... Gate insulating film, 13, 11
3, 213, 313, 413 ... Gate electrode, 13a, 1
13a, 213a, 313a, 413a ... Polycrystalline silicon film, 13b, 113b, 213b, 313b, 413
b ... Polycrystalline silicon-germanium film, 213c ... Metal film, 311, 411 ... Substrate.

Claims (6)

[Claims] 1. A semiconductor device comprising a gate electrode having a two-layer structure composed of a polycrystalline silicon film and a polycrystalline silicon-germanium film on a gate insulating film. 2. A step of forming a gate insulating film on a semiconductor substrate, a step of depositing a polycrystalline silicon film on the gate insulating film, and a step of processing the polycrystalline silicon film into a gate electrode shape. And a step of depositing a polycrystalline silicon-germanium film on the gate electrode-shaped polycrystalline silicon film. 3. A polycrystalline silicon film on the gate insulating film,
A semiconductor device comprising a gate electrode having a three-layer structure composed of a polycrystalline silicon-germanium film and a polycrystalline refractory metal-semiconductor alloy film. 4. A step of forming a gate insulating film on a semiconductor substrate, a step of depositing a polycrystalline silicon film on the gate insulating film, and a step of processing the polycrystalline silicon film into a gate electrode shape. And a step of depositing a polycrystalline silicon-germanium film on the gate electrode-shaped polycrystalline silicon film, and a step of depositing a polycrystalline refractory metal-silicon film on the polycrystalline silicon-germanium film. A method for manufacturing a characteristic semiconductor device. 5. A step of forming a gate insulating film on a semiconductor substrate, a step of depositing a polycrystalline silicon film on the gate insulating film, and a step of processing the polycrystalline silicon film into a gate electrode shape. Depositing a polycrystalline silicon-germanium film on the gate electrode-shaped polycrystalline silicon film; depositing a polycrystalline refractory metal film on the polycrystalline silicon-germanium film; And a step of forming a polycrystalline refractory metal-semiconductor alloy film from the metal film and the polycrystalline silicon-germanium film. 6. A step of forming a gate insulating film on a semiconductor substrate, a step of depositing a polycrystalline silicon film on the gate insulating film, a step of processing the polycrystalline silicon film into a gate electrode shape, Depositing a polycrystalline silicon-germanium film on a gate electrode-shaped polycrystalline silicon film, and depositing a polycrystalline refractory metal film on the surface of the semiconductor substrate including the polycrystalline silicon-germanium film And a step of forming a polycrystalline refractory metal-semiconductor alloy film by reacting the polycrystalline refractory metal film with the polycrystalline silicon-germanium film in contact therewith, and the unreacted polycrystalline refractory metal And a step of removing the metal film.