WO1999039388A1 - Semiconductor insulating structure with reduced surface field strength and method for the production of the said structure - Google Patents

Semiconductor insulating structure with reduced surface field strength and method for the production of the said structure Download PDF

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Publication number
WO1999039388A1
WO1999039388A1 PCT/DE1999/000118 DE9900118W WO9939388A1 WO 1999039388 A1 WO1999039388 A1 WO 1999039388A1 DE 9900118 W DE9900118 W DE 9900118W WO 9939388 A1 WO9939388 A1 WO 9939388A1
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semiconductor
epitaxial layer
layer
island
field effect
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PCT/DE1999/000118
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German (de)
French (fr)
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Heinz Mitlehner
Dethard Peters
Reinhold SCHÖRNER
Ulrich Weinert
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Siemens Aktiengesellschaft
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Publication of WO1999039388A1 publication Critical patent/WO1999039388A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the invention relates to a semiconductor insulator structure with at least one drift region of a first conductivity type, at least one source electrode for injecting charge carriers into the drift region, at least one drain electrode for sucking the charge carriers out of the drift region, at least one gate connection for Controlling the current of the charge carriers between at least one of the source and drain electrodes and a method for producing such a semiconductor insulator structure.
  • Components in switching and power technology must both reliably block the required reverse voltage and also work with minimal power loss when switched on.
  • the geometry of the component and the dopant concentrations in the individual semiconductor regions are suitably dimensioned.
  • the electrical field strength must not exceed the breakdown or breakdown field strength E BD of the semiconductor material used at any point on the component.
  • the highest field strengths occur at the blocking pn junctions and at the surface of the component that is not shielded by pn junctions.
  • the maximum breakdown field strength of the semiconductor material used is reached.
  • SiC silicon-doped germanium
  • a disadvantage of components with an MIS structure made of SiC compared to components made of Si is, however, that the maximum threshold voltage of the component is determined by the breakdown field strength in the insulator of the MIS structure and this - especially in the case of SiO 2 as an insulator - a great deal is lower than the breakdown voltage of SiC.
  • the problem with SiC is that the breakdown field strength of the semiconductor is significantly higher than the breakdown field strength of the insulator Si0 2 , so that there is degradation of the insulator if the component is operated with field strengths that are close to the breakdown field strength of the semiconductor SiC.
  • the problem of degradation of the electrical properties of the insulator does not occur in silicon devices with Si0 2 as the insulator layer due to the low breakdown field strength of the semiconductor Si compared to the higher breakdown field strength in Si0 2 , even if the full breakdown field strength of the semiconductor is used.
  • the solution according to the invention consists in arranging an island region of a second conductivity type in the region of a first conductivity type in the semiconductor substrate, so that the semiconductor surface is largely shielded from the electric field.
  • the island region serves as a source of stationary charges which act as counter-charges to the charges of the first type in the space charge zone.
  • the island regions are arranged such that the gate electrode is shielded from the drain electrode in the vertical direction.
  • the island regions are dimensioned such that, in a symmetrical position with respect to the gate electrode, as seen from the drain electrode, the trough is twice the amount of a maximum adjustment inaccuracy ⁇ overlap.
  • the trough preferably has a higher dopant concentration on the semiconductor surface and a lower dopant concentration on the side opposite the semiconductor surface.
  • the vertical semiconductor insulator structure controlled by the field effect can be a UMOSFET or VMOSFET, ie the gate electrode is designed as a trench electrode in the drift region.
  • the general field effect controlled vertical semiconductor insulator structure is particularly suitable for a semiconductor device in which the drift region consists of SiC.
  • the island regions of a plurality of cells are preferably arranged in such a way that they form a regular structure.
  • the method according to the invention for producing a vertical semiconductor insulator structure controlled by field effect comprises the steps: applying a semiconductor layer, which serves as a drift path for charge carriers and which is of a first conductivity type, to a semiconductor substrate, arranging at least one well region in the semiconductor layer Applying an insulator layer on the surface of the semiconductor layer, producing a gate electrode separated from the semiconductor layer by the insulator layer, one connected to the semiconductor layer
  • Source electrode and a drain electrode is characterized in that the application of the semiconductor layer comprises the sub-steps: growing a first epitaxial layer of a first conductivity type on the semiconductor substrate, arranging island regions of a second conductivity type in or on the first epitaxial layer, growing a second epitaxial layer of the first conduction type on the first epitaxial layer with the island regions.
  • the island regions of a plurality of cells are arranged on the first epitaxial layer at regular intervals from one another.
  • adjustment structures are etched for later adjustment of a p-well and the wells for the MOSFET are adjusted on the basis of the etched-in adjustment structures.
  • the advantage of the component according to the invention is that a near-surface, field-reduced space is created in the semiconductor substrate, so that the high breakdown field strength of silicon carbide can also be fully used in components with MOS structures without the long-term stability of the components being too high electrical field strengths in the MOS structures is impaired.
  • the shielding of the MOSFET due to the shielding of the MOSFET
  • the invention thus provides the possibility of specifically setting the threshold voltage of the MOSFET by suitable choice of the doping in the region of the inversion channel.
  • the arrangement according to the invention of differently doped semiconductor regions significantly reduces the electrical field in the semiconductor at the border to the insulator, without appreciably impairing the electrical properties of the component in the passage.
  • the full breakdown voltage of the semiconductor material used can thus be utilized with the component according to the invention.
  • Figure 1 shows a MOS-FET as an embodiment of the invention.
  • Figure 2 " shows a MOS-FET according to the prior art.
  • FIG. 3 shows the result of a simulation calculation of the electrical field strength in the component according to FIG. 2.
  • FIG. 4 shows the result of a simulation calculation of the electrical field strength in the device according to the invention
  • FIG. 5 shows a MOS-FET structure as another
  • FIG. 6 shows a MOS-FET as a further embodiment of the invention.
  • the structure of a vertical power MOSFET according to the prior art is shown in FIG. 2. Only one cell is shown. Usually, however, many similar cells are arranged on a semiconductor substrate.
  • the vertical power MOSFET comprises a semiconductor substrate 1 on which an epitaxial layer 2 of a first conductivity type, e.g. n-leading, grew up.
  • the epitaxial layer or semiconductor layer 2 serves as a drift path for charge carriers.
  • a trough 4 of a second conduction type, e.g. B. p-type and within this a first and second implantation area 5 and 6 are provided.
  • the first implantation area 5 is of the same conductivity type as the tub 4, but is more heavily doped.
  • the second implantation region 6 is of the opposite conductivity type to the second conductivity type.
  • An insulator layer 7 is applied to the surface of this structure. It separates a gate electrode 3 from the implantation regions 5 and 6 and from the tub 4 and the epitaxial layer 2 itself. In addition, the insulator layer 7 separates the gate electrode 3 on the other side a metallization of the entire structure, which serves as the source electrode 8. The source electrode 8 is connected directly to the implantation areas 5 and 6 in window areas.
  • the charge carriers injected from the source electrode 8 can flow from the implantation region 6 through a channel in the trough 4 and the epitaxial layer 2 and the semiconductor substrate 1 to a drain electrode 9, which is located on the
  • Source electrode 8 and the gate electrode 3 opposite side of the semiconductor device is located.
  • the disadvantage of this structure is that the electrical field strength penetrates directly from the drain electrode 9 and so there is a high field strength at the transition between the epitaxial layer 2 and the insulator layer 7, which leads to the degradation of the insulator 7.
  • FIG. 1 A further disadvantage of the structure according to the prior art, as shown in FIG. 2, is that if the well 4 is doped more deeply than on the surface, the implant profile is pulled up at the mask edge. As a result, the near-surface doping increases in the region of the MOSFET channel and increases the threshold voltage of the semiconductor switch.
  • the structure according to the invention is shown in FIG. 1. It differs from the structure according to the prior art (FIG. 2) in that it is characterized in that an island region 10 is arranged in the epitaxial layer 2.
  • the elements of the structure according ⁇ Inventive correspond in Figure 1 to those of the structure according to the prior art in Figure 2 and are labeled the same.
  • the island 10 inserted in the epitaxial layer 2 according to the invention serves as a source of stationary charges which act as counter-charges to the foreign atoms (i.e. acceptors or donors) in the space charge zone in the epitaxial layer and largely keep the electric field away from the semiconductor surface.
  • the island 10 does not hinder the flow of current, since it is then flooded with charge carriers.
  • the claimed structure naturally applies to the case of an n-channel MOSFET as well as to the opposite case of a p-channel MOSFET, with only the respective conductivity type of the individual zones of the component having to be “reversed”.
  • the epitaxial layer 2 is of the n-type, the island 10 will be of the p-type and vice versa.
  • the island region 10 is preferably arranged in the drift region, that is to say under the region in which the MOS structure borders directly on the epitaxial layer 2.
  • the electrical field strength was calculated for silicon carbide as a semiconductor material and an applied reverse voltage of 1000 V.
  • the dimensions of the component and the dopant concentrations in the simulation were assumed to be 13 ⁇ m with a 10 ⁇ m well.
  • a cell is understood here as the left or right half of the illustration in FIG. 1 or 2, which are separated from one another by a vertical, dashed line in FIG. 1 and FIG. 2.
  • the tub depth was (including the implantation areas 5 and 6) ) 0.6 ⁇ m, the doping on the surface of the tub 4 was 6-10 16 cm "" 3 to a maximum of 4-10 18 cm “3.
  • the thickness of the epitaxial layer 2 was 12 ⁇ m with a doping of
  • the simulation result is shown as a three-dimensional graphic in FIG. 3.
  • the x-axis shows the horizontal extent in FIG. 2 (ie from left to right and vice versa) of the component in the range between 9 ⁇ m and 14 ⁇ m
  • the y-axis shows the extent of the component perpendicular to the drawing plane in FIG. 2 in the range between 0 and 5 ⁇ m again
  • the z-axis indicates the field strength E in the range between 0 and 300 V / ⁇ m.
  • a structure was used as the MOS structure in which the epitaxial layer 2 was n-doped and the tub was p-doped.
  • the breakdown field strength of silicon carbide which is typically 200 V / ⁇ m (2.0 MV / cm) is first reached at the corner of the p-well of the MOSFET.
  • the electric field strength at the other sections of the pn junction and at the semiconductor surface is approx. 160 V / ⁇ m.
  • the electrical field strength in the oxide 7 of the MOS structure is therefore 400 V / ⁇ m and is thus clearly above the field strength of approximately 200 V / ⁇ m, from which the electrical properties of the insulator 7 begin to degrade.
  • MIS metal insulator semiconductor
  • the normal component of the dielectric displacement from the semiconductor continuously into the insulator of the MIS structure passes, ie the electrical fields in the insulator (Ei) and on the semiconductor surface (Es) are linked by the ratio of the relative dielectric constants of the insulator ( ⁇ t ) and the semiconductor ( ⁇ s ) by:
  • the breakdown field strength (E BD ) of the respective semiconductor material which is a function of the basic doping of the semiconductor, is used as the field on the semiconductor surface.
  • the breakdown strengths given apply to silicon with a dopant concentration of 10 14 cm -3 , for silicon carbide with a dopant concentration of 10 16 cm “3 .
  • Limit field strength for silicon dioxide from which the long-term stability of the insulator is impaired.
  • the limit field strength is typically 200 - 300 V / ⁇ m significantly exceeded in the oxide.
  • the electrical properties of the insulator then degrade in the event of blocking by the injection of charge carriers from the silicon carbide into the oxide.
  • the maximum size for the dimensioning of components with MIS structures is the maximum permissible electric field strength in the oxide.
  • the potential of silicon carbide with regard to the maximum possible reverse voltage can only be used to a very limited extent.
  • FIG. 4 shows the course of the electric field strength in the arrangement according to the invention in three dimensions at a blocking voltage of 1000 V analogously to FIG. 3.
  • the dimensions of the component and the associated dopant concentrations were chosen to be identical to those in the simulation calculation according to FIG. 3.
  • the horizontal extent of the island area 10 was chosen so that in the projection onto an imaginary horizontal line there is an overlap with the tub 4 and the tub 4 and the island area 10 are not conclusive with one another. 2-10 17 cm "3 was selected as the dopant concentration in the island region 10.
  • the island region 10 according to the invention in the epitaxial layer 2 leads to a reduction in the electrical field on the semiconductor surface under the MOS structure; here the electrical field strength is drastically reduced: from 160 V ⁇ m to 65 V / ⁇ m.
  • a space is created above the entire island 10 in which the electrical field is significantly reduced, and the field tip at the corner of the trough 4 of the MOSFET is reduced, ie the breakdown resistance of the component is thus increased overall.
  • the invention thus creates a space near the surface in which the field is reduced.
  • the high breakdown field strength of silicon carbide can also be fully utilized in components with MOS structures without the long-term stability of the components being impaired by excessive electrical field strengths in the MOS structures.
  • the inventors have found that there must not be a gap between the edges of the buried island 10 and the trough 4 of the MOSFET in the x direction in FIG. 4, since the field on the semiconductor surface then grows again very quickly.
  • the overlap between the trough 4 and the island area 10 should therefore be at least ⁇ for a given adjustment error of ⁇ ⁇ .
  • the edges of the buried island region 10 and the trough 4 of the MOSFET then lie exactly one above the other on one side and overlap by 2 ⁇ on the other side.
  • values for the overlap that are smaller than 0 mean that there is a gap between the edges of the island region 10 and the well 4 of the MOSFET.
  • the field strength occurring in the gate oxide at maximum misalignment is 160 V / ⁇ m in this example.
  • this MOSFET can be used up to a reverse voltage of 1000 V without the gate oxide 7 being degraded.
  • the island 10 according to the invention in MOS components thus enables the breakdown field strength of the semiconductor material used to be fully utilized.
  • the orientation in the vertical direction is decisive for the properties of the component.
  • the vertical arrangement of the buried island region 10 is preferably dimensioned according to the requirements for the passage case. The vertical distance between the buried island region 10 and the well 4 of the MOSFET must be large enough to avoid any significant impediment to the current flow due to the JFET effect in the channel between the well 4 and the island region 10. In the embodiment shown in FIG.
  • this structure can be used in all cases in which parts of a component are to be protected against high electrical field strengths or semiconductor regions with a reduced electrical field strength are required.
  • An example of a further application of the invention is the U-MOSFET shown in FIG. 5, in which the maximum field strength in the insulator 7 of the MIS structure at the bottom and at the edges of the U-trenches is likewise exceeded.
  • the U-MOSFET in FIG. 5 comprises a first epitaxial layer 2 of a first conductivity type on a semiconductor substrate 1.
  • a second epitaxial layer 12 of a second conductivity type and a third layer 11 of the first conductivity type in turn are arranged on this.
  • the third layer 11 can also be deposited as an epitaxial layer on the second epitaxial layer 12 or can be produced by implantation in the second epitaxial layer 12.
  • the source contact 8 is connected to the layer 11. orderly.
  • the gate 3, which is separated from the first epitaxial layer 2 and the layers 11 and 12 by an insulator layer 7, is etched into the layers 11 and 12. Otherwise, the same elements as in Figure 1 or 2 are provided with the same reference numerals.
  • an island 10 is arranged in the first epitaxial layer 2 in a U-MOSFET. Although several islands 10 can be arranged in the epitaxial layer 2, only one of them is shown in FIG. 5. The island regions 10 ensure that the field between gate 3 and drain 9 does not stress the insulator 7 and causes it to age, but rather insulator 7 is shielded and less stressed.
  • gate electrode 3 is not essential for the invention. It can therefore also be applied to a VMOSFET etc. instead of a UMSOFET.
  • the doping in the channel region of the MOSFET can be optimized for the threshold voltage.
  • An embodiment with an arrangement for optimizing the doping is shown in FIG.
  • the structure of the embodiment in FIG. 6 essentially corresponds to that of the embodiment according to FIG. 1.
  • the tub 4 has a section 13 which differs from the rest of the tub 4 in terms of its doping .
  • the maximum dopant concentration in the depth of the well 4 is reduced in this section 13.
  • the dopant concentration raised to the semiconductor surface via the implantation mask is reduced and the threshold voltage of the MOSFET is reduced
  • the doping can be reduced to such an extent that in the region of the (not shown) inverter tion channel, ie running within the trough 4 between the implantation region 6 and the epitaxial layer 2 essentially parallel to the surface of the semiconductor, results in a homogeneous doping.
  • the value of this doping depends on the desired threshold voltage.
  • the methods with which the section 13 can be produced in a self-adjusting manner are generally known in the field of semiconductor components and are not further explained here.
  • the electrical field reaches through the island 10 to the semiconductor surface.
  • a plurality of island regions 10 can be arranged in such a way that they form a "large-mesh" grid. The high-precision adjustment process of the well 4 of the MOSFET to the buried island 10 is thus eliminated.
  • the production of the island area 10 described can include the following steps:
  • An epitaxial layer 2 of the same conductivity type is grown on the n-type silicon carbide substrate 1.
  • the p-island regions 10 are implanted in this epitaxial layer 2.
  • Suitable adjustment structures can be etched for later adjustment of the p-well 4. These structures are then overgrown with a further n-epitaxial layer (the continuation of the epitaxial layer 2) of the desired thickness.
  • the p-wells for the MOSFET are now adjusted so that the desired overlap of well 4 and island 10 is achieved.
  • a MOSFET component can be produced according to the invention, the breakdown strength of which is very high and in which the
  • Insulator layer is not exposed to a high permanent load and thus has a longer average life.

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Abstract

The invention has the aim of providing a component in which maximum field strength in the semiconductor substrate can be used without causing degradation of the electrical properties of the insulating layer and a method for producing such a component. The inventive vertical field effect semiconductor insulating structure is characterized in that an island area having a second type of conduction is arranged in the drift area. The vertical semiconductor insulating structure is produced by growing a first epitaxial layer of a first type of conduction on the semiconductor substrate, by arranging the island areas of a second type of conduction in or on the first epitaxial layer and by growing a second epitaxial layer of the first type of conduction on the first epitaxial layer with the island areas.

Description

Beschreibung description
HALBLEITER-ISOLATOR-STRUKTUR MIT REDUZIERTER FELDSTÄRKE AN DER OBERFLÄCHE UND VERFAHREN ZUR HERSTELLUNG DERSELBENSEMICONDUCTOR ISOLATOR STRUCTURE WITH REDUCED FIELD THICKNESS ON THE SURFACE AND METHOD FOR PRODUCING THE SAME
Die Erfindung betrifft eine Halbleiter-Isolator-Struktur mit wenigstens einem Driftgebiet von einem ersten Leitungstyp, wenigstens einer Source-Elektrode zum Injizieren von Ladungsträgern in das Driftgebiet, wenigstens einer Drain- Elektrode zum Absaugen der Ladungsträger aus dem Driftgebiet, wenigstens einem Gate-Anschluß zum Steuern des Stromes der Ladungsträger zwischen wenigstens einer der Source- und der Drain-Elektroden sowie ein Verfahren zur Herstellung einer solchen Halbleiter-Isolator-Struktur.The invention relates to a semiconductor insulator structure with at least one drift region of a first conductivity type, at least one source electrode for injecting charge carriers into the drift region, at least one drain electrode for sucking the charge carriers out of the drift region, at least one gate connection for Controlling the current of the charge carriers between at least one of the source and drain electrodes and a method for producing such a semiconductor insulator structure.
Bauelemente der Schalt- und Leistungstechnik müssen sowohl eine geforderte Sperrspannung sicher blockieren als auch im eingeschalteten Zustand mit minimaler Verlustleistung arbeiten. Um diese Anforderungen zu erfüllen, werden die Geome- trie des Bauelementes und die Dotierstoffkonzentrationen in den einzelnen Halbleitergebieten geeignet dimensioniert. Im Sperrfall darf dabei die elektrische Feldstärke an keiner Stelle des Bauelementes die breakdown- oder Durchbruchfeidstärke EBD des verwendeten Halbleitermaterials überschreiten. Die höchsten Feldstärken treten an den sperrenden pn-Über- gängen und an der nicht durch pn-Übergänge abgeschirmten Oberfläche des Bauelementes auf. Hier wird im Sperrfall maximal die Durchbruchfeldstärke des verwendeten Halbleitermaterials erreicht.Components in switching and power technology must both reliably block the required reverse voltage and also work with minimal power loss when switched on. In order to meet these requirements, the geometry of the component and the dopant concentrations in the individual semiconductor regions are suitably dimensioned. In the event of blocking, the electrical field strength must not exceed the breakdown or breakdown field strength E BD of the semiconductor material used at any point on the component. The highest field strengths occur at the blocking pn junctions and at the surface of the component that is not shielded by pn junctions. In the case of blocking, the maximum breakdown field strength of the semiconductor material used is reached.
Für Bauelemente der Schalt- und Leistungstechnik wurde bisher fast ausschließlich Silicium als Halbleitermaterial eingesetzt. Ein weiterer Halbleiter ist SiC. Gegenüber Si als Halbleitermaterial bietet SiC die Vorteile einer sehr hohen Spannungsfestigkeit. Mit SiC wird es daher möglich,So far, almost exclusively silicon has been used as a semiconductor material for components in switching and power engineering. Another semiconductor is SiC. Compared to Si as a semiconductor material, SiC offers the advantages of a very high dielectric strength. With SiC it is therefore possible
Bauelemente für sehr viel höhere Spannungen herzustellen als mit Si. Bauelemente mit SiC als Halbleitermaterial sind z. B. in „Critical Materials, Device Design, Performance and Reliability Issues in 4H-SiC Power UMOSFET Structures", Materials Research Society, Spring Meeting, 8. - 12. April 1996, San Francisco, von Agarwal et al . beschrieben.Manufacture components for much higher voltages than with Si. Components with SiC as a semiconductor material are e.g. B. in "Critical Materials, Device Design, Performance and Reliability Issues in 4H-SiC Power UMOSFET Structures", Materials Research Society, Spring Meeting, April 8-12, 1996, San Francisco, by Agarwal et al.
Ein Nachteil von Bauelementen mit MIS-Struktur aus SiC gegenüber Bauelementen aus Si liegt jedoch darin, daß die maximale Einsatzspannung des Bauelements durch die Durch- bruchfeldstärke in dem Isolator der MIS-Struktur bestimmt wird und diese - insbesondere bei Si02 als Isolator - sehr viel niedriger liegt als die Durchbruchspannung von SiC. Mit anderen Worten, man hat bei SiC das Problem, daß die Durchbruchfeidstärke des Halbleiters deutlich über der Durchbruchfeidstärke des Isolators Si02 liegt, so daß es zu einer Degradation des Isolators kommt, wenn man das Bauelement mit Feldstärken betreibt, die in der Nähe der Durchbruchfeidstärke des Halbleiters SiC liegen. Dagegen tritt bei Silicium-Bauele enten mit Si02 als Isolatorschicht aufgrund der niedrigen Durchbruchfeldstärke des Halbleiters Si gegen- über der höheren Durchbruchfeldstärke in Si02 das Problem der Degradation der elektrischen Eigenschaften des Isolators nicht auf, auch wenn die volle Durchbruchfeldstärke des Halbleiters genutzt wird.A disadvantage of components with an MIS structure made of SiC compared to components made of Si is, however, that the maximum threshold voltage of the component is determined by the breakdown field strength in the insulator of the MIS structure and this - especially in the case of SiO 2 as an insulator - a great deal is lower than the breakdown voltage of SiC. In other words, the problem with SiC is that the breakdown field strength of the semiconductor is significantly higher than the breakdown field strength of the insulator Si0 2 , so that there is degradation of the insulator if the component is operated with field strengths that are close to the breakdown field strength of the semiconductor SiC. In contrast, the problem of degradation of the electrical properties of the insulator does not occur in silicon devices with Si0 2 as the insulator layer due to the low breakdown field strength of the semiconductor Si compared to the higher breakdown field strength in Si0 2 , even if the full breakdown field strength of the semiconductor is used.
Aufgabe der vorliegenden Erfindung ist es, ein Bauelement zu schaffen, bei dem die maximale Feldstärke in dem Halbleitersubstrat ausgenutzt werden kann, ohne daß es zu einer Degradation der elektrischen Eigenschaften einer Isolatorschicht kommt, sowie ein Verfahren zum Herstellen eines solchen Bauelements anzugeben.It is an object of the present invention to provide a component in which the maximum field strength in the semiconductor substrate can be used without the electrical properties of an insulator layer being degraded, and to specify a method for producing such a component.
Diese Aufgabe wird gelöst durch ein Bauelement mit den Merkmalen nach Anspruch 1 bzw. ein Verfahren nach Anspruch 8. Die Unteransprüche beziehen sich auf bevorzugte Ausführungs- formen der Erfindung. Die erfindungsgemäße Lösung besteht darin, im Halbleitersubstrat einen Inselbereich eines zweiten Leitungstyps in einem Bereich von einem ersten Leitungstyp anzuordnen, so daß die Halbleiteroberfläche gegen das elektrische Feld weitgehend abgeschirmt ist. Der Inselbereich dient als Quelle ortsfester Ladungen, die als Gegenladungen zu den Ladungen vom ersten Typ in der Raumladungszone wirken.This object is achieved by a component with the features according to claim 1 and a method according to claim 8. The subclaims relate to preferred embodiments of the invention. The solution according to the invention consists in arranging an island region of a second conductivity type in the region of a first conductivity type in the semiconductor substrate, so that the semiconductor surface is largely shielded from the electric field. The island region serves as a source of stationary charges which act as counter-charges to the charges of the first type in the space charge zone.
Die erfindungsgemäße durch Feldeffekt gesteuerte vertikale Halbleiter-Isolator-Struktur mit wenigstens einem Driftgebiet von einem ersten Leitungstyp, wenigstens einer Source-Elektrode zum Injizieren von Ladungsträgern in das Driftgebiet, wenigstens einer Drain-Elektrode zum Absaugen der Ladungsträger aus dem Driftgebiet, wenigstens einer Gate-Elektrode zum Steuern des Stromes der Ladungsträger zwischen wenigstens einer der Source- und der Drain-Elektroden, ist dadurch gekennzeichnet, daß in dem Driftgebiet jeweils ein Inselbereich von einem zweiten Leitungstyp angeordnet ist.The vertical semiconductor insulator structure according to the invention controlled by field effect with at least one drift region of a first conductivity type, at least one source electrode for injecting charge carriers into the drift region, at least one drain electrode for suctioning the charge carriers out of the drift region, at least one gate Electrode for controlling the current of the charge carriers between at least one of the source and drain electrodes is characterized in that an island region of a second conductivity type is arranged in each case in the drift region.
In einer Ausführungsform der durch Feldeffekt gesteuerten vertikalen Halbleiter-Isolator-Struktur sind die Inselbereiche so angeordnet, daß in vertikaler Richtung die Gate- Elektrode von der Drain-Elektrode abgeschirmt ist.In one embodiment of the vertical semiconductor insulator structure controlled by the field effect, the island regions are arranged such that the gate electrode is shielded from the drain electrode in the vertical direction.
In einer weiteren Ausführungsform der durch Feldeffekt gesteuerten vertikalen Halbleiter-Isolator-Struktur sind die Inselbereiche so dimensioniert, daß sie in symmetrischer Position in bezug auf die Gate-Elektrode von der Drain- Elektrode aus gesehen die Wanne um das Zweifache des Betrags einer maximalen Justierungenauigkeit δ überlappen.In a further embodiment of the vertical semiconductor insulator structure controlled by the field effect, the island regions are dimensioned such that, in a symmetrical position with respect to the gate electrode, as seen from the drain electrode, the trough is twice the amount of a maximum adjustment inaccuracy δ overlap.
Vorzugsweise weist die Wanne eine höhere Dotierstoffkonzen- tration an der Halbleiteroberfläche und eine niedrigere Dotierstoffkonzentration auf der der Halbleiteroberfläche gegenüberliegenden Seite auf. Insbesondere kann die durch Feldeffekt gesteuerte vertikale Halbleiter-Isolator-Struktur ein UMOSFET oder VMOSFET sein, d. h. die Gate-Elektrode ist als Graben-Elektrode in dem Driftgebiet ausgeführt.The trough preferably has a higher dopant concentration on the semiconductor surface and a lower dopant concentration on the side opposite the semiconductor surface. In particular, the vertical semiconductor insulator structure controlled by the field effect can be a UMOSFET or VMOSFET, ie the gate electrode is designed as a trench electrode in the drift region.
Die allgemeine durch Feldeffekt gesteuerte vertikale Halbleiter-Isolator-Struktur ist besonders geeignet für ein Halbleiterbauelement, bei dem das Driftgebiet aus SiC besteht .The general field effect controlled vertical semiconductor insulator structure is particularly suitable for a semiconductor device in which the drift region consists of SiC.
Bei mehreren Zellen einer durch Feldeffekt gesteuerte vertikale Halbleiter-Isolator-Struktur auf einem Halbleitersubstrat werden die Inselbereiche mehrerer Zellen vorzugsweise so angeordnet, daß sie eine regelmäßige Struktur bilden.In the case of a plurality of cells of a vertical semiconductor insulator structure controlled by a field effect on a semiconductor substrate, the island regions of a plurality of cells are preferably arranged in such a way that they form a regular structure.
Das erfindungsgemäße Verfahren zum Herstellen einer durch Feldeffekt gesteuerten vertikalen Halbleiter-Isolator- Struktur umfaßt die Schritte: Aufbringen einer Halbleiterschicht, die als Driftstrecke für Ladungsträger dient und die von einem ersten Leitungstyp ist, auf ein Halbleiter- substrat, Anordnen wenigstens eines Wannenbereichs in der Halbleiterschicht, Aufbringen einer Isolatorschicht auf der Oberfläche der Halbleiterschicht, Erzeugen einer von der Halbleiterschicht durch die Isolatorschicht getrennten Gate- Elektrode, einer mit der Halbleiterschicht verbundenenThe method according to the invention for producing a vertical semiconductor insulator structure controlled by field effect comprises the steps: applying a semiconductor layer, which serves as a drift path for charge carriers and which is of a first conductivity type, to a semiconductor substrate, arranging at least one well region in the semiconductor layer Applying an insulator layer on the surface of the semiconductor layer, producing a gate electrode separated from the semiconductor layer by the insulator layer, one connected to the semiconductor layer
Source-Elektrode und einer Drain-Elektrode, und ist dadurch gekennzeichnet, daß das Aufbringen der Halbleiterschicht die Teilschritte umfaßt: Aufwachsen einer ersten Epitaxieschicht eines ersten Leitungstyps auf das Halbleitersubstrat, Anord- nen von Inselbereichen eines zweiten Leitungstyps in oder auf der ersten Epitaxieschicht, Aufwachsen einer zweiten Epitaxieschicht des ersten Leitungstyps auf der ersten Epitaxieschicht mit den Inselbereichen.Source electrode and a drain electrode, and is characterized in that the application of the semiconductor layer comprises the sub-steps: growing a first epitaxial layer of a first conductivity type on the semiconductor substrate, arranging island regions of a second conductivity type in or on the first epitaxial layer, growing a second epitaxial layer of the first conduction type on the first epitaxial layer with the island regions.
Insbesondere werden bei dem erfindungsgemäßen Verfahren die Inselbereiche mehrerer Zellen in regelmäßigen Abständen voneinander auf der ersten Epitaxieschicht angeordnet. In einer bevorzugten Ausführungsform werden nach dem Aufwachsen der ersten Epitaxieschicht zur späteren Justierung einer p-Wanne Justierstrukturen geätzt und anhand der eingeätzten Justiertstrukturen die Wannen für den MOSFET justiert .In particular, in the method according to the invention, the island regions of a plurality of cells are arranged on the first epitaxial layer at regular intervals from one another. In a preferred embodiment, after the growth of the first epitaxial layer, adjustment structures are etched for later adjustment of a p-well and the wells for the MOSFET are adjusted on the basis of the etched-in adjustment structures.
Der Vorteil des erfindungsgemäßen Bauelements besteht darin, daß ein oberflächennaher, feldreduzierter Raum in dem Halb- leitersubstrat geschaffen wird, so daß die hohe Durchbruchfeldstärke von Siliciumcarbid auch bei Bauelementen mit MOS- Strukturen voll genutzt werden kann, ohne daß die Langzeitstabilität der Bauelemente durch zu hohe elektrische Feldstärken in den MOS-Strukturen beeinträchtigt wird. Außerdem läßt sich bei einem MOSFET aufgrund der Abschirmung desThe advantage of the component according to the invention is that a near-surface, field-reduced space is created in the semiconductor substrate, so that the high breakdown field strength of silicon carbide can also be fully used in components with MOS structures without the long-term stability of the components being too high electrical field strengths in the MOS structures is impaired. In addition, due to the shielding of the MOSFET
Feldes durch den Inselbereich die Dotierstoff onzentration in der Wanne so einstellen, daß sich im Bereich des Inversionskanals eine homogene Dotierung ergibt. Mit der Erfindung ergibt sich somit die Möglichkeit, die Einsatzspannung des MOSFET durch geeignete Wahl der Dotierung im Bereich des Inversionskanals gezielt einzustellen.Field through the island area adjust the dopant concentration in the trough so that a homogeneous doping results in the area of the inversion channel. The invention thus provides the possibility of specifically setting the threshold voltage of the MOSFET by suitable choice of the doping in the region of the inversion channel.
Die erfindungsgemäße Anordnung unterschiedlich dotierter Halbleitergebiete reduziert das elektrische Feld im Halb- leiter an der Grenze zum Isolator deutlich, ohne die elektrischen Eigenschaften des Bauelements im Durchlaß nennenswert zu beeinträchtigen. Mit dem erfindungsgemäßen Bauelement kann somit die volle Durchbruchspannung des verwendeten Halbleitermaterials ausgenutzt werden.The arrangement according to the invention of differently doped semiconductor regions significantly reduces the electrical field in the semiconductor at the border to the insulator, without appreciably impairing the electrical properties of the component in the passage. The full breakdown voltage of the semiconductor material used can thus be utilized with the component according to the invention.
Weitere Merkmale und Vorteile ergeben sich aus der folgenden Beschreibung von zeichnerisch dargestellten Ausführungsbeispielen der Erfindung.Further features and advantages result from the following description of exemplary embodiments of the invention which are shown in the drawings.
Figur 1 zeigt einen MOS-FET als eine Ausführungsform der Erfindung. Figur 2 "zeigt einen MOS-FET nach dem Stand der Technik. Figur 3 zeigt das Ergebnis einer Simulationsrechnung der elektrischen Feldstärke in dem Bauelement nach Figur 2. Figur 4 zeigt das Ergebnis einer Simulationsrechnung der elektrischen Feldstärke in dem erfindungsgemäßenFigure 1 shows a MOS-FET as an embodiment of the invention. Figure 2 " shows a MOS-FET according to the prior art. FIG. 3 shows the result of a simulation calculation of the electrical field strength in the component according to FIG. 2. FIG. 4 shows the result of a simulation calculation of the electrical field strength in the device according to the invention
Bauelement nach Figur 1. Figur 5 zeigt eine MOS-FET-Struktur als eine weitereComponent according to FIG. 1. FIG. 5 shows a MOS-FET structure as another
Ausführungsform der Erfindung. Figur 6 zeigt einen MOS-FET als eine weitere Ausführungsform der Erfindung.Embodiment of the invention. FIG. 6 shows a MOS-FET as a further embodiment of the invention.
Die Erfindung wird im folgenden anhand eines vertikalen Leistungs-MOSFET als Ausführungsbeispiel näher beschrieben und im Vergleich zum Stand der Technik dargestellt.The invention is described in more detail below using a vertical power MOSFET as an exemplary embodiment and is shown in comparison with the prior art.
Ein vertikaler Leistungs-MOSFET nach dem Stand der Technik ist in seinem Aufbau in Figur 2 gezeigt. Dargestellt ist nur eine Zelle. Üblicherweise sind jedoch viele gleichartige Zellen auf einem Halbleitersubstrat angeordnet. Der verti- kale Leistungs-MOSFET umfaßt ein Halbleitersubstrat 1, auf dem eine Epitaxieschicht 2 von einem ersten Leitungstyp, z.B. n-leitend, aufgewachsen ist. Die Epitaxieschicht oder Halbleiterschicht 2 dient als Driftstrecke für Ladungsträger. In dieser Epitaxieschicht 2 sind als Source-Anschluß und als Leitungskanal eine Wanne 4 von einem zweiten Leitungstyp, z. B. p-leitend, und innerhalb dieser ein erster und zweiter Implantationsbereich 5 bzw. 6 vorgesehen. Der erste Implantationsbereich 5 ist von demselben Leitungstyp wie die Wanne 4, ist aber stärker dotiert. Der zweite Implantationsbereich 6 ist vom dem zweiten Leitungstyp entgegengesetzten Leitungstyp.The structure of a vertical power MOSFET according to the prior art is shown in FIG. 2. Only one cell is shown. Usually, however, many similar cells are arranged on a semiconductor substrate. The vertical power MOSFET comprises a semiconductor substrate 1 on which an epitaxial layer 2 of a first conductivity type, e.g. n-leading, grew up. The epitaxial layer or semiconductor layer 2 serves as a drift path for charge carriers. In this epitaxial layer 2 are a trough 4 of a second conduction type, e.g. B. p-type, and within this a first and second implantation area 5 and 6 are provided. The first implantation area 5 is of the same conductivity type as the tub 4, but is more heavily doped. The second implantation region 6 is of the opposite conductivity type to the second conductivity type.
Auf der Oberfläche dieser Struktur ist eine Isolatorschicht 7 aufgebracht. Sie trennt eine Gate-Elektrode 3 von den Implantationsbereichen 5 und 6 sowie von der Wanne 4 und der Epitaxieschicht 2 selbst. Außerdem trennt die Isolatorschicht 7 die Gate-Elektrode 3 auf der anderen Seite von einer Metallisierung der gesamten Struktur, die als Source- Elektrode 8 dient. Die Source-Elektrode 8 ist in Fensterbereichen direkt mit den Implantationsbereichen 5 und 6 verbunden.An insulator layer 7 is applied to the surface of this structure. It separates a gate electrode 3 from the implantation regions 5 and 6 and from the tub 4 and the epitaxial layer 2 itself. In addition, the insulator layer 7 separates the gate electrode 3 on the other side a metallization of the entire structure, which serves as the source electrode 8. The source electrode 8 is connected directly to the implantation areas 5 and 6 in window areas.
Die von der Source-Elektrode 8 injizierten Ladungsträger können je nach Vorspannung der Gate-Elektrode 3 von dem Implantationsbereich 6 durch einen Kanal in der Wanne 4 und die Epitaxieschicht 2 sowie das Halbleitersubstrat 1 zu einer Drain-Elektrode 9 abfließen, die sich auf der derDepending on the bias of the gate electrode 3, the charge carriers injected from the source electrode 8 can flow from the implantation region 6 through a channel in the trough 4 and the epitaxial layer 2 and the semiconductor substrate 1 to a drain electrode 9, which is located on the
Source-Elektrode 8 und der Gate-Elektrode 3 gegenüberliegenden Seite des Halbleiterbauelements befindet.Source electrode 8 and the gate electrode 3 opposite side of the semiconductor device is located.
Der Nachteil dieses Aufbaus liegt darin, daß die elektrische Feldstärke direkt von der Drain-Elektrode 9 durchgreift und sich so an dem Übergang zwischen Epitaxieschicht 2 und Isolatorschicht 7 eine hohe Feldstärke ergibt, die zur Degradation des Isolators 7 führt.The disadvantage of this structure is that the electrical field strength penetrates directly from the drain electrode 9 and so there is a high field strength at the transition between the epitaxial layer 2 and the insulator layer 7, which leads to the degradation of the insulator 7.
Dies ist ein Problem, das sich erstmalig bei SiC-Bauelemen- ten stellt. Da für Bauelemente der Schalt- und Leistungstechnik bisher fast ausschließlich der Halbleiter Silicium eingesetzt wurde, tritt aufgrund der niedrigen Durchbruchfeldstärke des Halbleiters dieses Problem der Degradation der elektrischen Eigenschaften von MIS-Strukturen auf Si- Basis mit Siliciumdioxid nicht auf, auch wenn die volle Durchbruchfeldstärke des Halbleiters genutzt wird.This is a problem that arises for the first time with SiC components. Since silicon has almost exclusively been used for components in switching and power engineering, this problem of degradation of the electrical properties of Si-based MIS structures with silicon dioxide does not occur due to the low breakdown field strength of the semiconductor, even if the full breakdown field strength of the Semiconductor is used.
Ein weiterer Nachteil der Struktur nach dem Stand der Technik, wie sie in Figur 2 gezeigt ist, besteht darin, daß bei höherer Dotierung der Wanne 4 in der Tiefe als an der Oberfläche das Implantationsprofil an der Maskenkante hochgezogen wird. Dadurch steigt die oberflächennahe Dotierung im Bereich des MOSFET-Kanals an und erhöht die Einsatzspannung des Halbleiterschalters. Die erfindungsgemäße Struktur ist in Figur 1 dargestellt. Sie unterscheidet sich von der Struktur nach dem Stand der Technik (Figur 2) dadurch bzw. ist gekennzeichnet dadurch, daß ein Inselbereich 10 in der Epitaxieschicht 2 angeordnet ist. Im übrigen entsprechen die Elemente der erfindungs¬ gemäßen Struktur in Figur 1 denen der Struktur nach dem Stand der Technik in Figur 2 und sind gleich bezeichnet.A further disadvantage of the structure according to the prior art, as shown in FIG. 2, is that if the well 4 is doped more deeply than on the surface, the implant profile is pulled up at the mask edge. As a result, the near-surface doping increases in the region of the MOSFET channel and increases the threshold voltage of the semiconductor switch. The structure according to the invention is shown in FIG. 1. It differs from the structure according to the prior art (FIG. 2) in that it is characterized in that an island region 10 is arranged in the epitaxial layer 2. Moreover, the elements of the structure according ¬ Inventive correspond in Figure 1 to those of the structure according to the prior art in Figure 2 and are labeled the same.
Die erfindungsgemäß eingefügte Insel 10 in der Epitaxie- schicht 2 dient als Quelle ortsfester Ladungen, die als Gegenladungen zu den Fremdatomen (d. h. Akzeptoren oder Donatoren) in der Raumladungszone in der Epitaxieschicht wirken und das elektrische Feld weitgehend von der Halbleiteroberfläche fernhalten. Wenn das Bauelement im Durchlaß betrieben wird, behindert die Insel 10 dagegen den Stromfluß nicht, da sie dann von Ladungsträgern überschwemmt wird.The island 10 inserted in the epitaxial layer 2 according to the invention serves as a source of stationary charges which act as counter-charges to the foreign atoms (i.e. acceptors or donors) in the space charge zone in the epitaxial layer and largely keep the electric field away from the semiconductor surface. On the other hand, when the component is operated in the passage, the island 10 does not hinder the flow of current, since it is then flooded with charge carriers.
Die beanspruchte Struktur gilt selbstverständlich für den Fall eines n-Kanal-MOSFET genauso wie für den entgegen- gesetzten Fall eines p-Kanal-MOSFET, wobei nur der jeweilige Leitungstyp der einzelnen Zonen des Bauelements „umgedreht" werden muß. Wenn z. B. die Epitaxieschicht 2 vom n-Typ ist, wird die Insel 10 vom p-Typ sein und umgekehrt.The claimed structure naturally applies to the case of an n-channel MOSFET as well as to the opposite case of a p-channel MOSFET, with only the respective conductivity type of the individual zones of the component having to be “reversed”. the epitaxial layer 2 is of the n-type, the island 10 will be of the p-type and vice versa.
Vorzugsweise ist der Inselbereich 10 im Driftgebiet, also unter dem Gebiet, in dem die MOS-Struktur direkt an die Epitaxieschicht 2 grenzt, angeordnet.The island region 10 is preferably arranged in the drift region, that is to say under the region in which the MOS structure borders directly on the epitaxial layer 2.
Die elektrischen Eigenschaften des Halbleiterbauelements nach Figur 1 und nach Figur 2 werden im folgenden miteinander verglichen, wobei auf die graphische Darstellung von Simulationsrechnungen in Figur 3 und Figur 4 Bezug genommen wird, die mit einem Finite-Elemente-Programm erstellt wurden.The electrical properties of the semiconductor component according to FIG. 1 and according to FIG. 2 are compared with one another in the following, reference being made to the graphic representation of simulation calculations in FIG. 3 and FIG. 4, which were created using a finite element program.
Die Simulation des Feldverlaufs in der Struktur nach dem Stand der Technik, wie sie in Figur 2 dargestellt ist, ist in Figur 3 gezeigt. Die Berechnung der elektrischen Feldstärke wurde für Siliciumcarbid als Halbleitermaterial und eine angelegte Sperrspannung von 1000 V durchgeführt. Als Abmessungen des Bauelements und die Dotierstoffkonzentra- tionen wurde bei der Simulation eine Zellänge von 13 μm mit 10 μm Wannenlänge angenommen. (Als eine Zelle wird hier die linke oder rechte Hälfte der Darstellung in Figur 1 oder 2 verstanden, die durch eine vertikale, gestrichelte Linie in Figur 1 und Figur 2 voneinander getrennt sind.) Die Wannen- tiefe betrug (einschließlich der Implantationsbereiche 5 und 6) 0,6 μm, die Dotierung an der Oberfläche der Wanne 4 betrug 6-1016 cm""3 bis maximal 4-1018 cm"3. Die Dicke der Epitaxieschicht 2 betrug 12 μm bei einer Dotierung vonThe simulation of the field profile in the structure according to the prior art, as shown in Figure 2, is shown in Figure 3. The electrical field strength was calculated for silicon carbide as a semiconductor material and an applied reverse voltage of 1000 V. The dimensions of the component and the dopant concentrations in the simulation were assumed to be 13 μm with a 10 μm well. (A cell is understood here as the left or right half of the illustration in FIG. 1 or 2, which are separated from one another by a vertical, dashed line in FIG. 1 and FIG. 2.) The tub depth was (including the implantation areas 5 and 6) ) 0.6 μm, the doping on the surface of the tub 4 was 6-10 16 cm "" 3 to a maximum of 4-10 18 cm "3. The thickness of the epitaxial layer 2 was 12 μm with a doping of
8-1015 cm"3.8-10 15 cm "3 .
Das Simulationsergebnis ist als dreidimensionale Grafik in Figur 3 dargestellt. Die x-Achse gibt die horizontale Ausdehnung in Figur 2 (d. h. von links nach rechts und umgekehrt) des Bauelements im Bereich zwischen 9 μm und 14 μm wieder, die y-Achse gibt die Ausdehnung des Bauelements senkrecht zur Zeichenebene in Figur 2 im Bereich zwischen 0 und 5 μm wieder und die z-Achse gibt die Feldstärke E im Bereich zwischen 0 und 300 V/μm an. Als MOS-Struktur wurde ein Aufbau zugrundegelegt, bei dem die Epitaxieschicht 2 n- dotiert und die Wanne p-dotiert ist.The simulation result is shown as a three-dimensional graphic in FIG. 3. The x-axis shows the horizontal extent in FIG. 2 (ie from left to right and vice versa) of the component in the range between 9 μm and 14 μm, the y-axis shows the extent of the component perpendicular to the drawing plane in FIG. 2 in the range between 0 and 5 μm again and the z-axis indicates the field strength E in the range between 0 and 300 V / μm. A structure was used as the MOS structure in which the epitaxial layer 2 was n-doped and the tub was p-doped.
Wie Figur 3 zu entnehmen ist, wird die Durchbruchfeldstärke von Siliciumcarbid, die typischerweise bei 200 V/μm (2,0 MV/ cm) liegt, zuerst an der Ecke der p-Wanne des MOSFET er- reicht. Die elektrische Feldstärke an den anderen Abschnitten des pn-Übergangs und an der Halbleiteroberfläche liegt bei ca. 160 V/μm. Im Oxid 7 der MOS-Struktur beträgt damit die elektrische Feldstärke 400 V/μm und liegt damit deutlich über der Feldstärke von ca. 200 V/μm, ab der die elektri- sehen Eigenschaften des Isolators 7 zu degradieren beginnen. Dieses Verhalten der Feldstärke beruht darauf, daß in den an MIS-Strukturen (MIS : Metall-Isolator-Halbleiter) der Oberfläche, wie z.B. beim vertikalen Leistungs-MOSFET, die Normalkomponente der dielektrischen Verschiebung aus dem Halbleiter stetig in den Isolator der MIS-Struktur übergeht, d.h. die elektrischen Felder im Isolator (Ei) und an der Halbleiteroberfläche (Es) über das Verhältnis der relativen Dielektrizitätskonstanten des Isolators ( εt ) und Halbleiters ( εs ) verknüpft sind durch:As can be seen in FIG. 3, the breakdown field strength of silicon carbide, which is typically 200 V / μm (2.0 MV / cm), is first reached at the corner of the p-well of the MOSFET. The electric field strength at the other sections of the pn junction and at the semiconductor surface is approx. 160 V / μm. The electrical field strength in the oxide 7 of the MOS structure is therefore 400 V / μm and is thus clearly above the field strength of approximately 200 V / μm, from which the electrical properties of the insulator 7 begin to degrade. This behavior of the field strength is based on the fact that in the MIS structures (MIS: metal insulator semiconductor) of the surface, such as, for example, in the case of the vertical power MOSFET, the normal component of the dielectric displacement from the semiconductor continuously into the insulator of the MIS structure passes, ie the electrical fields in the insulator (Ei) and on the semiconductor surface (Es) are linked by the ratio of the relative dielectric constants of the insulator (ε t ) and the semiconductor (ε s ) by:
Figure imgf000012_0001
Figure imgf000012_0001
Die maximale elektrische Feldstärke im Isolator ( E, max ) ist für Siliciumdioxid (^=3,9), den gebräuchlichsten Isolator in MIS-Strukturen, auf den Halbleitermaterialien Silicium und Siliciumcarbid typischerweise:The maximum electric field strength in the insulator (E, max ) is typically for silicon dioxide (^ = 3.9), the most common insulator in MIS structures, on the semiconductor materials silicon and silicon carbide:
Silicium ,,maχ = 60 v μm ,=ll,9; £,_max = EBD = 20 V/μm bei einer Dotierstoffkonzentration von 1014 cm"3)Silicon ,, ma χ = 60 v μm, = ll, 9; £, _ max = E BD = 20 V / μm with a dopant concentration of 10 14 cm "3 )
Silicium- £,,max = 500 V/μm =9, 66, Es^ = EBD = 200 V/μm carbid bei einer Dotierstoffkonzentration von 101S cm"3)Silicon £,, max = 500 V / μm = 9, 66, E s ^ = E BD = 200 V / μm carbide with a dopant concentration of 10 1S cm "3 )
Als Feld an der Halbleiteroberfläche wird die Durchbruch- feldstärke ( EBD ) des jeweiligen Halbleitermaterials eingesetzt, die eine Funktion der Grunddotierung des Halbleiters ist. Die angegebenen Durchbruchfeidstärken gelten für Silicium bei einer Dotierstoffkonzentration von 1014 cm-3, für Siliciumcarbid bei einer Dotierstoffkonzentration von 1016 cm"3.The breakdown field strength (E BD ) of the respective semiconductor material, which is a function of the basic doping of the semiconductor, is used as the field on the semiconductor surface. The breakdown strengths given apply to silicon with a dopant concentration of 10 14 cm -3 , for silicon carbide with a dopant concentration of 10 16 cm "3 .
Für Silicium liegt die maximale elektrische Feldstärke im Oxid der MIS-Struktur ( E!>max = 60 V/μm) weit unter derFor silicon, the maximum electric field strength in the oxide of the MIS structure (E !> Max = 60 V / μm) is far below that
Grenzfeldstärke für Siliciumdioxid, ab der die Langzeit- Stabilität des Isolators beeinträchtigt wird. Für Siliciumcarbid dagegen wird die Grenzfeldstärke von typischerweise 200 - 300 V/μm im Oxid deutlich überschritten. Die elektrischen Eigenschaften des Isolators degradieren dann im Sperrfall durch die Injektion von Ladungsträgern aus dem Siliciumcarbid in das Oxid. Limitierende Größe bei der Dimensionierung von Bauelementen mit MIS-Strukturen wird damit die maximal zulässige elektrische Feldstärke im Oxid. Das Potential von Siliciumcarbid hinsichtlich der maximal möglichen Sperrspannung kann nur sehr eingeschränkt ausgeschöpft werden.Limit field strength for silicon dioxide, from which the long-term stability of the insulator is impaired. For silicon carbide, on the other hand, the limit field strength is typically 200 - 300 V / μm significantly exceeded in the oxide. The electrical properties of the insulator then degrade in the event of blocking by the injection of charge carriers from the silicon carbide into the oxide. The maximum size for the dimensioning of components with MIS structures is the maximum permissible electric field strength in the oxide. The potential of silicon carbide with regard to the maximum possible reverse voltage can only be used to a very limited extent.
In Figur 4 ist der Verlauf der elektrischen Feldstärke in der erfindungsgemäßen Anordnung bei einer Sperrspannung von 1000 V analog zu Figur 3 dreidimensional dargestellt. Um einen direkten Vergleich zum Stand der Technik zu haben, wurden die Abmessungen des Bauelements und die zugehörigen Dotierstoffkonzentrationen identisch zu denen bei der Simulationsrechnung nach Figur 3 gewählt. Für den Inselbereich 10 wurde als Ausdehnung in die Tiefe (vertikal) 0,6 μm und ein Abstand von der Wanne 4 von 3 μm angenommen. Die horizontale Ausdehnung des Inselbereichs 10 wurde so gewählt, daß in der Projektion auf eine gedachte horizontale Linie ein Überlapp mit der Wanne 4 besteht und die Wanne 4 und der Inselbereich 10 nicht schlüssig miteinander abschließen. Als Dotierstoffkonzentration in dem Inselbereich 10 wurde 2-1017 cm"3 gewählt.FIG. 4 shows the course of the electric field strength in the arrangement according to the invention in three dimensions at a blocking voltage of 1000 V analogously to FIG. 3. In order to have a direct comparison with the prior art, the dimensions of the component and the associated dopant concentrations were chosen to be identical to those in the simulation calculation according to FIG. 3. For the island area 10, an extension into the depth (vertical) of 0.6 μm and a distance from the trough 4 of 3 μm were assumed. The horizontal extent of the island area 10 was chosen so that in the projection onto an imaginary horizontal line there is an overlap with the tub 4 and the tub 4 and the island area 10 are not conclusive with one another. 2-10 17 cm "3 was selected as the dopant concentration in the island region 10.
Wie man in Figur 4 sieht, kommt es mit dem erfindungsgemäßen Inselbereich 10 in der Epitaxieschicht 2 zu einer Verringerung des elektrischen Feldes an der Halbleiteroberfläche unter der MOS-Struktur; hier reduziert sich die elektrische Feldstärke drastisch: von 160 Vμm auf 65 V/μm. Zusätzlich entsteht oberhalb der gesamten Insel 10 ein Raum, in dem das elektrische Feld deutlich verringert ist, und die Feldspitze an der Ecke der Wanne 4 des MOSFET wird abgebaut, d.h. die Durchbruchfestigkeit des Bauelementes wird damit insgesamt erhöht. Damit schafft die Erfindung einen oberflächennahen Raum, in dem das Feld reduziert ist. Damit kann insbesondere die hohe Durchbruchfeldstärke von Siliciumcarbid auch bei Bauelementen mit MOS-Strukturen voll genutzt werden, ohne daß die Langzeitstabilität der Bauelemente durch zu hohe elektrische Feldstärken in den MOS-Strukturen beeinträchtigt wird.As can be seen in FIG. 4, the island region 10 according to the invention in the epitaxial layer 2 leads to a reduction in the electrical field on the semiconductor surface under the MOS structure; here the electrical field strength is drastically reduced: from 160 Vμm to 65 V / μm. In addition, a space is created above the entire island 10 in which the electrical field is significantly reduced, and the field tip at the corner of the trough 4 of the MOSFET is reduced, ie the breakdown resistance of the component is thus increased overall. The invention thus creates a space near the surface in which the field is reduced. In particular, the high breakdown field strength of silicon carbide can also be fully utilized in components with MOS structures without the long-term stability of the components being impaired by excessive electrical field strengths in the MOS structures.
Die Erfinder haben festgestellt, daß zwischen den Kanten der vergrabenen Insel 10 und der Wanne 4 des MOSFET in x-Rich- tung in Figur 4 keine Lücke vorhanden sein darf, da das Feld an der Halbleiteroberfläche dann sehr rasch wieder anwächst. Der Überlapp zwischen der Wanne 4 und dem Inselbereich 10 sollte also bei einem gegebenen Justierfehler von ± δ mindestens δ sein. Bei maximaler Fehljustierung liegen dann die Kanten des vergrabenen Inselbereichs 10 und der Wanne 4 des MOSFET auf einer Seite exakt übereinander, auf der anderen Seite überlappen sie um 2δ .The inventors have found that there must not be a gap between the edges of the buried island 10 and the trough 4 of the MOSFET in the x direction in FIG. 4, since the field on the semiconductor surface then grows again very quickly. The overlap between the trough 4 and the island area 10 should therefore be at least δ for a given adjustment error of ± δ. With maximum misalignment, the edges of the buried island region 10 and the trough 4 of the MOSFET then lie exactly one above the other on one side and overlap by 2δ on the other side.
Die Daten für unterschiedlichen Überlapp bei der Zelle, die der Simulation in Figur 4 zugrunde liegt, sind in Tabelle 1 in Bezug auf Leitwert und elektrische Feldstärke an der Halbleiteroberfläche bei unterschiedlichen Überlappungen des Inselbereichs 10 und der Wanne 4 zusammengestellt und mit einem MOSFET nach dem Stand der Technik (ohne Inselbereich 10) verglichen.The data for different overlaps in the cell on which the simulation in FIG. 4 is based are compiled in Table 1 with regard to the conductance and electrical field strength on the semiconductor surface with different overlaps of the island region 10 and the trough 4 and with a MOSFET according to the prior art the technology (without island area 10) compared.
In der Tabelle 1 bedeuten Werte für den Überlapp, die kleiner als 0 sind, daß zwischen den Kanten des Inselbereichs 10 und der Wanne 4 des MOSFET eine Lücke besteht. In Table 1, values for the overlap that are smaller than 0 mean that there is a gap between the edges of the island region 10 and the well 4 of the MOSFET.
Figure imgf000015_0001
Figure imgf000015_0001
Tabelle 1Table 1
Der Einbau des ideal justierten Inselbereichs 10 mit einem Überlapp von δ = 2 μm reduziert nach Tabelle 1 den Leitwert des berechneten vertikalen MOSFET um 31% gegenüber dem Leitwert des MOSFET ohne Inselbereich 10 (erste Zeile in der Tabelle) . Ist der Inselbereich 10 um δ fehljustiert, wird die Stromverteilung asymmetrisch: auf einer Seite verringert sich der Leitwert um 41% gegenüber dem Leitwert des MOSFET ohne Inselbereich 10, auf der anderen Seite um 19%, im Mittel also ebenfalls 31% gegenüber dem Leitwert des MOSFET ohne Inselbereich 10. Die Sperrfähigkeit aber bleibt auf beiden Seiten erhalten. Die bei maximaler Fehljustierung auftretende Feldstärke im Gate-Oxid beträgt in diesem Beispiel 160 V/μm. Im Gegensatz zu der Anordnung nach dem Stand der Technik ohne Inselbereich ist dieser MOSFET bis zu einer Sperrspannung von 1000 V einsetzbar, ohne daß das Gate-Oxid 7 degradiert. Damit ermöglicht die erfindungsgemäße Insel 10 in MOS-Bauelementen die volle Ausschöpfung der Durchbruchfeldstärke des verwendeten Halbleitermaterials . Neben der Anordnung des Inselbereichs 10 und der Wanne 4 in horizontaler Richtung ist die Ausrichtung in vertikaler Richtung maßgeblich für die Eigenschaften des Bauelements. Die vertikale Anordnung des vergrabenen Inselbereichs 10 wird vorzugsweise gemäß den Erfordernissen für den Durchlaßfall dimensioniert. Der vertikale Abstand zwischen dem vergrabenen Inselbereich 10 und der Wanne 4 des MOSFET muß groß genug sein, um eine nennenswerte Behinderung des Stromflusses durch den JFET-Effekt im Kanal zwischen Wanne 4 und Inselbereich 10 zu vermeiden. Bei der in Figur 1 dargestellten Ausführungsform mit den oben genannten Daten, die der Berechnung zu Figur 4 zugrunde liegen, ist dies für einen Abstand von 3 μm gewährleistet. Aus demselben Grund darf der für den Sperrfall wichtige Überlapp der beiden Gebiete in lateraler Richtung nicht zu groß werden.According to Table 1, the installation of the ideally adjusted island area 10 with an overlap of δ = 2 μm reduces the conductance of the calculated vertical MOSFET by 31% compared to the conductance of the MOSFET without island area 10 (first line in the table). If the island area 10 is misaligned by δ, the current distribution becomes asymmetrical: on one side the conductance decreases by 41% compared to the conductance of the MOSFET without island area 10, on the other side by 19%, i.e. on average also 31% compared to the conductance of the MOSFET without island area 10. The blocking ability remains on both sides. The field strength occurring in the gate oxide at maximum misalignment is 160 V / μm in this example. In contrast to the arrangement according to the prior art without an island region, this MOSFET can be used up to a reverse voltage of 1000 V without the gate oxide 7 being degraded. The island 10 according to the invention in MOS components thus enables the breakdown field strength of the semiconductor material used to be fully utilized. In addition to the arrangement of the island region 10 and the trough 4 in the horizontal direction, the orientation in the vertical direction is decisive for the properties of the component. The vertical arrangement of the buried island region 10 is preferably dimensioned according to the requirements for the passage case. The vertical distance between the buried island region 10 and the well 4 of the MOSFET must be large enough to avoid any significant impediment to the current flow due to the JFET effect in the channel between the well 4 and the island region 10. In the embodiment shown in FIG. 1 with the above-mentioned data on which the calculation for FIG. 4 is based, this is guaranteed for a distance of 3 μm. For the same reason, the overlap of the two areas in the lateral direction, which is important for the blocking situation, must not become too large.
Neben der oben beschriebenen Anwendung der vergrabenen Insel 10 beim vertikalen Leistungs-MOSFET kann diese Struktur in all den Fällen eingesetzt werden, in denen Teile eines Bau- elementes vor hohen elektrischen Feldstärken geschützt werden sollen bzw. Halbleitergebiete mit verminderter elektrischer Feldstärke erforderlich sind. Ein Beispiel für eine weitere Anwendung der Erfindung ist der in Figur 5 gezeigte U-MOSFET, bei dem ebenfalls die maximale Feldstärke im Isolator 7 der MIS-Struktur am Boden und an den Kanten der U-Gräben überschritten wird.In addition to the use of the buried island 10 described above for vertical power MOSFETs, this structure can be used in all cases in which parts of a component are to be protected against high electrical field strengths or semiconductor regions with a reduced electrical field strength are required. An example of a further application of the invention is the U-MOSFET shown in FIG. 5, in which the maximum field strength in the insulator 7 of the MIS structure at the bottom and at the edges of the U-trenches is likewise exceeded.
Der U-MOSFET in Figur 5 umfaßt wie der in Figur 1 gezeigte erfindungsgemäße vertikale MOSFET auf einem Halbleiter- substrat 1 eine erste Epitaxieschicht 2 von einem ersten Leitungstyp. Auf dieser ist eine zweite Epitaxieschicht 12 von einem zweiten Leitungstyp und darauf wiederum eine dritte Schicht 11 von dem ersten Leitungstyp angeordnet. Die dritte Schicht 11 kann ebenfalls als Epitaxieschicht auf der zweiten Epitaxieschicht 12 abgeschieden werden oder durch Implantation in der zweiten Epitaxieschicht 12 hergestellt werden. Auf der Schicht 11 ist der Source-Kontakt 8 an- geordnet. Das Gate 3, das durch eine Isolatorschicht 7 von der ersten Epitaxieschicht 2 und den Schichten 11 und 12 getrennt ist, ist in die Schichten 11 und 12 geätzt. Im übrigen sind gleiche Elemente wie in Figur 1 oder 2 mit denselben Bezugszeichen versehen.Like the vertical MOSFET according to the invention shown in FIG. 1, the U-MOSFET in FIG. 5 comprises a first epitaxial layer 2 of a first conductivity type on a semiconductor substrate 1. A second epitaxial layer 12 of a second conductivity type and a third layer 11 of the first conductivity type in turn are arranged on this. The third layer 11 can also be deposited as an epitaxial layer on the second epitaxial layer 12 or can be produced by implantation in the second epitaxial layer 12. The source contact 8 is connected to the layer 11. orderly. The gate 3, which is separated from the first epitaxial layer 2 and the layers 11 and 12 by an insulator layer 7, is etched into the layers 11 and 12. Otherwise, the same elements as in Figure 1 or 2 are provided with the same reference numerals.
Erfindungsgemäß wird bei einem U-MOSFET in der ersten Epitaxieschicht 2 eine Insel 10 angeordnet. Obgleich mehrere Inseln 10 angeordnet werden können in der Epitaxieschicht 2, ist nur eine davon in Figur 5 dargestellt. Durch die Inselbereiche 10 wird erreicht, daß das Feld zwischen Gate 3 und Drain 9 nicht den Isolator 7 belastet und diesen altern läßt, sondern der Isolator 7 abgeschirmt und weniger belastet wird.According to the invention, an island 10 is arranged in the first epitaxial layer 2 in a U-MOSFET. Although several islands 10 can be arranged in the epitaxial layer 2, only one of them is shown in FIG. 5. The island regions 10 ensure that the field between gate 3 and drain 9 does not stress the insulator 7 and causes it to age, but rather insulator 7 is shielded and less stressed.
Die genaue Form der Gate-Elektrode 3 ist für die Erfindung nicht wesentlich. Sie kann daher auch statt auf einen UMSOFET auch auf einen VMOSFET etc. angewendet werden.The exact shape of the gate electrode 3 is not essential for the invention. It can therefore also be applied to a VMOSFET etc. instead of a UMSOFET.
Zusätzlich kann mit dem eingebauten Inselbereich 10, der im Sperrfall einen Teil der Abschirmung übernimmt, die Dotierung im Kanalbereich des MOSFET auf Einsatzspannung optimiert werden. Eine Ausführungsform mit einer Anordnung zur Optimierung der Dotierung ist in Figur 6 gezeigt.In addition, with the built-in island region 10, which takes over part of the shielding in the event of blocking, the doping in the channel region of the MOSFET can be optimized for the threshold voltage. An embodiment with an arrangement for optimizing the doping is shown in FIG.
Der Aufbau der Ausführungsform in Figur 6 entspricht im wesentlichen dem der Ausführungsform nach Figur 1. Zusätzlich zu der Ausführungsform nach Figur 1 weist bei der Ausführungsform nach Figur 6 die Wanne 4 einen Abschnitt 13 auf, der sich durch seine Dotierung vom Rest der Wanne 4 unterscheidet. Die maximale Dotierstoffkonzentration in der Tiefe der Wanne 4 wird in diesem Abschnitt 13 verringert. Als Folge wird die über die Implantationsmaske an die Halbleiteroberfläche hochgezogene Dotierstoffkonzentration ver- ringert und die Einsatzspannung des MOSFET zu kleinerenThe structure of the embodiment in FIG. 6 essentially corresponds to that of the embodiment according to FIG. 1. In addition to the embodiment according to FIG. 1, in the embodiment according to FIG. 6 the tub 4 has a section 13 which differs from the rest of the tub 4 in terms of its doping . The maximum dopant concentration in the depth of the well 4 is reduced in this section 13. As a result, the dopant concentration raised to the semiconductor surface via the implantation mask is reduced and the threshold voltage of the MOSFET is reduced
Spannungen verschoben. Die Dotierung kann soweit verringert werden, daß sich im Bereich des (nicht dargestellten) Inver- sionskanals, d. h. innerhalb der Wanne 4 zwischen dem Implantationsbereich 6 und der Epitaxieschicht 2 im wesentlichen parallel zur Oberfläche des Halbleiters verlaufend, eine homogene Dotierung ergibt. Der Wert dieser Dotierung richtet sich nach der gewünschten Einsatzspannung. Die Verfahren, mit denen der Abschnitt 13 selbstjustierend hergestellt werden kann, sind auf dem Gebiet der Halbleiterbauelemente allgemein bekannt und werden hier nicht weiter erläutert.Tensions shifted. The doping can be reduced to such an extent that in the region of the (not shown) inverter tion channel, ie running within the trough 4 between the implantation region 6 and the epitaxial layer 2 essentially parallel to the surface of the semiconductor, results in a homogeneous doping. The value of this doping depends on the desired threshold voltage. The methods with which the section 13 can be produced in a self-adjusting manner are generally known in the field of semiconductor components and are not further explained here.
Bei allen hier beschriebenen Ausführungsformen gibt es für die Konzentration des Dotierstoffes in der Insel 10 einen optimalen Bereich. Bei zu hohen Konzentrationen wird die Sperrspannung des Bauelementes verringert, weil an der Ecke der Insel 10 die Durchbruchfeldstärke überschritten wird.In all of the embodiments described here, there is an optimal range for the concentration of the dopant in the island 10. If the concentrations are too high, the blocking voltage of the component is reduced because the breakdown field strength is exceeded at the corner of the island 10.
Bei zu geringen Konzentrationen greift das elektrische Feld durch die Insel 10 hindurch an die Halbleiteroberfläche.If the concentrations are too low, the electrical field reaches through the island 10 to the semiconductor surface.
Ferner können bei allen Ausführungsformen neben einer einzelnen Insel 10 mehrere Inselbereiche 10 so angeordnet werden, daß sie zusammen ein "großmaschiges" Gitter bilden. Damit entfällt der hochgenaue Justierprozeß der Wanne 4 des MOSFET zur vergrabenen Insel 10.Furthermore, in all embodiments, in addition to a single island 10, a plurality of island regions 10 can be arranged in such a way that they form a "large-mesh" grid. The high-precision adjustment process of the well 4 of the MOSFET to the buried island 10 is thus eliminated.
Die Herstellung des beschriebenen Inselbereichs 10 kann die folgenden Schritte umfassen:The production of the island area 10 described can include the following steps:
Auf das n-Typ Siliciumcarbid-Substrat 1 wird eine Epitaxieschicht 2 gleichen Leitungstyps aufgewachsen.An epitaxial layer 2 of the same conductivity type is grown on the n-type silicon carbide substrate 1.
In diese Epitaxieschicht 2 werden die p-Inselbereiche 10 implantiert.The p-island regions 10 are implanted in this epitaxial layer 2.
Zur späteren Justierung der p-Wanne 4 können geeignete (nicht dargestellte) Justierstrukturen geätzt werden. Anschließend werden diese Strukturen mit einer weiteren n-Epitaxieschicht (die Fortsetzung der Epitaxieschicht 2) gewünschter Dicke überwachsen.Suitable adjustment structures (not shown) can be etched for later adjustment of the p-well 4. These structures are then overgrown with a further n-epitaxial layer (the continuation of the epitaxial layer 2) of the desired thickness.
Anhand der zu Beginn eingeätzten Justierstrukturen werden jetzt die p-Wannen für den MOSFET justiert, so daß die gewünschte Überlappung von Wanne 4 und Insel 10 erreicht wird.Using the adjustment structures etched at the beginning, the p-wells for the MOSFET are now adjusted so that the desired overlap of well 4 and island 10 is achieved.
Alle weiteren Prozeßschritte sind die gleichen wie bei dem Stand der Technik.All other process steps are the same as in the prior art.
Mit dessen Herstellungsschritten kann erfindungsgemäß ein MOSFET-Bauelement hergestellt werden, dessen Durchbruch- festigkeit sehr hoch ist und bei dem insbesondere dieWith its manufacturing steps, a MOSFET component can be produced according to the invention, the breakdown strength of which is very high and in which the
Isolatorschicht keiner hohen Dauerbelastung ausgesetzt ist und die damit eine höhere mittlere Lebensdauer hat. Insulator layer is not exposed to a high permanent load and thus has a longer average life.

Claims

Patentansprüche claims
1. Durch Feldeffekt gesteuerte vertikale Halbleiter- Isolator-Struktur mit wenigstens einem Driftgebiet (2) von einem ersten Leitungstyp, wenigstens einer Source-Elektrode (8) zum Injizieren von1. Field effect controlled vertical semiconductor insulator structure with at least one drift region (2) of a first conductivity type, at least one source electrode (8) for injecting
Ladungsträgern in das Driftgebiet (2), wenigstens einer Drain-Elektrode (9) zum Absaugen derCharge carriers in the drift area (2), at least one drain electrode (9) for suctioning the
Ladungsträger aus dem Driftgebiet (2) , wenigstens einer Gate-Elektrode (8) zum Steuern des Stromes der Ladungsträger zwischen wenigstens einer der Source- (8) und der Drain-Elektroden (9), d a d u r c h g e k e n n z e i c h n e t , daß in demCharge carriers from the drift region (2), at least one gate electrode (8) for controlling the current of the charge carriers between at least one of the source (8) and the drain electrodes (9), that means that in that
Driftgebiet (2) jeweils ein Inselbereich (10) von einem zweiten Leitungstyp angeordnet ist.An island region (10) of a second conduction type is arranged in each case in the drift region (2).
2. Durch Feldeffekt gesteuerte vertikale Halbleiter-Isolator-Struktur nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, daß die Inselbereiche (10) so an- geordnet sind, daß in vertikaler Richtung die Gate-Elektrode (8) von der Drain-Elektrode (9) abgeschirmt ist.2. Vertical semiconductor insulator structure controlled by field effect according to claim 1, characterized in that the island regions (10) are arranged in such a way that the gate electrode (8) is shielded from the drain electrode (9) in the vertical direction .
3. Durch Feldeffekt gesteuerte vertikale Halbleiter-Isolator-Struktur nach Anspruch 2, d a d u r c h g e - k e n n z e i c h n e t, daß die Inselbereiche (10) so dimensioniert sind, daß sie in symmetrischer Position in bezug auf die Gate-Elektrode (3) von der Drain-Elektrode (9) aus gesehen die Wanne (4) um das Zweifache des Betrags einer maximalen Justierungenauigkeit (δ) überlappen.3. Vertical semiconductor insulator structure controlled by field effect according to claim 2, characterized in that the island regions (10) are dimensioned such that they are in a symmetrical position with respect to the gate electrode (3) from the drain electrode ( 9) seen from the overlap the trough (4) by twice the amount of a maximum adjustment inaccuracy (δ).
4. Durch Feldeffekt gesteuerte vertikale Halbleiter-Isolator-Struktur nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß die Wanne (4) eine höhere Dotierstoffkonzentration an der Halbleiterober- fläche und eine niedrigere Dotierstoffkonzentration auf der der Halbleiteroberfläche gegenüberliegenden Seite aufweist. 4. Vertical semiconductor insulator structure controlled by field effect according to one of the preceding claims, characterized in that the trough (4) has a higher dopant concentration on the semiconductor surface and a lower dopant concentration on the side opposite the semiconductor surface.
5. Durch Feldeffekt gesteuerte vertikale Halbleiter-Isolator-Struktur nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß die Gate- Elektrode (3) als Graben-Elektrode in dem Driftgebiet (2) ausgeführt ist.5. Field effect controlled vertical semiconductor insulator structure according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the gate electrode (3) is designed as a trench electrode in the drift region (2).
6. Durch Feldeffekt gesteuerte vertikale Halbleiter-Isolator-Struktur nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß das Drift- gebiet (2) aus SiC besteht.6. Vertical semiconductor insulator structure controlled by a field effect according to one of the preceding claims, that the drift region (2) consists of SiC.
7. Durch Feldeffekt gesteuerte vertikale Halbleiter-Isolator-Struktur nach Anspruch 1, d a d u r c h g e - k e n n z e i c h n et, daß die Inselbereiche (10) meh- rerer Zellen so angeordnet sind, daß sie eine regelmäßige Struktur bilden.7. Vertical semiconductor insulator structure controlled by field effect according to claim 1, d a d u r c h g e - k e n n z e i c h n et that the island regions (10) of several cells are arranged so that they form a regular structure.
8. Verfahren zum Herstellen einer durch Feldeffekt gesteuerten vertikalen Halbleiter-Isolator-Struktur, das die Schrit- te umfaßt:8. A method of fabricating a field effect controlled vertical semiconductor insulator structure comprising the steps of:
Aufbringen einer Halbleiterschicht (2), die als Driftstrecke für Ladungsträger dient und die von einem ersten Leitungstyp ist, auf ein Halbleitersubstrat (1),Applying a semiconductor layer (2), which serves as a drift path for charge carriers and which is of a first conductivity type, to a semiconductor substrate (1),
Anordnen wenigstens eines Wannenbereichs (4) in der Halb- leiterschicht (2)Arranging at least one well region (4) in the semiconductor layer (2)
Aufbringen einer Isolatorschicht (7) auf der Oberfläche derApplication of an insulator layer (7) on the surface of the
Halbleiterschicht (2) ,Semiconductor layer (2),
Erzeugen einer von der Halbleiterschicht (2) durch dieGenerate one of the semiconductor layer (2) through the
Isolatorschicht (7) getrennten Gate-Elektrode (3) , einer mit der Halbleiterschicht verbundenen Source-Elektrode (8) und einer Drain-Elektrode (9), d a d u r c h g e k e n n z e i c h n e t , daß das Aufbringen der Halbleiterschicht (2) umfaßt:Insulator layer (7) separate gate electrode (3), a source electrode (8) connected to the semiconductor layer and a drain electrode (9), so that the application of the semiconductor layer (2) comprises:
Aufwachsen einer ersten Epitaxieschicht eines ersten Lei- tungstyps auf das Halbleitersubstrat (1),Growing a first epitaxial layer of a first line type on the semiconductor substrate (1),
Anordnen von Inselbereichen (10) eines zweiten Leitungstyps in oder auf der ersten Epitaxieschicht, Aufwachsen einer zweiten Epitaxieschicht des ersten Leitungstyps auf der ersten Epitaxieschicht mit den Inselbereichen.Arranging island regions (10) of a second conduction type in or on the first epitaxial layer, Growing a second epitaxial layer of the first conductivity type on the first epitaxial layer with the island regions.
9. Verfahren nach Anspruch 8, d a d u r c h g e k e n n z e i c h n e t, daß die Inselbereiche mehrerer Zellen in regelmäßigen Abständen voneinander auf der ersten Epitaxieschicht angeordnet werden.9. The method according to claim 8, so that the island regions of a plurality of cells are arranged at regular intervals from one another on the first epitaxial layer.
10. Verfahren nach Anspruch 8 oder 9, d a d u r c h g e k e n n z e i c h n e t, daß nach dem Aufwachsen der ersten Epitaxieschicht Justierstrukturen geätzt werden, die als Justierhilfen für die Anordnung der Wanne (4) dienen. 10. The method of claim 8 or 9, d a d u r c h g e k e n e z e i c h n e t that after the growth of the first epitaxial layer adjustment structures are etched, which serve as adjustment aids for the arrangement of the tub (4).
PCT/DE1999/000118 1998-01-29 1999-01-19 Semiconductor insulating structure with reduced surface field strength and method for the production of the said structure WO1999039388A1 (en)

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DE19803424A DE19803424C1 (en) 1998-01-29 1998-01-29 Semiconductor insulator structure with reduced field strength at surface, esp. for component technology silicon carbide

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