JPS63186475A - Conductivity modulation type mosfet - Google Patents
Conductivity modulation type mosfetInfo
- Publication number
- JPS63186475A JPS63186475A JP62017372A JP1737287A JPS63186475A JP S63186475 A JPS63186475 A JP S63186475A JP 62017372 A JP62017372 A JP 62017372A JP 1737287 A JP1737287 A JP 1737287A JP S63186475 A JPS63186475 A JP S63186475A
- Authority
- JP
- Japan
- Prior art keywords
- base region
- conductivity type
- region
- conductivity
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000969 carrier Substances 0.000 claims abstract description 17
- 230000001939 inductive effect Effects 0.000 claims abstract description 4
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000002513 implantation Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 9
- 230000003071 parasitic effect Effects 0.000 description 9
- 239000012535 impurity Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は、電導度変調形ＭＯ８ＦＥＴに関し、ラッチ
アップ耐伍を改善したものである。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a conductivity modulated MO8FET with improved latch-up resistance.
（従来の技術）
従来の電導度変調形ＭＯ８ＦＥＴとしては、例えば第６
図に示すようなものがある（ＵＳＰ ４゜３６４．０
７３）。(Prior art) As a conventional conductivity modulation type MO8FET, for example,
There is something like the one shown in the figure (USP 4°364.0
73).
第６図中、２１はホール注入源となる第１導電形のｐ＋
アノード領域、２２は実質的にドレインとして作用する
低不純物濃度の第２導電形のｎベース領域であり、ｎベ
ース領域２２は、ｐ＋アノード領域２１を基板としてエ
ピタキシャル法により形成されている。In FIG. 6, 21 is p+ of the first conductivity type, which serves as a hole injection source.
The anode region 22 is a second conductivity type n base region with a low impurity concentration that essentially functions as a drain, and the n base region 22 is formed by an epitaxial method using the p + anode region 21 as a substrate.
上記のようにｐ形を第１導電形としたとき、これと反対
導電形のｎ形は第２導電形となる。When the p-type is the first conductivity type as described above, the n-type, which is the opposite conductivity type, is the second conductivity type.
ｎベース領域２２の表面側には、ＤＳＡ （Ｄｉｆｆｕ
ｓｉｏｎ ５ｅｌｆ Ａｌｉｇｎｍｅｎｔ）技術に
よってｎベース領域２３およびｎ１ソース領域２４が形
成されている。またｎ＋ソース領域２４とｎベース領ｔ
ｉｉｉ２２との間におけるｎベース領域２３上には、そ
のｎベース領域２３にチャネル２５を誘起させるゲート
電極２７がゲート酸化膜（絶縁膜〉２６を介して設けら
れている。On the surface side of the n base region 22, DSA (Diffu
An n base region 23 and an n1 source region 24 are formed using the ion 5elf alignment technique. Also, the n+ source region 24 and the n base region t
A gate electrode 27 for inducing a channel 25 in the n base region 23 is provided on the n base region 23 between the n base region iii 22 and the gate oxide film (insulating film) 26 .
２８はソース電極であり、ソース電極２８はｎ１ンース
ｆａ域２４およびｎベース領域２３に接続されている。28 is a source electrode, and the source electrode 28 is connected to the n1 base fa region 24 and the n base region 23.
２９はアノード電極である。29 is an anode electrode.
上述のように電導度変調形ＭＯ３ＦＥＴは、通常の縦形
ＭＯ８ＦＥＴに対して、そのドレイン相当領域にｐ＋ア
ノード領域２１を付加した構造とみることができる。As described above, the conductivity modulation type MO3FET can be considered to have a structure in which a p+ anode region 21 is added to the region corresponding to the drain of a normal vertical MO8FET.
そしてアノード電極２９に所要値の正電圧が加えられ、
ゲート電極２７に閾値電圧以上のゲート電圧が加えられ
ると、ゲート電極２７直下にチャネル２５が誘起されて
ｎベース領域２３の表面層が導通し、ｎ＋ソース領域２
４からチャネル２５を通ってｎベース領１ｉｉ！２２に
電子電流が流入される。一方、ｐ＋アノード領域２１か
らは、ｎベース領域２２に多量のホール（少数キャリヤ
）が注入される。Then, a required positive voltage is applied to the anode electrode 29,
When a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 27, a channel 25 is induced directly under the gate electrode 27, the surface layer of the n base region 23 becomes conductive, and the n+ source region 2
From 4 through channel 25 to n base area 1ii! An electron current flows into 22. On the other hand, a large amount of holes (minority carriers) are injected from the p + anode region 21 into the n base region 22 .
ｎベース領域２２に注入されたホールは、チャネル２５
から流れ込んだ電子と再結合しながら一部はｎベース領
域２３へ流れ込み、ソース電極２８へ抜ける。しかしｎ
ベース領域２２には、なお多量のキャリヤ蓄積が生じて
主導度変調が起き、動作時のオン抵抗が低減する。The holes injected into the n-base region 22 form the channel 25.
Some of the electrons flow into the n base region 23 while recombining with the electrons that flowed in from the source electrode 28 . But n
A large amount of carrier accumulation still occurs in the base region 22, leading to intensity modulation and reducing the on-resistance during operation.
このように電導度変調形ＭＯ８ＦＥＴは、動作時のオン
抵抗が非常に低くなり、且つ高耐圧であるという特性を
有している。In this way, the conductivity modulation type MO8FET has the characteristics of extremely low on-resistance during operation and high breakdown voltage.
しかるに電導度変調形ＭＯ８Ｆ Ｅ Ｔは、前述のよう
にｐ＋アノード領域２１を有し、このｐ＋アノード領域
２１上にｎベース領域２２が存在し、ｎベース領域２２
にはｎベース領域２３およびｎ“ソース領域２４が形成
されている。However, the conductivity modulation type MO8FET has the p+ anode region 21 as described above, the n base region 22 exists on the p+ anode region 21, and the n base region 22
An n base region 23 and an n'' source region 24 are formed in.
このような構造から、その内部には、第７図の等何回路
に示すように、ｐｎｐ形のトランジスタＱ１およびｎｐ
ｎ形のトランジスタＱ２が寄生的に生じ、この両トラン
ジスタＱ１、Ｑ２の結合により、ｐｎｐｎサイリスタが
形成されている。第７図中、Ｒｂはｎｐｎ形のトランジ
スタＱ２のベース抵抗で、ρベース領［２３の部分に生
じる。Because of this structure, there are a pnp transistor Q1 and an np transistor inside, as shown in the circuit shown in FIG.
An n-type transistor Q2 is generated parasitically, and a pnpn thyristor is formed by the combination of both transistors Q1 and Q2. In FIG. 7, Rb is the base resistance of the npn transistor Q2, which occurs in the ρ base region [23].
このため、トランジスタＱ１のエミッタに相当するｐ＋
アノード領域２１から注入されたホールのうち、そのコ
レクタに相当するｎベース領域２３に達する電流をｌｂ
とすると、ｎベース領域２３にＩｂ−Ｒｂなる電圧降下
が生じ、この電圧降下がトランジスタＱ２のベース閾値
電圧（−〇。Therefore, p+ corresponding to the emitter of transistor Q1
Of the holes injected from the anode region 21, the current reaching the n base region 23 corresponding to the collector is lb.
Then, a voltage drop of Ib-Rb occurs in the n base region 23, and this voltage drop is the base threshold voltage of the transistor Q2 (-〇.
６Ｖ）を超えると、当該トランジスタＱ２がオン状態に
転じて、そのコレクタ電流、即ち他のトランジスタＱ１
のベース電流の増加を引き起す。この結果、トランジス
タＱ１のコレクタ電流であるＩｂが増加してトランジス
タＱ２のベース電流が増加するという正帰還ループがで
きてラッチアップ現象が発生する。ラッチアップ現象が
発生すると、サイリスタ動作が生じるので電源を一旦切
らない限り元の状態に復帰しない。6V), the transistor Q2 turns on and its collector current, that is, the other transistor Q1
causes an increase in the base current of As a result, a positive feedback loop is created in which the collector current Ib of the transistor Q1 increases and the base current of the transistor Q2 increases, resulting in a latch-up phenomenon. When a latch-up phenomenon occurs, thyristor operation occurs and the original state cannot be restored unless the power is turned off.
したがってラッチアップ現象の発生を防止するためには
、ｎベース領域２３部分の抵抗Ｒｂおよびこれに流れる
電流１ｂをできる限り小さくすることが重要となる。Therefore, in order to prevent the latch-up phenomenon from occurring, it is important to make the resistance Rb of the n-base region 23 portion and the current 1b flowing therein as small as possible.
このため、従来の電導度変調形ＭＯ８ＦＥＴにあっては
、ｎベース領域２２の厚さを厚くして、ｐ＋アノード領
域２１からそのｎベース領域２２に注入されるホールの
大部分が再結合されるようにし、またｐ＋アノード領域
２１とｎベース領域２２とで構成される寄生トランジス
タＱ１のエミッタ注入効率を落すことが行なわれていた
。For this reason, in the conventional conductivity modulation type MO8FET, the thickness of the n base region 22 is increased so that most of the holes injected from the p+ anode region 21 into the n base region 22 are recombined. In addition, the emitter injection efficiency of the parasitic transistor Q1 composed of the p+ anode region 21 and the n base region 22 has been reduced.
（発明が解決しようとする問題点）
しかしながら、ｎベース領域２２の厚さを厚くしてｐ＋
アノード領域２１から注入されるホールの大部分を再結
合させるようにすると、［）ベース領域２２は低不純物
濃度領域であるため動作時のオン抵抗を十分に低くする
ことができないという問題点があった。(Problem to be Solved by the Invention) However, by increasing the thickness of the n base region 22, the p+
If most of the holes injected from the anode region 21 are recombined, there is a problem that the on-resistance during operation cannot be made sufficiently low because the base region 22 is a low impurity concentration region. Ta.
この発明は、このような従来の問題点に着目してなされ
たもので、ラッチアップ耐量が高く且つ動作時のオン抵
抗を十分に低くすることのできる電導度変調形ＭＯ８Ｆ
ＥＴを提供することを目的とする。The present invention was made by focusing on these conventional problems, and is a conductivity modulated MO8F that has high latch-up resistance and can sufficiently reduce on-resistance during operation.
The purpose is to provide ET.
［発明の構成］
（問題点を解決するための手段）
この発明は上記目的を達成するために、第１導電形の高
濃度領域と、該ａ濃度領域上に形成され当該高濃度領域
からの少数キャリヤ注入により電導度が変調されるとと
もに実質的にドレインとして作用する第２導電形のベー
ス領域と、該第２導電形のベース領域内に埋込まれ当該
第２導電形のベース領域の電導度を変調させた少数キャ
リヤを捕集する第１導電形のグリッドコレクタと、前記
第２導電形のベース領域の表面側に形成された第１導電
形のベース領域と、該第１導電形のベース領域の表面側
に形成された第２導電形のソース領域と、該ソース領域
と前記第２導電形のベース領域との間の前記第１導電形
のベース領域上にゲート絶縁膜を介して設けられ当該第
１導電形のベース領域にチャネルを誘起させるゲート電
極とを有することを要旨とする。[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention includes a high concentration region of the first conductivity type, and a high concentration region formed on the a concentration region and from which the high concentration region is formed. A base region of a second conductivity type whose conductivity is modulated by minority carrier injection and which substantially acts as a drain; and a base region of the second conductivity type embedded in the base region of the second conductivity type. a grid collector of a first conductivity type that collects minority carriers whose concentration is modulated; a base region of a first conductivity type formed on the surface side of the base region of the second conductivity type; A source region of a second conductivity type formed on the surface side of the base region, and a gate insulating film formed on the base region of the first conductivity type between the source region and the base region of the second conductivity type. The gist of the present invention is to include a gate electrode which is provided and which induces a channel in the base region of the first conductivity type.
（作用）
第１導電形の高濃度領域から第２導電形のベース領域に
注入されて、この第２導電形のベース領域に電導度変調
を生じさせた少数キャリヤの大部分は、第１導電形のグ
リッドコレクタに捕集されて、このグリッドコレクタ内
で多数キャリヤの一部として吸収潰滅する。したがって
第１導電形のベース領域への少数キャリヤの流入が極め
て少なくなってラッチアップ現象の発生が防止される。(Function) Most of the minority carriers that are injected from the high concentration region of the first conductivity type into the base region of the second conductivity type and cause conductivity modulation in the base region of the second conductivity type are It is collected in a shaped grid collector, where it is absorbed and destroyed as part of the majority carriers. Therefore, the flow of minority carriers into the base region of the first conductivity type is extremely reduced, and the latch-up phenomenon is prevented from occurring.
このように少数キャリヤはグリッドコレクタの作用で吸
収され消滅するので、第２導電形のベース領域はその厚
さを耐圧を所定値に保持し得る範囲で所定の厚さまで薄
くすることができ、オン抵抗の低減が図られる。In this way, the minority carriers are absorbed and disappear by the action of the grid collector, so the thickness of the base region of the second conductivity type can be reduced to a predetermined thickness within a range that can maintain the withstand voltage at a predetermined value. The resistance is reduced.
（実施例） 以下、この発明の実施例を図面に基づいて説明する。(Example) Embodiments of the present invention will be described below based on the drawings.
第１図ないし第３図は、この発明の一実施例を示す図で
ある。1 to 3 are diagrams showing one embodiment of the present invention.
まず構成を説明すると、第１図中、１はホール注入源と
なる高濃度領域としてのｐ＋アノード領域であり、ｐ＋
アノード領減滅１上は、当該ρ“アノード領域１からの
ホール（少数キャリヤ）注入により電導度変調が起きる
とともに、実質的にドレインとして作用する低不純物ａ
度のｎベース領域２が形成されている。First, to explain the structure, in FIG.
In the anode region depletion 1, conductivity modulation occurs due to the injection of holes (minority carriers) from the anode region 1, and the low impurity a, which essentially acts as a drain,
An n-base region 2 is formed.
そして、このｎベース領域２内のやや上側寄りに、当該
ｎベース領域２に電導度変調を生じさせたホールを捕集
して、これをほぼ消滅させるｐ＋グリッドコレクタ６が
埋込まれている。ｐ“グリッドコレクタ６は、後述する
ｐベース領域へのホールの流入を阻止することを目的と
するものであるので、この目的を効果的に生じさせるた
めに、そのｐベース領域の下方側の所定の部分にそれぞ
れ部分的に形成された高不純物濃度のｐ＋拡散層で構成
されている。A p+ grid collector 6 is embedded slightly above the n-base region 2 to collect holes that cause conductivity modulation in the n-base region 2 and substantially eliminate them. Since the purpose of the p" grid collector 6 is to prevent holes from flowing into the p base region, which will be described later, in order to effectively achieve this purpose, It is composed of a p+ diffusion layer with a high impurity concentration partially formed in each portion.
ｎベース領域２内へのｐ＋グリッドコレクタ６の埋込み
は、例えば次のようにして形成される。The p+ grid collector 6 is embedded in the n base region 2, for example, in the following manner.
即ち、まずρ“アノード領域１を基板として、エピタキ
シャル法により第１ｎベース領域３が所要の厚さで、所
要の低不純物濃度となるように形成される。次いで第１
ｎベース領域３の表面に、所定パターンのｐ＋グリッド
コレクタ６が高不純物濃度となるように拡散により形成
される。このようにしてｐ＋グリッドコレクタ６が形成
された第１ｎベース領域３を備えたエピタキシャルシリ
コンウェー八と、第２ｎベース領ｔ４４となる低不純物
濃度のシリコンウェーハとが、公知のシリコンウェーへ
の直接接合法（特開昭６０−５１７００号公報）により
張り合わせ界面５の部分で直接接合される。この直接接
合の際、第１ｎベース領域３の表面に予め拡散形成され
た所定パターンのｐ＋グリッドコレクタ６は、ｐベース
領域の直下となるように位置付けされる。ｐ＋アノード
領域１から注入されてｎベース領域２に電導度変調を生
じさせたホールは、ｐ＋グリッドコレクタ６で捕集され
てほぼ消滅するので、ｎベース領域２の厚さは、ホール
を再結合させる目的で格別厚くする必要はなく、第１ｎ
ベース領域３と第２ｎべ一ス領賊４との張り合わせで形
成されたｎベース領域２の全体の厚さは、可能な範囲で
所定の厚さまで薄くされる。That is, first, using the ρ'' anode region 1 as a substrate, a first n base region 3 is formed by an epitaxial method to a required thickness and a required low impurity concentration.
A p+ grid collector 6 having a predetermined pattern is formed on the surface of the n base region 3 by diffusion so as to have a high impurity concentration. The epitaxial silicon wafer having the first n-base region 3 in which the p+ grid collector 6 is formed in this way and the silicon wafer with a low impurity concentration that will become the second n-base region t44 are connected directly to the known silicon wafer. They are directly joined at the lamination interface 5 according to the method (Japanese Patent Laid-Open No. 60-51700). During this direct bonding, the p+ grid collector 6 having a predetermined pattern, which has been diffused and formed in advance on the surface of the first n-base region 3, is positioned directly below the p-base region. Holes that are injected from the p+ anode region 1 and cause conductivity modulation in the n base region 2 are collected by the p+ grid collector 6 and almost disappear, so the thickness of the n base region 2 is large enough to recombine the holes. There is no need to make it particularly thick for the purpose of
The overall thickness of the n base region 2 formed by pasting the base region 3 and the second n base region 4 together is reduced to a predetermined thickness within the possible range.
上記のようにして形成されたｐ十グリッドコレクタ埋込
みのｎベース領域２の表面側に、ｎベース領域７および
ｎ＋ソース領ｉｉｉ！８が形成され、ざらにｎ“ソース
領域８とｎベース領域２との間におけるｎベース領域７
上には、そのｎベース領域７にチャネル９を誘起させる
ためのゲート電極１２がゲート酸化！Ｉ（絶縁膜）１１
を介して設けられている。、１３はソース電極であり、
ンース電、極１３は、ｎ＋ソース領域８およびｎベース
領域７に接続されている。１４はアノード電極である。An n base region 7 and an n+ source region iii! 8 is formed, and an n base region 7 is formed roughly between the n'' source region 8 and the n base region 2.
Above, a gate electrode 12 for inducing a channel 9 in the n base region 7 is gate oxidized! I (insulating film) 11
It is provided through. , 13 is a source electrode,
The source electrode 13 is connected to the n+ source region 8 and the n base region 7. 14 is an anode electrode.
次に第２図および第３図を用いて作用を説明する。Next, the operation will be explained using FIGS. 2 and 3.
ｎベース領域２中にｐ＋グリッドコレクタ６が埋込まれ
たことにより、電Ｓ度変調形ＭＯ３ＦＥＴ中には、第２
図に示すように、前記第７図に示した奇生トランジスタ
Ｑ＋ 、Ｑ２の他に、ｐ＋アノード領域１、第１ｎベー
ス領域３およびｐ＋グリッドコレクタ６の各領域によっ
て、ｐ＋アノード領域１をエミッタとしたｐｎｐ形の寄
生バイポーラトランジスタＱ３が形成されている。この
奇生バイポーラトランジスタＱ３のコレクタ耐圧は、低
不純物１１１度の第１ｎベース領域３の厚さでほぼ決め
られる。By embedding the p+ grid collector 6 in the n base region 2, the second
As shown in the figure, in addition to the parasitic transistors Q+ and Q2 shown in FIG. A pnp type parasitic bipolar transistor Q3 is formed. The collector breakdown voltage of this strange bipolar transistor Q3 is approximately determined by the thickness of the first n base region 3 with a low impurity concentration of 111 degrees.
そして、アノード電極１４に所要値の正電圧が加えられ
、ゲート電極１２に閾値電圧以上のゲート電圧が加えら
れると、ゲート電極１２直下のｎベース領域７の表面層
が反転してチャネル９が誘起され、ｎ＋ソース領域８と
ドレインとして作用するｎベース領域２とが導通する。When a required positive voltage is applied to the anode electrode 14 and a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 12, the surface layer of the n-base region 7 directly under the gate electrode 12 is inverted and the channel 9 is induced. As a result, the n+ source region 8 and the n base region 2 acting as a drain are electrically connected.
一方、ｐ１アノード領域１からｎベース領域２に多量の
ホール（少数キセリャ）が注入され、ｎベース領域２に
電導度変調が起き、このｎベース領域２の部分の抵抗が
十分に低くなる。そして電゛Ｓ度変調を生じさせたホー
ルはｎベース領ＩｉＩ！２内を拡散してｐ＋グリッドコ
レクタ６の埋込領域に達し、このｐ′″グリッドコレク
タ６に捕集されて当該ｐ＋グリッドコレクタ６内で多数
キャリヤの一部として吸収される。したがってｐ＋グリ
ッドコレクタ６の部分でホールの殆んどが捕集されて消
滅し、またｐ＋グリッドコレクタ６を形成しているｐ＋
拡散層は、特にｎベース領域７の下方に配置されている
ので、ｐベース領ｖＡ７へのホールの流入が顕著に少な
くなる。On the other hand, a large amount of holes (minority number of holes) are injected from the p1 anode region 1 into the n base region 2, conductivity modulation occurs in the n base region 2, and the resistance of this portion of the n base region 2 becomes sufficiently low. And the hole that caused the S degree modulation is in the n-base region IiI! 2, reaches the embedded region of the p+ grid collector 6, is collected by this p''' grid collector 6, and is absorbed as part of the majority carriers within the p+ grid collector 6. Therefore, the p+ grid collector Most of the holes are collected and disappear in the part 6, and the p+ which forms the p+ grid collector 6
Since the diffusion layer is particularly arranged below the n-base region 7, the inflow of holes into the p-base region vA7 is significantly reduced.
この結果、当該電導度変調形ＭＯ８ＦＥＴは、出力電流
（ドレイン電流）があるレベル以上となっても、寄生ト
ランジスタＱ２のベース電位の上昇が抑制され、その奇
生トランジスタＱ２のオン動作、ひいてはサイリスタ動
作が防止されてラッチアップに対する耐量が向上される
。As a result, in the conductivity modulated MO8FET, even if the output current (drain current) exceeds a certain level, the rise in the base potential of the parasitic transistor Q2 is suppressed, and the on-operation of the parasitic transistor Q2 and the thyristor operation are suppressed. This prevents latch-up and improves resistance to latch-up.
このように、この実施例の電導度変調形ＭＯ８ＦＥＴは
、奇生トランジスタＱ１、Ｑ２側のオン動作、云い換え
れば、サイリスタ動作が抑制されるので、その耐圧は、
前述した他の寄生トランジスタＱ３のコレクタ耐圧で規
定される。そしてこのコレクタ耐圧は、第１ｎベース領
域３の厚さでほぼ決まり、且つこの厚さはオン抵抗にも
関係するので、この第１ｎベース領域３の厚さを所定の
耐圧が得られる範囲で薄く設定することにより、所定の
耐圧で且つ低オン抵抗を有する優れた特性のｆｆｌＩＪ
度変調形ＭＯ３ＦＥＴが実現される。In this way, in the conductivity modulated MO8FET of this embodiment, the on operation of the parasitic transistors Q1 and Q2, in other words, the thyristor operation is suppressed, so its breakdown voltage is
It is defined by the collector breakdown voltage of the other parasitic transistor Q3 mentioned above. This collector breakdown voltage is almost determined by the thickness of the first n-base region 3, and this thickness is also related to the on-resistance, so the thickness of the first n-base region 3 is made as thin as possible within a range where a predetermined breakdown voltage can be obtained. By setting, fflIJ with excellent characteristics that has a predetermined withstand voltage and low on-resistance.
A modulated MO3FET is realized.
第３図のａ特性線は、上述のようなこの実施例に係る電
導度変調形ＭＯ８ＦＥＴの耐圧特性を示したもので、前
記第６図の従来例におけるラッチアップ領域線すと比べ
ると、電導度変調形ＭＯ８ＦＥＴの通常の使用範囲であ
る成るレベル以上のドレイン電流値において、この実施
例のものは降伏耐量が優れ、素子の安全動作領域が広げ
られている。The characteristic line a in FIG. 3 shows the withstand voltage characteristics of the conductivity modulated MO8FET according to this embodiment as described above. At a drain current value exceeding the level in which the degree modulation type MO8FET is normally used, this example has excellent breakdown strength and the safe operation area of the device is expanded.
次いで第４図および第５図には、この発明の伯の実施例
を示す。Next, FIGS. 4 and 5 show an embodiment of the present invention.
この実施例は、ｐ＋グリッドコレクタ１６のパターンを
、多数の円孔を有するようなメツシュ状のパターンとし
て、第１ｎベース領域３と第２ｎベース領域４との直接
接合法による張り合わせの際に、ｎベース領域７に対す
るグリッドコレクタ１６の位置合わせの手間が省けるよ
うにしたものである。In this embodiment, the pattern of the p+ grid collector 16 is a mesh pattern having a large number of circular holes, and when the first n base region 3 and the second n base region 4 are bonded together by the direct bonding method, the n This saves the effort of aligning the grid collector 16 with respect to the base area 7.
第５図は、ｐ＋グリッドコレクタ１６の埋込み部分の平
面図を示したもので、多数の円孔の部分に第１ｎベース
領域３が臨んでおり、この円孔の部分で、ｎ＋ソース領
ｔｉｉ！８からの電子電流がアノード電極１４側に抜け
る。FIG. 5 shows a plan view of the buried portion of the p+ grid collector 16, in which the first n base region 3 faces the portions of many circular holes, and the n+ source regions tii! The electron current from 8 passes to the anode electrode 14 side.
ラッチアップ耐量の向上およびオン抵抗の低減作用等に
ついては、前記一実施例のものとほぼ同様である。The effects of improving latch-up resistance and reducing on-resistance are substantially the same as those of the first embodiment.
なお、上述の各実施例ではｎチャネルの電導度変調形Ｍ
Ｏ８ＦＥＴについて述べてきたが、ｎチャネルの電導度
変調形ＭＯ３ＦＥＴにも同様に適用できる。このとき高
濃度領域はカソードとなる。Note that in each of the above embodiments, the n-channel conductivity modulation type M
Although the description has been made regarding the O8FET, it can be similarly applied to an n-channel conductivity modulation type MO3FET. At this time, the high concentration region becomes a cathode.
［発明の効果コ
以上説明したように、この発明によれば第１導電形の高
濃度領域上に、この高濃度領域からの少数キャリヤ注入
によって電導度が変調されるとともに実質的にドレイン
として作用する第２導電形のベース領域を形成し、この
第２導電形のベース領域内に当該第２導電形のベース領
域に電導度変調を生じさせた少数キャリヤを捕集する第
１導電形のグリッドコレクタを埋込み、第２導電形のベ
ース領域の表面側には第１導電形のベース領域を形成し
、さらにこの第１導電形のベース領域の表面側に第２導
電形のソース領域を形成したので、第２導電形のベース
領域に電導度変調を生じさせた少数キャリヤの大部分は
、第１導電形のグリッドコレクタに捕集されて、そのグ
リッドコレクタ内で多数キャリヤの一部として吸収され
消滅する。[Effects of the Invention] As explained above, according to the present invention, minority carriers are injected into the high concentration region of the first conductivity type from the high concentration region, thereby modulating the conductivity and substantially acting as a drain. a grid of a first conductivity type that forms a base region of a second conductivity type, and collects minority carriers causing conductivity modulation in the base region of the second conductivity type; A collector is embedded, a base region of a first conductivity type is formed on the surface side of the base region of the second conductivity type, and a source region of a second conductivity type is further formed on the surface side of the base region of the first conductivity type. Therefore, most of the minority carriers that caused conductivity modulation in the base region of the second conductivity type are collected by the grid collector of the first conductivity type and absorbed as part of the majority carriers within the grid collector. Disappear.
したがって第１導電形のベース領域への少数キャリヤの
流入が顕著に減少しラッチアップ現象の発生が防止され
る。またこれとともに、第２導電形のベース領域は、耐
圧を所定値に保持し得る範囲でその厚さを薄くすること
ができるので、動作時のオン抵抗を低くすることができ
るという利点がある。Therefore, the inflow of minority carriers into the base region of the first conductivity type is significantly reduced, and the latch-up phenomenon is prevented from occurring. In addition, since the thickness of the base region of the second conductivity type can be reduced within a range that allows the breakdown voltage to be maintained at a predetermined value, there is an advantage that the on-resistance during operation can be reduced.
第１図ないし第３図はこの発明に係る電導度変調形ＭＯ
８ＦＥＴの一実施例を示すもので、第１図は縦断面図、
第２図は寄生トランジスタを含む等価回路を示す回路図
、第３図は耐圧特性を従来例と比較して示す特性図、第
４図はこの発明の他の実施例を示ず縦断面図、第５図は
第４図のＶ−Ｖ線断面図、第６図は従来の電導度変調形
ＭＯ８ＦＥＴを示す縦断面図、第７図は同上従来例にお
ける寄生トランジスタを含む等価回路を示す回路図であ
る。
１：ｐ＋アノード領域（高濃度領域）、２：ｎベース領
域、
６．１６ ： ｌ）″ グリッドコレクタ、７：ｎベー
ス領域、
８：ｎ＋ソース領域、
９：チャネル、
１１：ゲート酸化膜（絶縁膜）、
１２：ゲート電極、
１３：ソース電極、
１４ニアノード電極。
代理人 弁理士 三 好 保 男アノード・ソー
ス間電圧
第３図
第４図1 to 3 show conductivity modulation type MO according to the present invention.
This shows an example of an 8FET, and FIG. 1 is a longitudinal cross-sectional view;
FIG. 2 is a circuit diagram showing an equivalent circuit including a parasitic transistor, FIG. 3 is a characteristic diagram showing breakdown voltage characteristics in comparison with a conventional example, and FIG. 4 is a longitudinal cross-sectional view showing another embodiment of the present invention. Fig. 5 is a cross-sectional view taken along the line V-V in Fig. 4, Fig. 6 is a vertical cross-sectional view showing a conventional conductivity modulated MO8FET, and Fig. 7 is a circuit diagram showing an equivalent circuit including a parasitic transistor in the conventional example. It is. 1: p+ anode region (high concentration region), 2: n base region, 6.16: l)'' grid collector, 7: n base region, 8: n+ source region, 9: channel, 11: gate oxide film (insulating 12: Gate electrode, 13: Source electrode, 14 Near anode electrode. Agent: Yasu Miyoshi, Patent Attorney Anode-source voltage Figure 3 Figure 4
Claims (1)
ャリヤ注入により電導度が変調されるとともに実質的に
ドレインとして作用する第２導電形のベース領域と、 該第２導電形のベース領域内に埋込まれ当該第２導電形
のベース領域の電導度を変調させた少数キャリヤを捕集
する第１導電形のグリッドコレクタと、 前記第２導電形のベース領域の表面側に形成された第１
導電形のベース領域と、 該第１導電形のベース領域の表面側に形成された第２導
電形のソース領域と、 該ソース領域と前記第２導電形のベース領域との間の前
記第１導電形のベース領域上にゲート絶縁膜を介して設
けられ当該第１導電形のベース領域にチャネルを誘起さ
せるゲート電極と を有することを特徴とする電導度変調形ＭＯＳＦＥＴ。[Claims] A high concentration region of a first conductivity type, and a second conductivity region formed on the high concentration region and whose conductivity is modulated by minority carrier injection from the high concentration region and substantially acting as a drain. a base region of a conductivity type; a grid collector of a first conductivity type that is embedded in the base region of the second conductivity type and collects minority carriers that modulate the conductivity of the base region of the second conductivity type; a first conductivity type formed on the surface side of the base region of the second conductivity type;
a base region of a conductivity type; a source region of a second conductivity type formed on the surface side of the base region of the first conductivity type; and a base region of the first conductivity type between the source region and the base region of the second conductivity type. A conductivity modulation type MOSFET characterized by having a gate electrode provided on a base region of a conductivity type via a gate insulating film and inducing a channel in the base region of the first conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62017372A JPS63186475A (en) | 1987-01-29 | 1987-01-29 | Conductivity modulation type mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62017372A JPS63186475A (en) | 1987-01-29 | 1987-01-29 | Conductivity modulation type mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63186475A true JPS63186475A (en) | 1988-08-02 |
Family
ID=11942189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62017372A Pending JPS63186475A (en) | 1987-01-29 | 1987-01-29 | Conductivity modulation type mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63186475A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5519245A (en) * | 1989-08-31 | 1996-05-21 | Nippondenso Co., Ltd. | Insulated gate bipolar transistor with reverse conducting current |
| EP0869558A2 (en) * | 1997-03-31 | 1998-10-07 | Motorola, Inc. | Insulated gate bipolar transistor with reduced electric fields |
| WO1999039388A1 (en) * | 1998-01-29 | 1999-08-05 | Siemens Aktiengesellschaft | Semiconductor insulating structure with reduced surface field strength and method for the production of the said structure |
| WO2000002250A1 (en) * | 1998-07-07 | 2000-01-13 | Infineon Technologies Ag | Vertical semiconductor element with reduced electric surface field |
| US7265416B2 (en) * | 2002-02-23 | 2007-09-04 | Fairchild Korea Semiconductor Ltd. | High breakdown voltage low on-resistance lateral DMOS transistor |
| US9224853B2 (en) | 2007-12-26 | 2015-12-29 | Fairchild Semiconductor Corporation | Shielded gate trench FET with multiple channels |
| US9368587B2 (en) | 2001-01-30 | 2016-06-14 | Fairchild Semiconductor Corporation | Accumulation-mode field effect transistor with improved current capability |
| US9431481B2 (en) | 2008-09-19 | 2016-08-30 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
| US9595596B2 (en) | 2007-09-21 | 2017-03-14 | Fairchild Semiconductor Corporation | Superjunction structures for power devices |
-
1987
- 1987-01-29 JP JP62017372A patent/JPS63186475A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5519245A (en) * | 1989-08-31 | 1996-05-21 | Nippondenso Co., Ltd. | Insulated gate bipolar transistor with reverse conducting current |
| EP0869558A2 (en) * | 1997-03-31 | 1998-10-07 | Motorola, Inc. | Insulated gate bipolar transistor with reduced electric fields |
| EP0869558A3 (en) * | 1997-03-31 | 1999-07-21 | Motorola, Inc. | Insulated gate bipolar transistor with reduced electric fields |
| WO1999039388A1 (en) * | 1998-01-29 | 1999-08-05 | Siemens Aktiengesellschaft | Semiconductor insulating structure with reduced surface field strength and method for the production of the said structure |
| WO2000002250A1 (en) * | 1998-07-07 | 2000-01-13 | Infineon Technologies Ag | Vertical semiconductor element with reduced electric surface field |
| US6847091B2 (en) | 1998-07-07 | 2005-01-25 | Infineon Technologies Ag | Vertical semiconductor component having a reduced electrical surface field |
| US9368587B2 (en) | 2001-01-30 | 2016-06-14 | Fairchild Semiconductor Corporation | Accumulation-mode field effect transistor with improved current capability |
| US7265416B2 (en) * | 2002-02-23 | 2007-09-04 | Fairchild Korea Semiconductor Ltd. | High breakdown voltage low on-resistance lateral DMOS transistor |
| US9595596B2 (en) | 2007-09-21 | 2017-03-14 | Fairchild Semiconductor Corporation | Superjunction structures for power devices |
| US9224853B2 (en) | 2007-12-26 | 2015-12-29 | Fairchild Semiconductor Corporation | Shielded gate trench FET with multiple channels |
| US9431481B2 (en) | 2008-09-19 | 2016-08-30 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
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