WO1996013055A2 - Plastic encapsulation of ic device by two level epoxy encapsulation - Google Patents

Plastic encapsulation of ic device by two level epoxy encapsulation Download PDF

Info

Publication number
WO1996013055A2
WO1996013055A2 PCT/US1995/012808 US9512808W WO9613055A2 WO 1996013055 A2 WO1996013055 A2 WO 1996013055A2 US 9512808 W US9512808 W US 9512808W WO 9613055 A2 WO9613055 A2 WO 9613055A2
Authority
WO
WIPO (PCT)
Prior art keywords
die
recited
epoxy
integrated circuit
topping
Prior art date
Application number
PCT/US1995/012808
Other languages
French (fr)
Other versions
WO1996013055A3 (en
Inventor
Andrea Shu-Hui Chen
Randy Hsiao-Yu Lo
Hem Takiar
Original Assignee
National Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corporation filed Critical National Semiconductor Corporation
Priority to EP95937353A priority Critical patent/EP0765529A2/en
Publication of WO1996013055A2 publication Critical patent/WO1996013055A2/en
Publication of WO1996013055A3 publication Critical patent/WO1996013055A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • This invention relates generally to integrated circuit epoxy encapsulated plastic packaging. More particularly it relates to the use of a two level encapsulation arrangement wherein an inner glob-type topping formed from a non-brominated/non-antimony epoxy material is provided to reduce gold-aluminum intermetallic growth in integrated circuit packages.
  • a problem seen during the transfer molding process is the wire sweep or wire J - ' problem in which the bonding wires have a tendency to move, and possibly contact one an th.-. during the injection molding thereby shorting out the leads.
  • the wire wash problem ⁇ particularly noticeable when fairly viscous transfer molding compounds are used during th-.- encapsulation process.
  • An effective measure taken to counter this occurrence is glob-topping that is applied to form a hardened protective barrier over the entire bonding wire region as schematically shown in Fig. la.
  • the glob-topping used in this instance may be any suitable material including a non-brominated epoxy material that contains essentially no bromine, antimony or their compounds thereof. Such materials are commonly referred to as non-flame retardant epoxies.
  • an integrated circuit packaging arrangement for reducing gold-aluminum intermetallic growth.
  • the arrangement provides improved high temperature storage life.
  • a die having a plurality of aluminum bond pads is mounted on a support member.
  • the bond pads are then electrically coupled to associated wiring traces using a plurality of gold bonding wires.
  • Each bonding wire is bonded at a first end to an associated aluminum bond pad and the second end is bonded to an associated wire trace.
  • the connection between the gold bonding wire and the aluminum bond pad defines an intermetallic contact region.
  • the support member can be a variety of supporting structures on which a die can be mounted such as, a substrate, a circuit board, a die attach pad of a lead frame, etc.
  • the wiring traces may take the form of conductive traces laid down on (or within) a substrate, traces on a circuit board, bond pads of an adjacent die, other circuit components within a package, leads of a lead frame etc.
  • the epoxy topping is soft cured until it has gelled but not fully hardened before overmolding, although fully curing the epoxy topping yields acceptable results. The topping tends to "shield" the contacts from the brominated transfer molding compound used to form the exterior plastic package.
  • the transfer molding compound includes at least one of bromine, antimony, and compounds thereof.
  • the package includes a die 22 having aluminum bond pads 28, a lead frame 24, gold bonding wires 32 arranged to electrically connect the bond pads to the lead frame, a non-brominated epoxy topping 38 that covers the intermetallic regions on the top surface of a die 22, and a plastic encapsulation transfer molding compound 40.
  • Fig. 2d shows a cross sectional view of the unit in Fig. 2c that has been molded with a conventional flame retardant transfer molding compound 40 to form an exterior plastic package
  • This second level transfer molding technique is practiced widely and is well known to those skilled in the art.
  • the lead frame has been formed into legs 42 that attach and eleclricallv connect the IC to the circuit board.
  • the resulting package yields considerably improved high temperature storage life and looks and performs in a comparable or superior manner as a standard plastic IC package.
  • the package of the present invention also maintains the UL 94 V-0 flame retardant rating.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A two level epoxy encapsulated integrated circuit device with improved high temperature characteristics is disclosed. The arrangement is particularly useful in packaging integrated circuits (22) having aluminium die pads (28) that are electrically connected to other components using gold bonding wires (32). A non-brominated epoxy topping (38) is applied over the top surface of the die (22) taking special care to encapsulate the intermetallic gold/aluminum bond regions. A second level encapsulation (40) involving a transfer molding compound is then performed to form an exterior plastic package. The resulting package has reduced intermetallic growth and improved high temperature storage life and operational reliability.

Description

PLASTIC ENCAPSULATION OF IC DEVICE BY TWO LEVEL
EPOXY ENCAPSULATION
FIELD OF THE INVENTION
This invention relates generally to integrated circuit epoxy encapsulated plastic packaging. More particularly it relates to the use of a two level encapsulation arrangement wherein an inner glob-type topping formed from a non-brominated/non-antimony epoxy material is provided to reduce gold-aluminum intermetallic growth in integrated circuit packages.
BACKGROUND OF THE INVENTION
One of the most popular techniques of packaging an integrated circuit is by encapsulation (plastic packages). Typically, packaging an integrated circuit using plastic encapsulation involves mounting a die on a support member such as a die attach pad of a lead frame; electrically coupling the die to associated wiring traces such as leads in a lead frame; and then overmolding the die and portions of the wiring trace with a transfer molding compound to form a protective plastic package.
A common method used for electrically coupling an integrated circuit die to its associated wiring trace in semiconductor packaging is wire bonding. Bonding wires are typically made of gold (Au) wherein one end of the bonding wire has a gold ball bond that attaches to the contact region on the die. The contact region on the die typically has an aluminum (Al) bond pad for making electrical contact with the gold ball of the bonding wire. The metallurgical bond between the gold ball bond and aluminum bond pad will be rcterrcd to as an intermetallic contact region from this point on The second end of the bonding wire is then attached to an associated wiring trace, lead tip, bond pad or the like that is arranged to electrically connect the integrated circuit to another component.
It has been found that the intermetallic contact region is particularly susceptible to intermetallic growth which can result in bond degradation and possible electrical failure of the package. This eems to be a particular problem with gold-aluminum bonds and does not seem to occur as much in other intermetallic bonds such as gold-copper or gold-silver bonds In packages that contain lead frames, intermetallic growth at the bonding wire-lead frame contact region is usually not a problem since lead frames are typically formed from copper that is spot plated with silver because gold better adheres to silver and produces a good quality bond
One place where intermetallic growth frequently occurs is during high tempcramr . storage testing. Elevated temperatures combined with the presence of certain substances MI . : as bromine or antimony tend to accelerate intermetallic growth in the contact regions Bπun..' and antimony have very good flame retardant characteristics and are frequently ustΛ. ■■ conventional epoxy transfer molding compounds in order to meet flame retardant guideline-
A problem seen during the transfer molding process is the wire sweep or wire J - ' problem in which the bonding wires have a tendency to move, and possibly contact one an th.-. during the injection molding thereby shorting out the leads. The wire wash problem ι particularly noticeable when fairly viscous transfer molding compounds are used during th-.- encapsulation process. An effective measure taken to counter this occurrence is glob-topping that is applied to form a hardened protective barrier over the entire bonding wire region as schematically shown in Fig. la. The glob-topping used in this instance may be any suitable material including a non-brominated epoxy material that contains essentially no bromine, antimony or their compounds thereof. Such materials are commonly referred to as non-flame retardant epoxies. Such a method for glob topping is disclosed in Weiler et al. co-pending application Serial No. 08/225,900 entitled: Plastic Encapsulated Integrated Circuit Package Having Protective Barrier for Its Bonding Wires and Method filed 04/ 1 1 /94 which is incorporated by reference herein in its entirety Fig. l a is a diagrammatic cross sectional view of a die and lead frame assembly 2 that has had glob-topping 4 applied over the entire die 6 and bonding wires 8. The die 6 is attached to a die attach pad 12 that is supported by support arms (not shown) connected to the lead frame 10. Fig. l b shows the glob-toppcd integrated circuit assembly 2 that has been overmolded with a transfer molding compound to form the exterior plastic package 16.
A similar type coating sometimes applied over the die and bonding wires is sihconc, which is used for stress relief. Si cone has a relatively high thermal expansion as compared t the silicon die but imparts less stress on the die during thermal expansion since it is vci v soli and tends to act like a cushion. Sihcone does not contain flame retardants but has the undesirable properties of having very limited structural and mechanical integrity unl ike other materials, such as epoxy encapsulants, which can stand alone in chip-on-board applκ .itior.s They also exhibit poor adhesion to molding compounds unlike epoxies. Sihcone, bceau • ..; it relatively high thermal expansion coefficient, tends lo sweep the bonding wires into , on..ι . with each other during thermal excursions and sihcone also possesses a much lo - n than epoxies thus is very soft. Thermal excursions and transfer molding pose shear sve^ < •• the both the pad structure and ball bond which may result in bond pull or separated - o-.'.i : For the above and other reasons other materials, such as epoxies, are preferable to silu on. !■ ■ use in semiconductor packages.
A solution used in the past to reduce intermetallic growth was to eliminate gold aluminum intermetallic bonds altogether in semiconductor packages. This yielded higher reliability but was much more costly because it required an expensive new Fab and assembly processes. Another approach was to try to control the concentration of intermetallic growth inducing substances at the source of the epoxy supply. The supplying manufacturer would try to reduce the concentration level of these substances by, for example, introducing ion scavengers and by "cleaning" up the overall manufacturing process. Voltage tests were then 96/13055 PC
performed on the packages since intermetallic growth resulted in increased resistance thus yielding lower voltage readings If the tests proved unsatisfactory, subsequent iterations of the cleansing process and compound formulations may have had to have been evaluated This can be a tediously time consuming and costly process to endure A much more efficient and less costly way to reduce Au-Al intermetallic growth at the semiconductor packaging stage is needed Accordingly, it is a general objective of the present invention to provide a method and apparatus that reduces Au-Al intermetallic growth and allows for improved high temperature and operational reliability
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, an integrated circuit packaging arrangement for reducing gold-aluminum intermetallic growth is described. The arrangement provides improved high temperature storage life. In a method aspect of the invention, a die having a plurality of aluminum bond pads is mounted on a support member. The bond pads are then electrically coupled to associated wiring traces using a plurality of gold bonding wires. Each bonding wire is bonded at a first end to an associated aluminum bond pad and the second end is bonded to an associated wire trace. The connection between the gold bonding wire and the aluminum bond pad defines an intermetallic contact region. A non-brominated epoxy topping material that contains es.sentialh no bromine, antimony or oxide compounds thereof, is then applied over the intermetallic contact regions of the die. The epoxy topping material is applied only on the surface of the die that contains the bond pads and does not overflow the die or encapsulate the entire bonding wires The die, bonding wires and the non-brominated epoxy topping material are then overmolded with a flame retardant epoxy transfer molding compound lo form an exterior plastic package
The support member can be a variety of supporting structures on which a die can be mounted such as, a substrate, a circuit board, a die attach pad of a lead frame, etc. The wiring traces may take the form of conductive traces laid down on (or within) a substrate, traces on a circuit board, bond pads of an adjacent die, other circuit components within a package, leads of a lead frame etc. In one preferred embodiment, the epoxy topping is soft cured until it has gelled but not fully hardened before overmolding, although fully curing the epoxy topping yields acceptable results. The topping tends to "shield" the contacts from the brominated transfer molding compound used to form the exterior plastic package. In another embodiment, the transfer molding compound includes at least one of bromine, antimony, and compounds thereof. In a separate apparatus aspect of the invention a packaged integrated circuit that has reduced intermetallic growth lhat results in improv ed high temperature storage life is described The packaged integrated circuit includes a die mounted on a support member w ith the die containing a plurality of aluminum bond pads A plurality of gold bonding wires arc provided with each bonding wire having a first end that is electrically connected to an associated bond pad thereby defining an intermetallic contact region and a second end electrically connected to an associated w iring trace A non-brominated epoxy topping material is disposed ov er the top surface of the die and the intermetallic contact regions such that the epoxy encapsulant does not overflow the die or encapsulate the entire bonding wires A transfer molding compound overmolds the die, the bond g wires and the topping material to form an exterior plastic package
Adv antages of the present invention include improved high temperature storage lite unaltered external appearance and package performance from conventional plastic packages, and a package that continues to meet flame retardant requirements Another advantage is that the invention can also be used in any plastic package for a variety of products
The two level encapsulated package of the present invention is superior to a device encapsulated with either just the transfer molding compound or the non-brominated epoxv encapsulant alone since, in combination, the molding compound provides the dev ice ith good flame retardant capabilities while the epoxy topping gives high temperature reliabilitv Improved elevated temperature performance allows for greater reliability and high ambient temperature operation (>150 °C) which is particularly desirable in areas such as the automotive market and other high temperature environments
BRIEF DESCRIPTION OF THE DRAWINGS
The invention, together with further objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which-
Fig. la is a diagrammatic cross sectional illustration of a glob-top epoxy applied to a die, bonding wires, and lead frame assembly to prevent wire wash.
Fig lb is a diagrammatic cross sectional illustration the assembly in Fig. la that is molded with a transfer molding compound to form an exterior package.
Figs. 2a-2d show diagrammatic cross sectional illustrations of the encapsulation process in the present invention. Fig. 2a shows a die attached to a die attach pad of a lead frame.
Fig. 2b is a diagrammatic cross sectional illustration of the assembly in Fig. 2a that has been wire bonded.
Fig. 2c is a diagrammatic cross sectional illustration of the assembly in Fig. 2b with a non-brominated epoxy applied over the top surface of the die and intermetallic contact regions
Fig. 2d is a diagrammatic cross sectional illustration of the assembly in Fig. 2c encapsulated with a conventional transfer molding compound.
Fig. 3 is a top view of a die showing the aluminum die pads.
Fig. 4 is an illustration of a second embodiment where the non-brominated epoxy is applied only over the intermetallic contact regions.
Fig. 5 is a diagrammatic top view of the die in Fig. 4 wire bonded to a lead frame. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The following figures referenced lo are not draw n to scale but are used to illustrate the general structure of the device Referring initially to Fig. 2d, a packaged integrated circuit having a two level epoxy encapsulation of Us integrated circuit in accordance with a first embodiment of the present invention will be described The package includes a die 22 having aluminum bond pads 28, a lead frame 24, gold bonding wires 32 arranged to electrically connect the bond pads to the lead frame, a non-brominated epoxy topping 38 that covers the intermetallic regions on the top surface of a die 22, and a plastic encapsulation transfer molding compound 40. It should be noted that the non-brominated epoxy topping 38 is applied only to the top surface of the die 22 and does not overflow over the edge yet is applied in such a manner that the gold-aluminum intermetallic contact regions defined where the gold bonding wires 32 attach to the aluminum bond pads are completely covered
The means that supports the die is referred to herein as a support member and can be any suitable supporting structures. By way of example, substrates, circuit boards, heat spreaders, and die attach pads Likewise, the term wiring traces is used in this context to include any suitable structure that the bonding wires may be adhered to. By way of example, conductive traces or any contacts laid down on a substrate or circuit board, circuit components within a package, bond pads on adjacent dies, or leads on adjacent leads of a lead frame are all contemplated. Referring next to Fig. 2a, a method of packaging a die in accordance with a first embodiment of the present invention will be described. In the embodiment shown, a die 22 is affixed to a die attached pad 26. The die attach pad 26 may be supported by support arms (shown as 56 in Fig. 5) attached to the lead frame 24. The lead frame may be a conventional lead frame constructed, by way of example, out of copper or a copper alloy because of their relatively good conductivity and cost effectiveness. The lead frame may be stamped out of a sheet of conducting material or it can be etched in a process that is well known in the industry. Referring next to Fig. 2b, the die 22 is electrically coupled to a lead frame 24 through the use of bonding wires 32. It should be noted that other conventional bonding methods such as tape automated bonding (TAB) are possible as well Bonding wires 32 arc made of a conductive material such a gold because of its excellent conductivity and ability to bond well To improve bonding to copper lead frames, silver may be spot plated on the lead tips. The first end of the bonding wire is metallurgically bonded with the bond pad 28 on the die 22 Suitable wire bonding techniques are well known to those skilled in the art and are widely used in the industry today. By way of example ball bonding and stitch bonding are appropriate
Fig. 2c shows the assembly of Fig 2b after a non-brominated epoxy material 38 applied over the top surface of the die 22. Particular care is taken to cover the intermetallic contact regions. The non-brominated epoxy is also referred to as a non-flame retardant, as opposed to brominated materials which are present in typical transfer molding compounds formulated to meet the UL 94V-0 package flame retardant requirement. Brominated materials in this context includes, in addition to bromine, antimony and compounds thereof such as derivative oxides such as antimonytrioxide or antimonypentoxide, for example. By way of example, suitable non-brominated epoxy materials include non-flame retardant epoxies available from companies such as Dexter Electronic Materials of Industry, California and Sumitomo Bakelite Corp., which have been found to work well. In order to provide adequate protection, the topping material must at least cover the ball bond-bond pad intermetallic contact region but may also cover the entire die surface as shown in the Fig. 2c.
Flame retardants or brominated materials tend to accelerate intermetallic growth, which is especially prominent at elevated temperatures, in bonds between gold and aluminum. By way of example, some brominated compounds have been seen to induce intermetallic growth after around 1000 hours of high temperature testing at about 150°C to 175°C. Brominates and antimony play a catalytic role in inducing a degradative reaction that converts the gold rich intermetallic into AuAl5 among other byproducts. Continued intermetallic growth weakens the bonds resulting in increased resistivity or potential electrical failure of the package. Moisture induced degradation is also a significant issue Degradation of the gold wiic-aluminuin bond pad intermetallic bond is accelerated by moisture at ielativcly low temperatures 1 0- 160°C. leading lo loss of bond strength alter around 500 hours of testing. Non-brominaied epoxv topping is also effective in protecting against moisture induced degradation, as well
For applications w here heat dissipation is an important issue, the encapsulant can include a highly thermally conductive filler which, combined with high Tg compound, can be- very effective in conducting heat away from the die The conductive filler utilized in conduction with a heat spreader, for exampic, can be used effectively with high performance, high heal generating IC's. Following the application of the topping, the device is then baked to "gel' or "soft cure" the encapsulant. Of course the appropriate soft curing time will depend on the mateπal used as the topping. When the aforementioned epoxies are used, baking in the range of 1 10°C to 150°C, and preferably around 125°C for about several minutes works well To achieve optimum results, the epoxy should not be fully cured at this point. This permits the encapsulant to somewhat "harden" around the intermetallic contact areas prior to the transfer molding process. Acceptable results are also obtained if the epoxy topping is fully cured prior to the transfer molding step.
Fig. 2d shows a cross sectional view of the unit in Fig. 2c that has been molded with a conventional flame retardant transfer molding compound 40 to form an exterior plastic package This second level transfer molding technique is practiced widely and is well known to those skilled in the art. The lead frame has been formed into legs 42 that attach and eleclricallv connect the IC to the circuit board. The resulting package yields considerably improved high temperature storage life and looks and performs in a comparable or superior manner as a standard plastic IC package. The package of the present invention also maintains the UL 94 V-0 flame retardant rating.
Fig. 3 shows a top view of a typical die illustrating the aluminum bond pads 48 along the four outer edges of the top surface of the die. In this quad configuration, it may not be necessary to apply the non-brominated epoxy over the entire surface of the die but in a manner such that the bond pads are covered. Other arrangements of bond pads, for example, in a grid pattern throughout the entire surface of the die or portions thereof arc possible thus the application of the non-brominated epoxy over the entire surface makes sense. Fig. 4 shows a second embodiment where the die is sufficiently large enough such that the non-brominated epoxy can be applied in a "ring" over the intermetallic regions of the die 22, illustrated without bonding wires for simplicity, as described above. Further embodiments of the present invention that include spot application of individual bond pads when separation is large or irregularly spaced are possible, so long as the intermetallic regions are covered.
Fig. 5 shows a top view of the die in Fig. 4 wire bonded 32 to a conventional lead frame 24 with non-brominated epoxy encapsulation material 50 applied over the intermetallic regions in accordance with the second embodiment. It should be pointed out that the epoxy does not cover a major portion of the bonding wires 32 or any of the lead frame. Rather it is only deposited within the periphery of the die 22. This embodiment is then processed exactly as embodiment one in that a second level encapsulation of a transfer molding compound is performed to form the plastic package. There is no visible exterior difference from conventional packages and the alterations made by the invention are impervious to the customer. This two level encapsulation prove beneficial in several aspects over conventional plastic packages. Performance gain due to improved heat conduction of the encapsulant is possible. However, more importantly, the package provides improved high temperature storage life resulting in longer operational lifetime of the device.
Although two embodiments of the present invention have been described in detail, it should be understood that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. While this invention has been described in terms of a Quad Flat Package, it should also be understood that the invention can be applied to other types of packages as well. Particularly, the method described can be used in a multi-chip packages where multiple dies are coupled and bonded together within a single package. Similarly, the method is applicable to hybrid packages in which multiple components , ,,Λ« PCTA S95/12 O 96/13055
such as resistors, capacitors, or other circuit elements are coupled and bonded to the die/dies within a single package These multi-component packages may be electrically coupled in various ways including using gold bonding wires bonded lo aluminum bond pads in which this invention would be pertinent. It should be noted that the same type of improvement may be lound in both ball bonding and stitch bonding procedures Therefore the present examples arc to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope of the appended claims
Wluit is claimed is:

Claims

C L A I M S
1 A method of packaging an integrated circuit comprising the steps of
(a) mounting a die on a support member wherein the die has a plurality of aluminum bond pads,
(b) electrically coupling the bond pads to associated wiring traces by using a plurality of gold bonding wires wherein each bonding wire having a first end that is bonded to an associated aluminum bond pad and a second end bonded to a lead of an associated w ire trace, the connection between the gold bonding ball of first end of the bonding wire to the aluminum bond pad defines an intermetallic contact region, and
(c) applying a non-brominated epoxy topping material, that contains essential K no bromine, antimony or oxide compounds thereof, over the intermetallic contact regions ot itu- die wherein the epoxy topping material is applied only on the surface of the die that contain- u - bond pads and does not overflow the die or encapsulate the entire bonding wires, and
(d) overmolding the die, the bonding wires and the non-brominated epow to,-;- • • material with epoxy transfer molding compound to form an exterior plastic package
2 A method as recited in claim 1 wherein the support member is a w herein c support member is a die attach pad.
3 A method as recited in claim 1 wherein the support member is a substrate or circuit board.
4. A method as recited in claim 1 wherein the wiring trace is a lead frame
5 A method as recited in claim 1 wherein the wiring trace includes bonding pads of adjacent dies or circuit components, and includes electrical connections there between the aforementioned
6. A method as recited in claim I wherein the non-brominated epoxv topping material is non-flame retardant
7. A method as recited in claim 1 wherein the non-brominated epoxy topping material is applied only over the intermetallic contact regions on the die
8. A method as recited in claim 1 further compπsing the step of soft curing the non- brominated epoxy topping material after it has been applied to the die and before the overmolding step.
9. A method as recited in claim 8 wherein the soft curing is accomplished bv baking at a temperature in a range of approximately 1 10°C to 150°C until the topping is soft cured.
10. A method as recited in claim 1 further comprising the step of fully curing the non-brominated epoxy topping material after it has been applied to the die and before the overmolding step.
1 1 . A method as recited in claim 1 wherein the transfer molding compound is a flame retardant material that includes at least one of bromine, antimony, or compounds thereof
12. A packaged integrated circuit comprising:
(a) a die mounted on a support member, the die having a plurality of aluminum bond pads; (b) a plurality of gold bonding wires each having a first end thai is electrically connected to the bond pad thereby defining an intermetallic contact region;
(c) a plurality of wiring traces each electrically connected to a second end of an associated bonding wire,
(d) a non-brominated epoxy topping material, that contains essentially no bromine, antimony, or oxide compounds thereof, the topping material being disposed over the top surface of the die and the intermetallic contact regions such that the epoxy encapsulant does not overflow the die or encapsulate the entire bonding wires;
(e) a transfer molding compound that overmolds the die, the bonding wires and the topping material to form an exterior plastic package.
13. A packaged integrated circuit as recited in claim 12 wherein the support member is a die attach pad.
14. A packaged integrated circuit as recited in claim 12 wherein the support member includes a substrate or circuit board.
15. A packaged integrated circuit as recited in claim 12 wherein the wiπng trace is a lead frame.
16. A packaged integrated circuit as recited in claim 12 wherein the wiring trace includes bonding pads of adjacent dies or circuit components, and includes electrical connections there between the aforementioned.
17. A packaged integrated circuit as recited in claim 12 wherein the topping material is a non-flame retardant epoxy material.
18. A packaged integrated circuit as recited in claim 12 wherein the transfer molding compound is a flame retardant material that includes at least one of bromine, antimony, and an antimony based compound.
PCT/US1995/012808 1994-10-13 1995-10-13 Plastic encapsulation of ic device by two level epoxy encapsulation WO1996013055A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP95937353A EP0765529A2 (en) 1994-10-13 1995-10-13 Plastic encapsulation of ic device by two level epoxy encapsulation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US32276994A 1994-10-13 1994-10-13
US08/322,769 1994-10-13

Publications (2)

Publication Number Publication Date
WO1996013055A2 true WO1996013055A2 (en) 1996-05-02
WO1996013055A3 WO1996013055A3 (en) 1996-07-11

Family

ID=23256329

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1995/012808 WO1996013055A2 (en) 1994-10-13 1995-10-13 Plastic encapsulation of ic device by two level epoxy encapsulation

Country Status (2)

Country Link
EP (1) EP0765529A2 (en)
WO (1) WO1996013055A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2758417A1 (en) * 1997-01-16 1998-07-17 Thomson Csf Production of housing for packaging microwave component, for PCB
US11501116B1 (en) 2021-07-19 2022-11-15 Sas Institute Inc. Quality prediction using process data

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0260360A1 (en) * 1985-04-05 1988-03-23 Dow Corning Toray Silicone Co., Ltd. Resin-sealed semiconductor device
WO1990004854A1 (en) * 1988-10-17 1990-05-03 Gallo Anthony A Flame retardant epoxy molding compound, method and encapsulated device
US5225499A (en) * 1990-03-09 1993-07-06 Hitachi, Ltd. Resin composition for encapsulating of semiconductor and semiconductor apparatus using of the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55113350A (en) * 1979-02-23 1980-09-01 Hitachi Ltd Semiconductor device
JPS63107050A (en) * 1986-10-24 1988-05-12 Hitachi Ltd Resin seal type semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0260360A1 (en) * 1985-04-05 1988-03-23 Dow Corning Toray Silicone Co., Ltd. Resin-sealed semiconductor device
WO1990004854A1 (en) * 1988-10-17 1990-05-03 Gallo Anthony A Flame retardant epoxy molding compound, method and encapsulated device
US5225499A (en) * 1990-03-09 1993-07-06 Hitachi, Ltd. Resin composition for encapsulating of semiconductor and semiconductor apparatus using of the same

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
22ND ANNUAL PROCEEDINGS RELIABILITY PHYSICY 1984, 3 April 1984, LAS VEGAS, NEVADA, pages 37-47, XP000567344 REBECCA GALE: "EPOXY DEGRADATION INDUCED AU-AL INTERMETALLIC VOID FORMATION IN PLASTIC ENCAPSULATED MOS MEMORIES" *
PATENT ABSTRACTS OF JAPAN vol. 004, no. 165 (E-034), 15 November 1980 & JP,A,55 113350 (HITACHI LTD), 1 September 1980, *
PATENT ABSTRACTS OF JAPAN vol. 012, no. 348 (E-659), 19 September 1988 & JP,A,63 107050 (HITACHI LTD), 12 May 1988, *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2758417A1 (en) * 1997-01-16 1998-07-17 Thomson Csf Production of housing for packaging microwave component, for PCB
US11501116B1 (en) 2021-07-19 2022-11-15 Sas Institute Inc. Quality prediction using process data
US11630973B2 (en) 2021-07-19 2023-04-18 Sas Institute Inc. Quality prediction using process data

Also Published As

Publication number Publication date
EP0765529A2 (en) 1997-04-02
WO1996013055A3 (en) 1996-07-11

Similar Documents

Publication Publication Date Title
US6133068A (en) Increasing the gap between a lead frame and a semiconductor die
US5581119A (en) IC having heat spreader attached by glob-topping
US6291899B1 (en) Method and apparatus for reducing BGA warpage caused by encapsulation
JPH06236946A (en) Heat spreader and semiconductor device having strengthened connection between lead and plastic package
US6040633A (en) Oxide wire bond insulation in semiconductor assemblies
JPH0831988A (en) Sealing structure of tape carrier package
JP2959480B2 (en) Semiconductor device and manufacturing method thereof
JP2000077603A (en) Semiconductor device and its manufacture
JP2586835B2 (en) Semiconductor integrated circuit
US7572674B2 (en) Method for manufacturing semiconductor device
WO1996013055A2 (en) Plastic encapsulation of ic device by two level epoxy encapsulation
JPS60195955A (en) Semiconductor device
US5849607A (en) Process for attaching a lead frame to a semiconductor chip
JP3404438B2 (en) Semiconductor device and manufacturing method thereof
JP3683597B2 (en) Resin encapsulated semiconductor device
JPH0745960Y2 (en) Resin-sealed semiconductor device
JP2713141B2 (en) Semiconductor device
JPH08115941A (en) Semiconductor device
JP2779322B2 (en) Semiconductor package manufacturing method
JP3218816B2 (en) Semiconductor device
JPS6089945A (en) Sealed semiconductor device
JPH1084055A (en) Semiconductor device and its manufacturing method
KR0125874Y1 (en) Semiconductor package
KR0167440B1 (en) Semiconductor device
KR0161353B1 (en) Manufacture of epoxy mold packing

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): DE KR

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

WWE Wipo information: entry into national phase

Ref document number: 1995937353

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWP Wipo information: published in national office

Ref document number: 1995937353

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1995937353

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642