USRE37416E1 - Method for manufacturing a modular semiconductor power device - Google Patents

Method for manufacturing a modular semiconductor power device Download PDF

Info

Publication number
USRE37416E1
USRE37416E1 US08/558,979 US55897995A USRE37416E US RE37416 E1 USRE37416 E1 US RE37416E1 US 55897995 A US55897995 A US 55897995A US RE37416 E USRE37416 E US RE37416E
Authority
US
United States
Prior art keywords
sheet
strips
semiconductor device
electrically conductive
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/558,979
Inventor
Antonio P. Spatrisano
Luciano Gandolfi
Carlo Minotti
Natale Di Cristina
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Priority to US08/558,979 priority Critical patent/USRE37416E1/en
Application granted granted Critical
Publication of USRE37416E1 publication Critical patent/USRE37416E1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Definitions

  • the present invention relates to a method of manufacturing a modular semiconductor power device and to a device as obtained by such method.
  • the known semiconductor power devices involve complex and costly procedures, both from the point of view of the individual components necessary for constructing them and from the standpoint of their assembly and reciprocal insulation.
  • the object of this invention is to provide a particularly reliable modular power device obtained by means of an extremely simple and not very expensive assembly procedure, according to a highly flexible manufacturing method and with components which, although extremely limited in number, can be used to create various circuit arrangements and layouts, always using the same tools and always maintainins maintaining an identical external geometrical configuration of the devices obtained.
  • the reciprocal insulated insulation of the electrodes and their encapsulation are carried out in a single step.
  • the manufacturing method according to the invention for making a modular semiconductor power device comprising one or more semiconductor chips, a metal plate for dissipating heat generated by the Joule effect, a plurality of electrodes constituting the signal and power terminals of the device, and a resin encapsulation, comprises soldering the chip or chips onto one or more plates of electrically conductive material;
  • Each sheet can be made of copper and that the latter, before the chips are soldered onto it, can be placed in a plate consisting of three layers soldered directly onto each other, in which the first layer is made up of the sheet and copper strips insulated from the sheet itself.
  • the intermediate layer consists of an alumina plate and the third layer consists of a sheet of copper substantially equal in size or slightly smaller than the intermediate layer.
  • the aforesaid points of connection are situated on the aforesaid sheets and strips, the soldering of the inner ends of the terminals to the aforesaid points is preceded by the soldering of wires connecting the chips to the aforesaid strips.
  • the sheet can be soldered onto the internal surface of the plate and the connections between chips and strips can be made by means of ultrasound soldering of aluminum wires.
  • the aforesaid points of connection with the chips can be located on the aforesaid sheets and on wettable metal coatings on the surface of the chips.
  • the inner ends of the terminals After blanking of the one-piece frame and before the aforesaid soldering of the inner ends of the terminals to the points of connection, the inner ends of the terminals can be bent in a direction perpendicular to the plane of the frame.
  • the terminals designed to perform the function of signal terminals can be bent in a direction perpendicular to the base plate, while the terminals designed to perform the function of power terminals can be bent over the capsule in a direction parallel to the base plate itself.
  • FIG. 1 is an exploded view of the base plate and the substrates supporting the chips: ;
  • FIGS. 2 a and 2 b are a side view and a cross-sectional view of the base plate of FIG. 1;
  • FIGS. 3 a , 3 b and 3 c are bottom, top and cross-sectional views of a substrate of FIG. 1;
  • FIG. 4 is a view of the base plate of FIG. 1 after the substrates and the chips have been joined to it, and after the electrical connections between chips and metal coating of the substrates have been made;
  • FIG. 5 is a perspective view of the one-piece frame for obtaining the external terminals and their connections with the metal-coating of the substrates;
  • FIG. 6 is a plan view of the flattened frame from which the frame of FIG. 5 was obtained;
  • FIG. 7 is a perspective view of the modular device after the resin encapsulation has been carried out by molding.
  • FIGS. 8 a , 8 b and 8 c are respective perspective top and bottom views and a plan view of the finished device.
  • the base plate 11 of the device acts as a heat sink as well as a support and fastener for the device itself. It is made of heat-conductive metal with high mechanical strength.
  • the holes A in it serve to secure it, by means of screws, onto the external heat spreader, while the grooves V serve to absorb any possible deformation of the base plate due to the high tightening torque, thereby preventing them from being transmitted to the central portion of the plate.
  • the S-shaped recesses M, on the sides serve to ensure a better adhesion of the subsequently applied resin encapsulation, as is explained more clearly further on with reference to FIG. 8 b.
  • FIG. 1 also shows the components 12 and 13 , which are two chip-supporting substrates, which are soldered onto the base plate 11 by means of the layers of solder 14 .
  • each substrate is composed of a quadrangular-shaped thin medial layer 31 of alumina (less than 1 mm thick), with thin copper plates soldered directly onto its two lateral faces.
  • soldered onto the face destined to lie facing the upper face of the base plate 11 is a single copper plate 32 , which is also quadrangular in shape but with slightly smaller dimensions than those of the layer of alumina, while the other face is provided with a rectangular plate 33 , for supporting the chips and for the connections with an external electrode, and, on either side of said plate 33 , narrower plates (lateral strips) 34 , 35 and 36 designed both for soldering the conductor for connection with the chips, and for soldering other external electrodes.
  • FIG. 4 shows the device 41 as it appears after the two substrate substrates have been soldered onto the base plate, the chips have been soldered onto the larger upper copper plates b and f, and the electrical connections have been carried out between the chips and the lateral strips a, c, d, e, g, and h.
  • the latter connections are obtained by ultrasonic soldering with aluminum wire.
  • FIG. 5 shows a copper frame 51 designed to constitute the external terminals and the connections of the latter with the lateral strips and the plates f and b of FIG. 4 .
  • the frame of FIG. 5 is obtained by blanking from a copper sheet and by subsequently bending the terminal portions downwards, said terminal portions being subsequently soldered onto the lateral strips and the plates f and b.
  • FIG. 6 shows a plan view of the frame of FIG. 5, as it appears after being blanked from the copper sheet and before the bending of the terminal portions, which are indicated respectively by h, g, e, d, c, a, f, and b.
  • the terminal portions are then soldered respectively onto the strips h, g, e, d, c, and a, and onto the plates f and b of 41 .
  • the device is encapsulated by means of a molding process with insulting insulating resin (e.g. thermosetting epoxy resin), preferably of the low-stress type.
  • insulting insulating resin e.g. thermosetting epoxy resin
  • the device After the moldings phase, the device has the appearance shown in FIG. 7. At this point, in order to complete complete the device, it is necessary to shear the external temporary connections between the terminals, corresponding to the portions 61 illustrated in dotted cross- hatched lines in FIG. 6, and then bend the signal terminals upwards to a vertical position, and the power terminals inwards.
  • the finished device takes on the appearance of FIG. 8 a (top perspective view) and of FIG. 8 b (bottom perspective view), in which 81 , 82 , 83 and 84 indicate the signal terminals and 85 , 86 and 87 indicate the power terminals.
  • the resin encapsulation ends, from below, are flush with the lower surface of the base plate 11 , which can consequently be secured in direct contact with the supporting metal structure on which it is designed to be placed, thereby ensuring efficient dissipation of the heat.
  • the same figure clearly shows the function of the S-shaped recesses M on the base plate (see FIGS. 1 and 2 b ). In fact, on completion of the device, they are completely embedded in the resin body, so as to constitute two areas for anchoring and ensuring an efficient grip of the resin.
  • the one-piece of FIG. 5 and FIG. 6 can also be made with different geometrical layouts, to enable it to adapt to the different geometrical layouts of the aforesaid soldered strips, and to the different electrical functions of the device;
  • a further advantage in addition to those mentioned previously, is related to the particular structure of the substrate chosen for soldering the chips as well as that related to the type of resin used for the encapsulation.
  • these substrates which consist of a layer of alumina with copper plates soldered directly onto both faces, are characterized by thermal expansion coefficients very similar to those of silicon.
  • thermomechanical stress which would otherwise be transmitted to the chips due to the differential expansion of silicon and copper
  • other embodiments envisage the insertion, between the chips and the supporting copper plates, of layers of material, such as for example, molybdenum, having an expansion coefficient lying half way between those of silicon and copper, which however complicate the assembling and lower the thermal performance).
  • the wires connecting the chips to the metal strips of the substrates can be by direct soldering between the inner terminal portions of the one-piece frame and the chips, whenever the latter have wettable metal coatings. These internal portions can then be soldered to points (P) of connection with the chips situated on the aforesaid plates 33 and strips 34 , 35 , 36 (as in the case illustrated in FIGS. 4 and 5 ), or situated on the same plates and on wettable metal coatings on the surface of the chips.
  • the chip-supporting substrates could have a different structure from that previously described and the insulation between the chips and the dissipator could be achieved by means of a layer of the encapsulating resin itself—which in this case should be of high thermal conductivity—instead of by a layer of alumina.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The components used in the method comprise a heat-dissipating base plate, one or more three-layer plates (the top layer consisting of copper plates and strips) and a one-piece frame designed to constitute the terminals. After the chips have been soldered onto the upper plates and connected to the strips, the inner ends of the frame are soldered to points of connection with the chips. This is followed by the encapsulation in resin and the shearing of the outer portions of the frame, which, during the process, serve to temporarily connect the terminals.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation of application Ser. No. 08/152,253, filed on Nov. 12, 1993, now abandoned; which is a continuation of Ser. No. 07/864,492 filed on Apr. 7, 1992, now abandoned, which is a continuation of co-pending application Ser. No. 07/160,630 filed on 26 Feb. 1988 now abandoned.
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a modular semiconductor power device and to a device as obtained by such method.
BACKGROUND OF THE INVENTION
In the manufacture of modular semiconductor power devices, as in the manufacture of numerous other components, an important target is to produce extremely reliable products using sample simple and inexpensive procedures.
The known semiconductor power devices involve complex and costly procedures, both from the point of view of the individual components necessary for constructing them and from the standpoint of their assembly and reciprocal insulation.
Some of these known devices are described in U.S. Pat. No. 4,518,982. This patent gives a detailed description of a modular power device whose manufacturing process consists of soldering one or more semiconductor chips onto a flat portion of a first electrode (which also serves as a heat sink), soldering other electrodes (possibly containing other chips) onto the flat portion by means of a dielectric adhesive material, electrically connecting the various chips and electrodes, encapsulating the device in resin, and electrically insulating the heat dissipating surface by means of a further layer of insulating material.
OBJECT OF THE INVENTION
The object of this invention is to provide a particularly reliable modular power device obtained by means of an extremely simple and not very expensive assembly procedure, according to a highly flexible manufacturing method and with components which, although extremely limited in number, can be used to create various circuit arrangements and layouts, always using the same tools and always maintainins maintaining an identical external geometrical configuration of the devices obtained.
SUMMARY OF THE INVENTION
According to a particular feature of the manufacturing method, the reciprocal insulated insulation of the electrodes and their encapsulation are carried out in a single step. The manufacturing method according to the invention for making a modular semiconductor power device comprising one or more semiconductor chips, a metal plate for dissipating heat generated by the Joule effect, a plurality of electrodes constituting the signal and power terminals of the device, and a resin encapsulation, comprises soldering the chip or chips onto one or more plates of electrically conductive material;
positioning the plate or plates on a plane substantially parallel to the aforesaid heat dissipating plate and close to the latter;
blanking, from a single sheet of conductive material, a one-piece frame designed to constitute the power and signal terminals, the blanking enabling temporary connections to be kept between the portions of the terminal conductors designed to remain outside of the resin encapsulation;
soldering the inner ends of the terminals to points arranged for the connection to the aforesaid chips;
encapsulating with insulting insulating resin all the active parts of the device, leaving uncovered the outer surface of the plate and the portions of the terminals involved with the aforesaid temporary connections; and
shearing the temporary connections.
Each sheet can be made of copper and that the latter, before the chips are soldered onto it, can be placed in a plate consisting of three layers soldered directly onto each other, in which the first layer is made up of the sheet and copper strips insulated from the sheet itself. The intermediate layer consists of an alumina plate and the third layer consists of a sheet of copper substantially equal in size or slightly smaller than the intermediate layer. The aforesaid points of connection are situated on the aforesaid sheets and strips, the soldering of the inner ends of the terminals to the aforesaid points is preceded by the soldering of wires connecting the chips to the aforesaid strips.
The sheet can be soldered onto the internal surface of the plate and the connections between chips and strips can be made by means of ultrasound soldering of aluminum wires.
The aforesaid points of connection with the chips can be located on the aforesaid sheets and on wettable metal coatings on the surface of the chips.
After blanking of the one-piece frame and before the aforesaid soldering of the inner ends of the terminals to the points of connection, the inner ends of the terminals can be bent in a direction perpendicular to the plane of the frame.
After the encapsulation and the shearing of the temporary connections of the one-piece frame, the terminals designed to perform the function of signal terminals can be bent in a direction perpendicular to the base plate, while the terminals designed to perform the function of power terminals can be bent over the capsule in a direction parallel to the base plate itself.
BRIEF DESCRIPTION OF THE DRAWINGS
The features of the invention will be more clearly evident from the following description and the accompanying drawing in which:
FIG. 1 is an exploded view of the base plate and the substrates supporting the chips: ;
FIGS. 2a and 2 b, respectively, are a side view and a cross-sectional view of the base plate of FIG. 1;
FIGS. 3a, 3 b and 3 c, respectively, are bottom, top and cross-sectional views of a substrate of FIG. 1;
FIG. 4 is a view of the base plate of FIG. 1 after the substrates and the chips have been joined to it, and after the electrical connections between chips and metal coating of the substrates have been made;
FIG. 5 is a perspective view of the one-piece frame for obtaining the external terminals and their connections with the metal-coating of the substrates;
FIG. 6 is a plan view of the flattened frame from which the frame of FIG. 5 was obtained;
FIG. 7 is a perspective view of the modular device after the resin encapsulation has been carried out by molding; and
FIGS. 8a, 8 b and 8 c are respective perspective top and bottom views and a plan view of the finished device.
SPECIFIC DESCRIPTION
In FIG. 1 the base plate 11 of the device acts as a heat sink as well as a support and fastener for the device itself. It is made of heat-conductive metal with high mechanical strength. The holes A in it serve to secure it, by means of screws, onto the external heat spreader, while the grooves V serve to absorb any possible deformation of the base plate due to the high tightening torque, thereby preventing them from being transmitted to the central portion of the plate.
The S-shaped recesses M, on the sides (see the side and cross-sectional views of the plate shown in FIGS. 2a and 2 b) serve to ensure a better adhesion of the subsequently applied resin encapsulation, as is explained more clearly further on with reference to FIG. 8b.
FIG. 1 also shows the components 12 and 13, which are two chip-supporting substrates, which are soldered onto the base plate 11 by means of the layers of solder 14.
As illustrated in FIGS. 3a, 3 b and 3 c (bottom, top and cross-sectional views of a substrate) each substrate is composed of a quadrangular-shaped thin medial layer 31 of alumina (less than 1 mm thick), with thin copper plates soldered directly onto its two lateral faces. More precisely, soldered onto the face destined to lie facing the upper face of the base plate 11 is a single copper plate 32, which is also quadrangular in shape but with slightly smaller dimensions than those of the layer of alumina, while the other face is provided with a rectangular plate 33, for supporting the chips and for the connections with an external electrode, and, on either side of said plate 33, narrower plates (lateral strips) 34, 35 and 36 designed both for soldering the conductor for connection with the chips, and for soldering other external electrodes.
FIG. 4 shows the device 41 as it appears after the two substrate substrates have been soldered onto the base plate, the chips have been soldered onto the larger upper copper plates b and f, and the electrical connections have been carried out between the chips and the lateral strips a, c, d, e, g, and h. The latter connections are obtained by ultrasonic soldering with aluminum wire.
FIG. 5 shows a copper frame 51 designed to constitute the external terminals and the connections of the latter with the lateral strips and the plates f and b of FIG. 4. The frame of FIG. 5 is obtained by blanking from a copper sheet and by subsequently bending the terminal portions downwards, said terminal portions being subsequently soldered onto the lateral strips and the plates f and b.
FIG. 6 shows a plan view of the frame of FIG. 5, as it appears after being blanked from the copper sheet and before the bending of the terminal portions, which are indicated respectively by h, g, e, d, c, a, f, and b. After being bent downwards, the terminal portions are then soldered respectively onto the strips h, g, e, d, c, and a, and onto the plates f and b of 41. After the frame 51 has been soldered onto the device 41, the device is encapsulated by means of a molding process with insulting insulating resin (e.g. thermosetting epoxy resin), preferably of the low-stress type.
After the moldings phase, the device has the appearance shown in FIG. 7. At this point, in order to complete complete the device, it is necessary to shear the external temporary connections between the terminals, corresponding to the portions 61 illustrated in dotted cross-hatched lines in FIG. 6, and then bend the signal terminals upwards to a vertical position, and the power terminals inwards.
The finished device takes on the appearance of FIG. 8a (top perspective view) and of FIG. 8b (bottom perspective view), in which 81, 82, 83 and 84 indicate the signal terminals and 85, 86 and 87 indicate the power terminals.
As shown in FIG. 8b, the resin encapsulation ends, from below, are flush with the lower surface of the base plate 11, which can consequently be secured in direct contact with the supporting metal structure on which it is designed to be placed, thereby ensuring efficient dissipation of the heat. The same figure clearly shows the function of the S-shaped recesses M on the base plate (see FIGS. 1 and 2b). In fact, on completion of the device, they are completely embedded in the resin body, so as to constitute two areas for anchoring and ensuring an efficient grip of the resin.
As shown in FIG. 8c (plan view of the device), after the bending, the terminal holes of the three power terminals 85, 86 and 87 come to rest exactly above the three hexagonal nuts embedded in the resin, so as to enable the electrical connection with the external connecting rods.
The foregoing description gives a clear idea both of the versatility of the method of the invention and of the simplicity of the assembling procedure. In fact, it is clear that:
with the substrates of FIG. 1 and FIG. 3, it is possible to use chips of different number and sizes, to achieve different connections of the chips with the lateral strips, and to obtain soldered strips with different geometrical layouts;
the one-piece of FIG. 5 and FIG. 6 can also be made with different geometrical layouts, to enable it to adapt to the different geometrical layouts of the aforesaid soldered strips, and to the different electrical functions of the device;
the procedures for soldering the conductors connecting the chips to the metal strips and the external electrodes to the metal chip-supporting strips or plates are simplified due to the flat disposition of the soldering points and to the fact that the inner ends of the electrodes are soldered when they are still firmly secured to each other by the aforesaid temporary connections; and
due to the fact that the chips are soldered onto coplanar plates and to the presence of the temporary connections between the electrodes it is also possible to carry out the encapsulation and reciprocal insulation of the electrodes in a single step. A further advantage, in addition to those mentioned previously, is related to the particular structure of the substrate chosen for soldering the chips as well as that related to the type of resin used for the encapsulation. In fact, these substrates, which consist of a layer of alumina with copper plates soldered directly onto both faces, are characterized by thermal expansion coefficients very similar to those of silicon. This reduces to a minumum the thermomechanical stress which would otherwise be transmitted to the chips due to the differential expansion of silicon and copper (other embodiments envisage the insertion, between the chips and the supporting copper plates, of layers of material, such as for example, molybdenum, having an expansion coefficient lying half way between those of silicon and copper, which however complicate the assembling and lower the thermal performance).
The use of a low-stress type of resin helps to limit the stress transmitted to the chips even in the case of chips of very large dimensions.
It is also clear that numerous modifications, adjustments, variations and substitutions may be made to the embodiments previously described by way of example, always remaining within the spirit of this invention and its scope. For example, the wires connecting the chips to the metal strips of the substrates can be by direct soldering between the inner terminal portions of the one-piece frame and the chips, whenever the latter have wettable metal coatings. These internal portions can then be soldered to points (P) of connection with the chips situated on the aforesaid plates 33 and strips 34, 35, 36 (as in the case illustrated in FIGS. 4 and 5), or situated on the same plates and on wettable metal coatings on the surface of the chips.
Likewise, the chip-supporting substrates could have a different structure from that previously described and the insulation between the chips and the dissipator could be achieved by means of a layer of the encapsulating resin itself—which in this case should be of high thermal conductivity—instead of by a layer of alumina.

Claims (39)

We claim:
1. A method of manufacturing a modular semiconductor power device, comprising the steps of:
(a) welding semiconductor means including at least oneattaching a semiconductor chip onto conductive-sheet means including at least onea sheet of an electrically conductive material;
(b) forming a power-device body by fixingaffixing said sheet to a member provided with a heat-dissipating metal plate for dissipating heat generated by the Joule effect and parallel to and close to said heat-dissipating plate ;
(c) blanking from a single sheet of conductive material a one-pieceforming a frame formed with strips adapted to formfor signal and power terminals offor said devicesemiconductor chip, and with temporary connections between at least some of outer ends of said strips;
(d) solderingselectively connecting inner ends of said strips selectively to points of said conductive sheet means connected with said semiconductor means or to said semiconductor meanschip;
(e) encapsulating at least active parts of said bodysemiconductor chip, said sheet of electrically conductive material, and said inner ends of said strips with an insulating resin and leaving said outer ends of said strips and an outer surface of said plate uncovered by said resin ; and
(f) shearingremoving said temporary connections from said strips.
2. The method defined in claim 1wherein said conductor sheet means comprises a plurality of sheet members composed of copper, said sheet means being disposedfurther comprising forming said sheet of electrically conductive material by disposing a first electrically conductive sheet member on a first face of an intermediate layer formed with an alumina plate, and a further sheet of copper of a size at most equal to that of the intermediate layer and disposeddisposing a second electrically conductive sheet member on anothera second face of said intermediate layer, said inner ends of said strips being soldered to said sheet members and a plurality of chips forming said semiconductor means and connected with wires soldered to said sheet members .
3. The method defined in claim 2 wherein said further step of affixing said sheet is soldered to a surface of said heat-dissipating metal plate opposite said outer surface, connections between said chips and said sheet members being made by ultrasonic soldering of aluminum wires comprises attaching said second electrically conductive sheet member to said heat-dissipating plate.
4. The method defined in claim 1 wherein said inner ends are selectively connected to wettable metal coatings on surfaces of chips forming said semiconductor means. The method defined in claim 3 wherein said step of attaching said second electrically conductive sheet member to said heat-dissipating a plate comprises soldering said second electrically conductive sheet member to said heat-dissipating plate.
5. The method defined in claim 1 wherein, after blanking of said one-piece frame and prior to the soldering of said inner ends of said strips, said inner ends of said strips are bent in a direction perpendicular to a plane of said frame. The method defined in claim 4 wherein said step of soldering said second electrically conductive sheet member to said heat-dissipating plate comprises ultrasonically bonding said second electrically conductive sheet member to said heat-dissipating plate.
6. The method defined in claim 1 wherein, after encapsulation and shearing os said temporary connections, selected ones of said strips adapted to form signal terminals are bent in a direction perpendicular to said base plate while others of said strips adapted to form power terminals are bent over the encapsulating resin in a direction parallel to said base plate. The method defined in claim 2 wherein said step of disposing a first electrically conductive sheet member on a first face of an intermediate layer comprises disposing a first electrically conductive sheet member on a first face of an alumina layer.
7. The method defined in claim 2 wherein said steps of forming said sheet of electrically conductive material comprises disposing a first sheet member comprising copper on a first face of the intermediate layer and disposing a second electrically conductive sheet member comprising copper on a second face of said intermediate layer.
8. The method defined in claim 2 further comprising disposing a plurality of additional sheet members on said first face of said intermediate layer.
9. The method defined in claim 1 wherein said inner ends of said strips are selectively connected to wettable metal coatings on surfaces of said semiconductor chip.
10. The method defined in claim 1 wherein, after forming said frame and prior to the selectively connecting of inner ends of said strips, said inner ends of said strips are bent in a direction perpendicular to a plane of said frame.
11. The method defined in claim 1 wherein said encapsulating step comprises encapsulating at least parts of said semiconductor chip, said sheet of electrically conductive material, and said inner ends of said strips with an encapsulating resin, and wherein, after encapsulation and removing of said temporary connections, selected strips of said frame are adapted to form signal terminals bent in a direction perpendicular to said heat-dissipating plate while other selected strips of said frame are strips adapted to form power terminals bent over the encapsulating resin in a direction parallel to said base heat-dissipating plate.
12. The method defined in claim 1 wherein said step of affixing said sheet to said heat-dissipating plate comprises affixing said sheet to allow heat generated by a Joule effect to be dissipated.
13. The method defined in claim 1 wherein said step of affixing said sheet to said heat-dissipating plate comprises affixing said sheet parallel to and close to said heat-dissipating plate.
14. The method defined in claim 1 wherein said step of forming a frame comprises blanking a single sheet of conductive material.
15. The method defined in claim 1 wherein said step of selectively connecting inner ends of said strips comprises soldering said inner ends of said to said sheet of electrically conductive material or to said semiconductor chip.
16. The method defined in claim 1 wherein said step of encapsulating at least parts of said semiconductor chip said sheet of electrically conductive material, and said inner ends of said strips comprises encapsulating said at least parts of said semiconductor chip, said sheet of electrically conductive material, and said inner ends of said strips with an insulator.
17. The method defined in claim 11 wherein said step of encapsulating said semiconductor chip, said sheet of electrically conductive material, and said inner ends of said strips with an insulator comprises encapsulating said at least parts with an insulating resin.
18. The method defined in claim 1 wherein said step of encapsulating at least parts of said semiconductor chip, said sheet of electrically conductive material, and said inner ends of said strips with an insulator comprises leaving said outer ends of said strips uncovered by said insulator.
19. The method defined in claim 1 wherein said step of removing said temporary connections from said strips comprises shearing said temporary connections.
20. A method for making a semiconductor package, comprising:
attaching a semiconductor device to a first surface of a substrate, said substrate having power leads on said first surface;
electrically connecting said semiconductor device to said power leads;
connecting selected leads of a lead frame with said power leads, said lead frame having a plurality of said leads temporarily attached to each other; and
encapsulating at least portions of said selected leads and said semiconductor device.
21. The method of claim 20 further comprising locating said substrate on a heat sink body prior to locating said lead frame.
22. The method of claim 20 wherein said step of attaching a semiconductor device to a first surface of a substrate comprises attaching a semiconductor device on a first surface of an insulating substrate.
23. The method of claim 22 wherein said step of attaching a semiconductor device to a first surface of an insulating substrate comprises attaching a semiconductor device on a first surface of an alumina layer.
24. The method of claim 23 wherein said step of attaching a semiconductor device to a first surface of an insulating substrate comprises providing a conductive layer on said alumina layer and locating said semiconductor device on said conductive layer.
25. The method of claim 24 wherein said step of providing a conductive layer on said alumina layer on which said semiconductor device is located comprises providing a layer comprising copper.
26. The method of claim 20 wherein said step of attaching a semiconductor device to a first surface of a substrate comprises attaching a semiconductor device to a first surface of a sandwich comprising an alumina layer having said power leads on one surface of said substrate and a conductive layer on another surface of said substrate.
27. The method of claim 26 wherein said step of attaching a semiconductor device to a first surface of a sandwich comprising an alumina layer having said power leads on one surface of said substrate and a conductive layer on another surface of said substrate comprises attaching a semiconductor device to a first surface of a sandwich comprising an alumina layer having said power leads on one surface of said substrate and a conductive layer comprising copper on another surface.
28. The method of claim 27 further comprising locating said conductive layer comprising copper a body.
29. The method of claim 20 wherein said step of attaching a semiconductor device to a first surface of a substrate comprises providing an insulating layer having three topside conductors, one of which is for carrying said semiconductor device, and two of which are for providing power contacts.
30. The method of claim 29 further providing connecting wires from said two topside conductors for providing power contacts to said semiconductor chip.
31. The method of claim 29 wherein said three topside conductors comprises copper.
32. A method for making a package containing at least one semiconductor device comprising:
fabricating a structure comprising an insulating layer and plural top conductive layers on said insulating layer;
electrically coupling a semiconductor device to at least one of said top conductive layers so that at least some of said top conductive layers can supply power to said semiconductor device;
electrically contacting plural leads to at least some of said top conductive layers; and
encapsulating at least portions of said semiconductor device and said structure.
33. The method of claim 32 wherein said insulating layer is alumina.
34. The method of claim 32 further comprising forming said semiconductor device to present power leads external to said encapsulated portions.
35. The method of claim 32 further comprising attaching a heat sink to said insulating layer with a bottom conductive layer on said insulating layer between said insulating layer and said heat sink.
36. The method of claim 35 wherein said conductive layer between said insulating layer and said heat sink comprises copper.
37. The method of claim 32 further comprising providing three topside conductors, one of which for carrying said semiconductor chip and two of which for providing power contacts.
38. The method of claim 37 further providing connecting wires from said two topside conductors for providing power contacts to said semiconductor chip.
39. The method of claim 37 wherein said three topside conductors comprise copper.
US08/558,979 1987-03-09 1995-11-13 Method for manufacturing a modular semiconductor power device Expired - Lifetime USRE37416E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/558,979 USRE37416E1 (en) 1987-03-09 1995-11-13 Method for manufacturing a modular semiconductor power device

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
IT19630/87A IT1202657B (en) 1987-03-09 1987-03-09 MANUFACTURING PROCEDURE OF A SEMICONDUCTOR MODULAR POWER DEVICE AND DEVICE WITH IT OBTAINED
IT19630A/87 1987-03-09
US16063088A 1988-02-26 1988-02-26
US07/373,647 US4926547A (en) 1987-03-09 1989-06-27 Method for manufacturing a modular semiconductor power device
US86449292A 1992-04-07 1992-04-07
US15225393A 1993-11-12 1993-11-12
US08/558,979 USRE37416E1 (en) 1987-03-09 1995-11-13 Method for manufacturing a modular semiconductor power device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US07/373,647 Reissue US4926547A (en) 1987-03-09 1989-06-27 Method for manufacturing a modular semiconductor power device

Publications (1)

Publication Number Publication Date
USRE37416E1 true USRE37416E1 (en) 2001-10-23

Family

ID=11159882

Family Applications (4)

Application Number Title Priority Date Filing Date
US07/373,647 Ceased US4926547A (en) 1987-03-09 1989-06-27 Method for manufacturing a modular semiconductor power device
US07/462,544 Ceased US5038198A (en) 1987-03-09 1990-01-09 Modular semiconductor power device
US08/184,783 Expired - Lifetime USRE38037E1 (en) 1987-03-09 1994-01-21 Modular semiconductor power device
US08/558,979 Expired - Lifetime USRE37416E1 (en) 1987-03-09 1995-11-13 Method for manufacturing a modular semiconductor power device

Family Applications Before (3)

Application Number Title Priority Date Filing Date
US07/373,647 Ceased US4926547A (en) 1987-03-09 1989-06-27 Method for manufacturing a modular semiconductor power device
US07/462,544 Ceased US5038198A (en) 1987-03-09 1990-01-09 Modular semiconductor power device
US08/184,783 Expired - Lifetime USRE38037E1 (en) 1987-03-09 1994-01-21 Modular semiconductor power device

Country Status (5)

Country Link
US (4) US4926547A (en)
EP (1) EP0282124B1 (en)
JP (1) JPS6425732A (en)
DE (1) DE3884019T2 (en)
IT (1) IT1202657B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080142938A1 (en) * 2006-12-13 2008-06-19 Stats Chippac Ltd. Integrated circuit package system employing a support structure with a recess

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1202657B (en) * 1987-03-09 1989-02-09 Sgs Microelettronica Spa MANUFACTURING PROCEDURE OF A SEMICONDUCTOR MODULAR POWER DEVICE AND DEVICE WITH IT OBTAINED
DE3837920A1 (en) * 1988-11-09 1990-05-10 Semikron Elektronik Gmbh SEMICONDUCTOR ELEMENT
JP2504610B2 (en) * 1990-07-26 1996-06-05 株式会社東芝 Power semiconductor device
US5233583A (en) * 1990-12-19 1993-08-03 General Electric Company Tracking and reading system for an optical medium and medium for use therewith
JPH05166969A (en) * 1991-10-14 1993-07-02 Fuji Electric Co Ltd Semiconductor device
US5705848A (en) * 1995-11-24 1998-01-06 Asea Brown Boveri Ag Power semiconductor module having a plurality of submodules
JP3491481B2 (en) * 1996-08-20 2004-01-26 株式会社日立製作所 Semiconductor device and manufacturing method thereof
US5736432A (en) * 1996-09-20 1998-04-07 National Semiconductor Corporation Lead frame with lead finger locking feature and method for making same
US6534851B1 (en) * 2000-08-21 2003-03-18 Agere Systems, Inc. Modular semiconductor substrates
CN118053822B (en) * 2024-04-16 2024-08-06 四川职业技术学院 Packaging structure and packaging method of power management chip

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1255073A (en) * 1969-05-20 1971-11-24 Ferranti Ltd Improvements relating to electrical circuit assemblies
US4026008A (en) * 1972-10-02 1977-05-31 Signetics Corporation Semiconductor lead structure and assembly and method for fabricating same
US4102039A (en) * 1977-02-14 1978-07-25 Motorola, Inc. Method of packaging electronic components
US4106052A (en) 1975-04-19 1978-08-08 Semikron Gesellschaft Fur Gleichrichterbau Und Elektronik M.B.H. Semiconductor rectifier unit having a base plate with means for maintaining insulating wafers in a desired position
FR2495376A1 (en) * 1980-12-02 1982-06-04 Thomson Csf Casing for power semiconductors - has base plate forming heat sink with semiconductors encapsulated hardened plastics material
GB2099742A (en) * 1981-06-05 1982-12-15 Philips Electronic Associated Bonding metals to non-metals
US4396936A (en) 1980-12-29 1983-08-02 Honeywell Information Systems, Inc. Integrated circuit chip package with improved cooling means
DE3336979A1 (en) * 1982-10-12 1984-04-26 Mitsubishi Denki K.K., Tokio/Tokyo Turn-off thyristor module
US4518982A (en) * 1981-02-27 1985-05-21 Motorola, Inc. High current package with multi-level leads
US4530152A (en) * 1982-04-01 1985-07-23 Compagnie Industrielle Des Telecommunications Cit-Alcatel Method for encapsulating semiconductor components using temporary substrates
DE3516995A1 (en) * 1984-05-11 1985-11-14 Mitsubishi Denki K.K., Tokio/Tokyo Semiconductor device
US4558510A (en) * 1983-03-31 1985-12-17 Tokyo Shibaura Denki Kabushiki Kaisha Method of producing a semiconductor device
US4615031A (en) 1982-07-27 1986-09-30 International Standard Electric Corporation Injection laser packages
US4635356A (en) * 1984-12-28 1987-01-13 Kabushiki Kaisha Toshiba Method of manufacturing a circuit module
US4675989A (en) * 1984-05-11 1987-06-30 Amp Incorporated Method of making an electrical circuit package
US4722060A (en) * 1984-03-22 1988-01-26 Thomson Components-Mostek Corporation Integrated-circuit leadframe adapted for a simultaneous bonding operation
EP0282124A2 (en) * 1987-03-09 1988-09-14 STMicroelectronics S.r.l. Method for manufacturing a modular semiconductor power device and device obtained thereby
US4783428A (en) * 1987-11-23 1988-11-08 Motorola Inc. Method of producing a thermogenetic semiconductor device
US4807018A (en) * 1985-10-10 1989-02-21 Sgs Microelettronica S.P.A. Method and package for dissipating heat generated by an integrated circuit chip

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5340991A (en) * 1976-09-21 1978-04-13 Hitachi Zosen Corp Device for buffering rocked liquid load incylindrical tank of ship
JPS6092650A (en) * 1983-10-27 1985-05-24 Toshiba Corp Semiconductor device

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1255073A (en) * 1969-05-20 1971-11-24 Ferranti Ltd Improvements relating to electrical circuit assemblies
US4026008A (en) * 1972-10-02 1977-05-31 Signetics Corporation Semiconductor lead structure and assembly and method for fabricating same
US4106052A (en) 1975-04-19 1978-08-08 Semikron Gesellschaft Fur Gleichrichterbau Und Elektronik M.B.H. Semiconductor rectifier unit having a base plate with means for maintaining insulating wafers in a desired position
US4102039A (en) * 1977-02-14 1978-07-25 Motorola, Inc. Method of packaging electronic components
FR2495376A1 (en) * 1980-12-02 1982-06-04 Thomson Csf Casing for power semiconductors - has base plate forming heat sink with semiconductors encapsulated hardened plastics material
US4396936A (en) 1980-12-29 1983-08-02 Honeywell Information Systems, Inc. Integrated circuit chip package with improved cooling means
US4518982A (en) * 1981-02-27 1985-05-21 Motorola, Inc. High current package with multi-level leads
GB2099742A (en) * 1981-06-05 1982-12-15 Philips Electronic Associated Bonding metals to non-metals
US4530152A (en) * 1982-04-01 1985-07-23 Compagnie Industrielle Des Telecommunications Cit-Alcatel Method for encapsulating semiconductor components using temporary substrates
US4615031A (en) 1982-07-27 1986-09-30 International Standard Electric Corporation Injection laser packages
DE3336979A1 (en) * 1982-10-12 1984-04-26 Mitsubishi Denki K.K., Tokio/Tokyo Turn-off thyristor module
US4558510A (en) * 1983-03-31 1985-12-17 Tokyo Shibaura Denki Kabushiki Kaisha Method of producing a semiconductor device
US4722060A (en) * 1984-03-22 1988-01-26 Thomson Components-Mostek Corporation Integrated-circuit leadframe adapted for a simultaneous bonding operation
DE3516995A1 (en) * 1984-05-11 1985-11-14 Mitsubishi Denki K.K., Tokio/Tokyo Semiconductor device
US4675989A (en) * 1984-05-11 1987-06-30 Amp Incorporated Method of making an electrical circuit package
US4635356A (en) * 1984-12-28 1987-01-13 Kabushiki Kaisha Toshiba Method of manufacturing a circuit module
US4807018A (en) * 1985-10-10 1989-02-21 Sgs Microelettronica S.P.A. Method and package for dissipating heat generated by an integrated circuit chip
EP0282124A2 (en) * 1987-03-09 1988-09-14 STMicroelectronics S.r.l. Method for manufacturing a modular semiconductor power device and device obtained thereby
US4783428A (en) * 1987-11-23 1988-11-08 Motorola Inc. Method of producing a thermogenetic semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080142938A1 (en) * 2006-12-13 2008-06-19 Stats Chippac Ltd. Integrated circuit package system employing a support structure with a recess
US8422243B2 (en) * 2006-12-13 2013-04-16 Stats Chippac Ltd. Integrated circuit package system employing a support structure with a recess

Also Published As

Publication number Publication date
JPS6425732A (en) 1989-01-27
US5038198A (en) 1991-08-06
DE3884019T2 (en) 1994-02-03
DE3884019D1 (en) 1993-10-21
USRE38037E1 (en) 2003-03-18
EP0282124A3 (en) 1989-03-22
EP0282124B1 (en) 1993-09-15
US4926547A (en) 1990-05-22
IT8719630A0 (en) 1987-03-09
IT1202657B (en) 1989-02-09
EP0282124A2 (en) 1988-09-14

Similar Documents

Publication Publication Date Title
US6028358A (en) Package for a semiconductor device and a semiconductor device
EP0352429B1 (en) High power, pluggable tape automated bonding package
JP2819285B2 (en) Stacked bottom lead semiconductor package
US4340902A (en) Semiconductor device
US8916958B2 (en) Semiconductor package with multiple chips and substrate in metal cap
JPH05211281A (en) Stepped package for electronic device
JPS6324647A (en) Semiconductor package
JPH04233262A (en) Heat-removing body, package of multiple- attachment pad lead frame and method for electric insulation of semiconductor die
KR100902766B1 (en) Discrete package having insulated ceramic heat sink
US3469017A (en) Encapsulated semiconductor device having internal shielding
USRE37416E1 (en) Method for manufacturing a modular semiconductor power device
JPH0629459A (en) Semiconductor device and manufacture thereof
US5406120A (en) Hermetically sealed semiconductor ceramic package
US6049971A (en) Casing for integrated circuit chips and method of fabrication
JP4208490B2 (en) Semiconductor power module and manufacturing method thereof
JPH0645504A (en) Semiconductor device
JP2810130B2 (en) Semiconductor package
JP3894749B2 (en) Semiconductor device
JPS63284831A (en) Manufacture of hybrid integrated circuit
US11984432B2 (en) Semiconductor chip stack module and method of fabricating the same
KR19980063740A (en) Multilayer Leadframe for Molded Packages
JP3036484B2 (en) Semiconductor device and manufacturing method thereof
JPH08172142A (en) Semiconductor package, its manufacturing method, and semiconductor device
JP2001210737A (en) Semiconductor chip package and method of manufacturing the same
JP2504262Y2 (en) Semiconductor module