JPH08172142A - Semiconductor package, its manufacturing method, and semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a reliable semiconductor package and device which has improved heat dissipation property, electrical characteristics, and shape-keeping property and can be positively packaged to a packaging substrate. CONSTITUTION: A metal substrate is used as a substrate 20 of a package, a wiring pattern 24 is deposited and formed on the one surface of the substrate 20 via an electrical insulation layer 22 and the substrate 20 and the wiring pattern 24 and the electrical insulation layer 22 are subjected to drawing in one piece at the substrate surface side where the wiring pattern 24 is formed and then a housing hole 26 for mounting a semiconductor chip is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, a method of manufacturing the same, and a semiconductor device, and more particularly to a semiconductor package having a hole for accommodating a semiconductor chip, which is excellent in heat dissipation, electrical characteristics, and reliability. The present invention relates to a product and a suitable manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, with the rapid increase in speed and functionality of ICs, there has been a demand for an IC package that is small in size, has a large number of pins, is inexpensive, and has high reliability. On the other hand, PG
Various packages such as A, QFP and BGA have been developed. Among these semiconductor packages, there is a BGA that uses solder balls as external connection terminals as a surface mount type product that can be manufactured at a relatively low cost and that can easily achieve a large number of pins. FIG. 11 shows a conventional example of a cavity-down type BGA. In this product, a storage hole 6 for storing a semiconductor chip is provided in the substrate 5 in order to reduce the thickness, and a solder ball 7 is bonded around the storage hole 6. are doing.

[0003]

In a semiconductor package of a type in which a semiconductor chip is supported by a package substrate such as PGA or the above BGA product, a cavity is required when high heat dissipation is required as the speed of IC increases. A down structure is required, and an accommodation hole for accommodating a semiconductor chip is provided in the substrate. In the manufacture of these packages, ceramic green sheets are formed in multiple layers to form storage holes, or printed circuit boards are attached or spot-machined to form storage holes.

Therefore, in manufacturing such a semiconductor package, there has been a problem that the number of manufacturing steps is conventionally large and the manufacturing method is complicated. In addition, a product using a printed circuit board having a relatively low material cost has a problem that heat dissipation from the board and reliability are poor. The present invention has been made to solve these problems, and an object thereof is to easily form a storage hole for storing a semiconductor chip, which can be formed without shaving or bonding. Therefore, the manufacturing cost can be reduced, the package characteristics such as heat dissipation and electrical characteristics are excellent, and the structure is simple, so that the semiconductor package is highly reliable, the manufacturing method thereof, and the semiconductor. It is intended to provide a device.

[0005]

The present invention has the following constitution in order to achieve the above object. That is, a metal substrate is used as a package substrate, a wiring pattern is adhered and formed on one surface of the substrate via an electrically insulating layer, and the wiring pattern is formed together with the substrate on the substrate surface side where the wiring pattern is formed. And the electrical insulating layer is integrally pressed to form a storage hole for mounting a semiconductor chip. Also, an external connection terminal is attached to an outer peripheral area of the substrate so as to be electrically connected to the wiring pattern. The inner leads of the wiring pattern are arranged so as to surround the storage hole. Further, at least one stepped portion provided with a wiring pattern via the electrically insulating layer is formed around the accommodation hole. Further, the wiring pattern is formed in a plurality of layers via an electrically insulating layer. In addition, as a method of manufacturing a semiconductor package, a wiring pattern is formed in a predetermined pattern on one surface of a metal substrate used as a substrate of the package through an electrically insulating layer, and the wiring pattern and the electrically insulating layer are formed together with the substrate. And forming a housing hole for mounting a semiconductor chip on the substrate surface side of the substrate provided with the wiring pattern. In addition, after forming a wiring pattern on the substrate, a through hole for forming a through hole is provided by using a laser beam that erases only the electrically insulating layer, and the through hole is plated with a through hole to form an interlayer wiring. It is characterized in that the pattern or the substrate and the wiring pattern are electrically connected. Further, in the semiconductor device, a semiconductor chip is mounted in the storage hole of the semiconductor package, the semiconductor chip and the wiring pattern are electrically connected, and the semiconductor chip is sealed by potting, transfer molding or a cap. Is characterized by.

[0006]

The semiconductor package according to the present invention uses a metal plate for the substrate of the package, forms a wiring pattern on the substrate via an electrically insulating layer, and squeezes the substrate integrally with the electrically insulating layer and the wiring pattern. It is obtained by forming a storage hole for a semiconductor chip by processing. Since the substrate is formed by an integral squeezing process, it can be obtained as a semiconductor package having excellent heat dissipation, electrical characteristics, and shape retention, and by squeezing a semiconductor package having a predetermined molding accuracy. it can.
The package substrate can be used as a large-capacity ground circuit, and by integrally forming it without providing a through hole on the back surface, moisture can be effectively prevented from entering from the substrate side. Further, the circuit length connecting the semiconductor chip and the external connection terminal can be shortened. For semiconductor devices, semiconductor chips are preferably sealed by potting, transfer molding, and cap sealing, and heat dissipation,
It can be provided as a highly reliable semiconductor device having excellent electrical characteristics.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a configuration of an embodiment of a semiconductor package according to the present invention and a semiconductor device in which a semiconductor chip 10 is mounted on this semiconductor package. The semiconductor package of the embodiment is characterized in that a metal plate is used as the substrate 20 of the package, and the wiring pattern 24 is formed on the substrate 20 with the electrically insulating layer 22 interposed therebetween. It is characterized in that the electrical insulating layer 22 and the wiring pattern 24 are simultaneously squeezed when the storage hole 26 of the semiconductor chip 10 is formed.

FIG. 2 is an enlarged view of the structure of the substrate 20, the electrically insulating layer 22, the wiring pattern 24, etc. in the above embodiment.
The electrically insulating layer 22 is deposited on the outer side of the housing hole 26 for mounting the semiconductor chip 10 on the substrate 20, and the wiring pattern 24 is deposited on the surface of the electrically insulating layer 22. Reference numeral 28 is an external connection terminal joined to the outer peripheral area of the substrate 20. In the embodiment, solder balls are joined as the external connection terminals 28.

The storage hole 26 for storing the semiconductor chip 10 has the electrical insulating layer 22 and the wiring pattern 2 as described above.
4, the substrate 20 is formed by squeezing, but in the embodiment, two step portions are provided between the lowermost surface for joining the semiconductor chip 10 and the joining surface 30 for joining the external connection terminals 28.
That is, the first step portion 32a and the second step portion 32b are formed. The first step portion and the second step portion are formed by a rising surface formed by raising the substrate 20 and a flat surface connecting to the semiconductor chip 10 by wire bonding. The electrically insulating layer 22 and the wiring pattern 24 have the first step portion 32 a and the second step portion 3 respectively.
It is bent to follow the shape of 2b.

FIG. 3 shows a top view of the semiconductor package of the above embodiment. The semiconductor package has a square outer shape in a plan view, and a storage hole 26 for mounting the semiconductor chip 10 therein is formed in a recessed shape in the central portion. The wiring pattern 24 is arranged so as to surround the storage hole 26, and is formed radially from the peripheral edge of the storage hole 26 toward the outer edge of the substrate 20. The bottom surface of the storage hole 26 is formed into a flat surface by squeezing as shown in FIGS. 1 and 2, and the joint surface 3 for connecting the external connection terminal 28 is formed.
0 is also formed on a flat surface.

Although a metal material can be used for the substrate 10 as appropriate, a copper or copper alloy material or an aluminum material can be preferably used in view of heat dissipation, electrical characteristics and malleability. The copper alloy material is effective not only in terms of heat dissipation properties but also in terms of processing such as squeezing. Further, the thickness of the substrate 10 may be appropriately selected and used. 0.2m as a copper plate used for the substrate 10
Those having a thickness of about m to 1.2 mm can be used. Also,
The electrical insulating layer 22 is also not particularly limited as long as it has a predetermined electrical insulating property and is a material suitable for squeezing. Polyimide is excellent in heat resistance and electrical insulation and is effective as a material for the electrical insulation layer 22.

FIG. 1 shows a state in which the semiconductor chip 10 is mounted on the semiconductor package, the semiconductor chip 10 is sealed with potting resin 36, and then a cap 38 is sealed and joined to the flat surface portion of the second step portion 32b. Is. When a metal cap is used as the cap 38, the semiconductor device has an excellent heat dissipation property because the outer surface of the semiconductor device is covered with the metal substrate 20 and the cap 38, and it is effective that moisture penetrates into the package from the outside. Therefore, the reliability of the package can be improved. In addition, since the outer surface is covered with metal, the electromagnetic shield of the package can be effectively provided.

To electrically connect the semiconductor chip 10 and the wiring pattern 24, a bonding portion is provided on the wiring pattern 24 provided on the first step portion 32a of the substrate 10, and the semiconductor chip 10 and the bonding portion are connected by wire bonding. by. Of course, instead of wire bonding, the TAB tape may be used to connect the semiconductor chip 10 and the wiring pattern. The first step portion 32a
The intermediate rising surface of the second step portion 32b acts as a dam when the potting resin 36 is potted.

FIG. 4 shows an embodiment in which a wiring pattern 24 is formed on a substrate 20 and a semiconductor package is manufactured by squeezing. FIG. 4A shows a plate material which will be the substrate 20 of the package. In the example, a copper plate having a thickness of 0.3 mm was used as the substrate 20. In order to form a circuit on this substrate 20, a copper foil 42 was adhered to the substrate 20 using an uncured polyimide film (thickness 50 μm) 40, and cured and cured (FIG. 4 (b)). Polyimide film 40 and copper foil 42
A rectangular hole is formed in accordance with the shape of the storage hole for mounting the semiconductor chip 10, and the substrate 20 is exposed at the storage hole portion.

The thickness of the polyimide film 40 used as the electrically insulating layer 22 is not particularly limited, but it is necessary to use a film without pinholes or the like so as to maintain reliable electrical insulation. When using a polyimide film, sufficient electrical insulation can be obtained even with a thin film of about 10 μm. Since the electrically insulating layer 22 can be made thinner than the thickness of the metal substrate 20, there is an advantage that the bending due to the difference in the coefficient of thermal expansion between the substrate 20 and the electrically insulating layer 22 hardly occurs. By using a thin film, it is possible to integrally form a capacitor as a circuit component between the ground and the power source in the package.

Next, the copper foil 42 is etched to form the wiring pattern 24 (FIG. 4 (c)). The wiring pattern 24 is provided with required patterns such as a bonding portion and a connection portion with an external connection terminal. Since the wiring pattern 24 is formed by etching the copper foil 42, there is an advantage that even an extremely fine pattern can be easily formed. Next, the wiring pattern 24 is subjected to nickel plating and gold plating as protective plating, and the substrate 20 is squeezed to form a storage hole 26 for semiconductor chips and a step portion. Figure 4 (d) shows the pressed product.

The squeezing work of this embodiment is the same as the working method using an ordinary press die, and is formed into a predetermined shape through a predetermined working process. The size, the depth, the height of the stepped portion, etc. of the storage hole 26 are appropriately set according to the product. By the squeezing process, a step of about 0.1 to 1.5 mm can be easily obtained, so that the semiconductor chip storage hole 2
It is easy to form 6. Although the stepped portion is one step in FIG. 4D, it is of course possible to provide two or more stepped portions. In the squeezing process, since the shape is defined by the processing die, the dimensional accuracy of the storage holes 26 and the like can be set to a high level.

The storage hole 26 is formed by applying a squeezing process.
Although displacement such as extension of the substrate 20 and extension of the wiring pattern 24 occurs at the peripheral portion of the substrate, etc., these displacements are slight. Moreover, when the wiring pattern 24 is formed, these extensions,
The pattern may be designed in advance in consideration of deformation and the like. After performing the squeezing process, external connection terminals such as solder balls are attached to the outer lead portions of the wiring pattern 24 to obtain a semiconductor package product. In addition,
Depending on the product, the solder balls may not be attached at the packaging stage, and the solder balls may be attached after the semiconductor chip 10 is mounted. Electrically insulating layer 2 of the embodiment
Since No. 2 has high heat resistance, it is possible to attach solder balls in advance using high temperature solder.

In the above embodiment, an uncured polyimide film 40 is used as a method for forming a circuit pattern on the substrate 20.
The copper foil 42 is adhered to the substrate 20 by means of the above method. Instead of adhering the polyimide film 40, a material having an electric insulation property is coated on the substrate 20 to provide the electric insulation layer 22, and the electric insulation layer 22 is provided thereon. It is also possible to form a metal layer by forming a film by a vapor deposition method, an ion plating method, a sputtering method, plating or the like.

FIG. 5 shows a second embodiment of the semiconductor package.
A bonding portion is provided on each of the first step portion 32a and the second step portion 32b, and the bonding portion provided on each flat surface and the semiconductor chip 10 are connected by wire bonding. By providing the bonding portions in a plurality of stages in this way, it becomes possible to provide a margin in the arrangement space of the bonding portions.

FIG. 6 shows the first step 32a in the second embodiment.
And the planar arrangement of each bonding portion of the second step portion 32b. As described above, the bonding portion is formed into the first step portion 32a.
By alternately arranging and the second step portion 32b, it is possible to secure a necessary bonding area within a limited area. In the embodiment shown in FIG. 5, the cap 38 is attached to the joint surface of the external connection terminal 28.

FIG. 7 shows a third embodiment of the semiconductor package.
The wiring pattern 24 is extended to the bottom surface of the storage hole 26 for mounting the semiconductor chip 10, and the bonding portion provided on the bottom surface of the storage hole 26 and the semiconductor chip 10 are connected by wire bonding. In the case of the package in which the bonding portion is arranged on the step portion as in the above-described embodiment, the rising portion of the step portion is an inclined surface, so that the distance between the semiconductor chip 10 and the bonding portion is increased to some extent. Then, when the wiring pattern 24 is extended to the bottom surface of the storage hole 26 as in the present embodiment, there is an advantage that the semiconductor chip 10 and the bonding portion can be brought close to each other and the wire length can be shortened. Further, in the case of the configuration of the present embodiment, it is not necessary to tightly incline the rising portion of the step when the substrate 20 is squeezed, and there is an advantage that the elongation and displacement of the substrate 20 due to the squeezing can be suppressed to be small. is there.

FIG. 8 shows a fourth embodiment of the semiconductor package,
The extension end of the wiring pattern 24 is stopped up to above the second step portion 32b, the substrate 20 is left exposed at the first step portion 32a close to the semiconductor chip 10, and the substrate 20 is set to the ground potential. By bonding to the step portion 32a, it is possible to easily connect to the ground potential. In this semiconductor package, since the material of the substrate 20 is metal, the substrate 20 can be easily set to the ground potential, and the semiconductor chip 10 can be easily grounded.

FIG. 9 shows a fifth embodiment of the semiconductor package,
The wiring pattern 24 provided on the substrate 20 is formed in multiple layers. The wiring pattern 24 is an electrically insulating layer 22a, 2
By laminating with 2b sandwiched, a multilayer can be formed as shown in the figure. In the embodiment, the first step portion 32a is the exposed surface of the substrate 20, the second step portion 32b is formed relatively wide, and the wiring pattern 24 is formed in two steps on the second step portion 32b. Therefore, the wire bonding part is the first
The step portion 32a and the second step portion 32b have a three-step configuration of the two-step wiring pattern 24. The substrate 20 can be used as a ground potential, the first stage of the two-step wiring pattern 24 can be used as a signal line, and the second stage can be used as a power line.

When solder balls are joined as the external connection terminals 28 in a package in which the wiring patterns 24 are formed in multiple layers, the wiring patterns 2 other than the through holes are usually formed on the surface layer.
However, in the package of this embodiment, since the electrically insulating layer 22 can be formed extremely thin, it is possible to join the solder ball to the blind through hole. If you need to adjust the height of the through hole,
For example, the size of the solder ball pad may be adjusted.

Further, when the wiring pattern 24 is formed in multiple layers on the substrate 20, the electrical connection between layers is made by the through holes 23a and 23b as shown in FIG. 9, but the wiring pattern 24 is formed on the substrate 20 in this way. The following method is suitable for forming multiple layers. That is, similar to the above-described method, the wiring pattern 24 is formed in multiple layers on the substrate 20 with a predetermined pattern by the polyimide film or the like via the electrically insulating layers 22a and 22b, and the electrically insulating layer 2 is cured.
2a and 22b are hardened. Next, a through hole for forming a through hole is provided by irradiating a laser beam from above the film surface on which the multilayer is formed.

Since the portion of the wiring pattern 24 where the through hole is formed is predetermined, the portion where the through hole is formed is removed when the wiring pattern 24 of the surface layer is etched to form a pattern. Therefore, it is possible to easily form a through hole that leads from the surface of the electrically insulating layer to the underlying wiring pattern 24 or the substrate 20 by using a laser beam that erases only the electrically insulating layer. FIG. 9 shows a through hole 23 a that leads from the surface layer to the lowermost substrate 20 and a through hole 23 b that leads to the intermediate wiring pattern 24.

The method of forming a through hole for a through hole by using a laser beam has a variation in the thickness of the electrically insulating layer as compared with, for example, a method of forming a through hole with a drill after forming the wiring pattern 24 in multiple layers. However, there is an advantage that the through hole can be accurately and efficiently formed up to the position of the lower conductor layer. After forming the through holes, through hole plating is performed as in the conventional method to electrically connect the lower conductor layer and the wiring pattern 24 on the surface. It should be noted that the method of forming the through hole using the laser beam can be applied to the case of providing the single-layer wiring pattern 24 as well.

FIG. 10 shows, as a sixth embodiment of the semiconductor package, an example in which the semiconductor chip 10 is mounted by a so-called flip chip method. In this embodiment, the electrical insulating layer 22 and the wiring pattern 24 are formed by extending from the joint surface of the external connection terminal 28 of the substrate 20 to the bottom surface of the housing hole 26 of the semiconductor chip 10, and the inner lead portion of the wiring pattern 24 is formed. It is formed according to the bump arrangement of the semiconductor chip 10. As a result, the semiconductor chip 10 can be mounted by the flip chip method.

The embodiments of the semiconductor package have been described above. However, since the semiconductor package according to the present invention is formed by squeezing the substrate 20 of a metal plate, a method of forming a storage hole by shaving or bonding. It makes packaging much easier to manufacture. Further, there is an advantage that the shape retention of the package can be improved by processing the substrate 20. That is, the strength of the package, especially the semiconductor chip 10 is reduced by processing the flat substrate 20.
It is possible to improve the strength of the mounting portion of the, and it is possible to improve the reliability of the package.

On the other hand, looking at the portion of the substrate 20 where the external connection terminals are attached in the outer peripheral area of the storage hole 26,
The outer peripheral area portion is more flexible than the squeezed portion, but the fact that the outer peripheral portion of the substrate 20 is flexible in this way means that it is between the package and the mounting substrate when the semiconductor device is mounted. This is effective in that the thermal stress and the like generated in step 1 can be effectively released. That is, in the semiconductor package of the embodiment, the storage hole 26 portion for mounting the semiconductor chip is firmly formed to surely support the semiconductor chip, and the connection portion with the mounting board has some flexibility. Thus, it becomes possible to release the deformation stress, thermal stress, and the like due to bending, and to perform highly reliable mounting.

Further, since the shape retention of the substrate 20 is improved as described above, the substrate 20 can be made of a thin material, and the package can be made thinner. Further, since the metal plate is used for the substrate 20 and the drawing process is performed, the flatness of the underlying surface on which the wiring pattern 24 is formed is improved, and the electrically insulating layer 22 and the wiring pattern 24 formed on the substrate 20 are thin. it can. This makes it easy to form a fine pattern.

Further, as shown in the embodiment, the wiring pattern 2
4 is provided only on the side of the substrate 20 on which the semiconductor chip is mounted, and wiring patterns are not provided on both sides of the substrate 20 so that the wiring pattern is not routed between the front and back sides.
The length of the wiring pattern 24 from 0 to the external connection terminal 28 can be shortened. In addition, since the wiring pattern 24 is provided on one surface of the substrate 20 and no through hole is provided in the substrate 20, the sealing property of the substrate 20 is improved and water is completely prevented from entering from the substrate 20 side. Will be possible.

When the semiconductor chip 10 is mounted on the above-described semiconductor package to form a semiconductor device, the semiconductor chip 10 and the wiring pattern 24 are wire-bonded or TAB is used as described above, or the flip-chip method is used. After the connection, the semiconductor chip 10 is sealed by potting or the like, and the cap 38 is sealed. Of course, instead of the potting resin, the transfer molding method can be used, and the cap 38 can be used without potting.

The obtained semiconductor device is the substrate 2 of the package.
Since 0 is a metal plate, it is excellent in shape retention and has suitable heat dissipation. As shown in FIG. 1, when the semiconductor chip 10 is directly mounted on the substrate 20 by bonding, heat conduction from the semiconductor chip 10 to the substrate 20 is effectively performed.
Heat is dissipated from the entire substrate 20. Of course, it is also possible to attach a radiation fin to the substrate 20 in order to further enhance heat dissipation.

Since the semiconductor device according to the present invention can appropriately set the shape, arrangement, etc. of the wiring pattern 24, the wiring pattern 24 and the like can be formed according to the product, and can be applied to products according to various uses. . For example, it can be applied not only to a package mounting a single semiconductor chip but also to a package for MCM mounting a plurality of semiconductor chips.

[0037]

The semiconductor package according to the present invention can be provided as a product excellent in heat dissipation, electrical characteristics, insulation reliability, shape retention, and the like, and has a storage hole for mounting a semiconductor chip. The semiconductor package can be manufactured with high accuracy and easily. Further, according to the method of manufacturing the semiconductor package of the present invention, the semiconductor package can be manufactured appropriately. In addition, the semiconductor device according to the present invention has a remarkable effect that it can be provided as a product excellent in heat dissipation, electrical characteristics, sealing properties, and the like.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor package and a semiconductor device according to the present invention.

FIG. 2 is an explanatory diagram showing a configuration of an electrically insulating layer and a wiring pattern formed on a substrate.

FIG. 3 is an explanatory diagram showing a planar arrangement of a storage hole for a semiconductor chip, a wiring pattern, and the like.

FIG. 4 is an explanatory diagram showing an example of a method of manufacturing a semiconductor package.

FIG. 5 is an explanatory diagram showing a second embodiment of the semiconductor package.

FIG. 6 is an explanatory diagram showing a planar arrangement of bonding portions formed on the step portion.

FIG. 7 is an explanatory diagram showing a third embodiment of the semiconductor package.

FIG. 8 is an explanatory view showing a fourth embodiment of the semiconductor package.

FIG. 9 is an explanatory view showing a fifth embodiment of the semiconductor package.

FIG. 10 is an explanatory view showing a sixth embodiment of the semiconductor package.

FIG. 11 is a sectional view of a conventional example of a semiconductor package.

[Explanation of symbols]

 10 Semiconductor Chip 20 Substrate 22 Electrical Insulating Layer 24 Wiring Pattern 26 Storage Hole 28 External Connection Terminal 30 Bonding Surface 32a First Step Part 32b Second Step Part 38 Cap 40 Polyimide Film 42 Copper Foil

Claims (8)

[Claims] 1. A metal substrate is used as a package substrate, and a wiring pattern is adhered and formed on one surface of the substrate via an electrically insulating layer, and the substrate surface side on which the wiring pattern is formed together with the substrate. A semiconductor package, wherein the wiring pattern and the electrically insulating layer are integrally pressed to form a storage hole for mounting a semiconductor chip. 2. The semiconductor package according to claim 1, wherein an external connection terminal is attached to an outer peripheral area of the substrate so as to be electrically connected to the wiring pattern. 3. The semiconductor package according to claim 1, wherein inner leads of the wiring pattern are arranged so as to surround the storage hole. 4. At least one stepped portion provided with a wiring pattern around the accommodation hole via the electrically insulating layer.
The semiconductor package according to claim 1, wherein the semiconductor package is stepwise formed. 5. The semiconductor package according to claim 1, wherein the wiring pattern is formed in a plurality of layers with an electrically insulating layer interposed therebetween. 6. A wiring pattern is formed in a predetermined pattern on one surface of a metal substrate used as a package substrate, and the wiring pattern and the electrically insulating layer are integrated together with the substrate. A method of manufacturing a semiconductor package, characterized by forming a storage hole for mounting a semiconductor chip on the substrate surface side of the substrate provided with the wiring pattern. 7. After forming a wiring pattern on the substrate, a through hole for forming a through hole is provided by using a laser beam that erases only the electrically insulating layer, and the through hole is plated with a through hole. 7. The method of manufacturing a semiconductor package according to claim 6, wherein the wiring pattern between layers or the substrate and the wiring pattern are electrically connected. 8. A semiconductor chip is mounted in the storage hole of the semiconductor package according to claim 1,
A semiconductor device, wherein a semiconductor chip and the wiring pattern are electrically connected, and the semiconductor chip is sealed by potting, transfer molding or a cap.