US20090309679A1 - Connection method and substrate - Google Patents

Connection method and substrate Download PDF

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Publication number
US20090309679A1
US20090309679A1 US12/474,531 US47453109A US2009309679A1 US 20090309679 A1 US20090309679 A1 US 20090309679A1 US 47453109 A US47453109 A US 47453109A US 2009309679 A1 US2009309679 A1 US 2009309679A1
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United States
Prior art keywords
line
substrate
points
dielectric
connection
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US12/474,531
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English (en)
Inventor
Masato Kikuchi
Shunsuke Mochizuki
Masahiro Yoshioka
Ryosuke Araki
Masaki Handa
Takashi Nakanishi
Hiroshi Ichiki
Tetsujiro Kondo
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Sony Corp
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Sony Corp
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Assigned to SONY CORPORATION reassignment SONY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KONDO, TETSUJIRO, NAKANISHI, TAKASHI, ARAKI, RYOSUKE, HANDA, MASAKI, ICHIKI, HIROSHI, YOSHIOKA, MASAHIRO, MOCHIZUKI, SHUNSUKE, KIKUCHI, MASATO
Publication of US20090309679A1 publication Critical patent/US20090309679A1/en
Priority to US13/431,698 priority Critical patent/US8334730B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/003—Coplanar lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/026—Coplanar striplines [CPS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/08—Microstrips; Strip lines
    • H01P3/081—Microstriplines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/08—Microstrips; Strip lines
    • H01P3/085—Triplate lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
    • H01P5/022—Transitions between lines of the same kind and shape, but with different dimensions
    • H01P5/028—Transitions between lines of the same kind and shape, but with different dimensions between strip lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0248—Skew reduction or using delay lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components

Definitions

  • the present invention relates to a connection method and a substrate. More particularly, the present invention relates to a connection method capable of reducing reflection due to impedance unmatching in a connection part and satisfactorily maintaining signal quality in a case where, for example, electronic parts are to be mounted on a substrate, and to a substrate for use therewith.
  • Connection structures between parts and substrates are broadly divided into the following two types.
  • One type is a completely shielded structure like a coaxial cable, and the other type is an open structure in which inductive capacity exists between signal lines like wiring on a substrate.
  • wiring By forming wiring to be a line structure like a microstrip, it is possible to adjust impedance so as to deal with a high-speed signal.
  • connection method including the step of connecting, using a line on a dielectric element, two points through which a signal flows, the two points having different heights and the widths of the line at the positions of the two points having been adjusted on the basis of the thickness of the dielectric element.
  • a higher point of the two points may be a point on a line of an electronic part mounted on a substrate, and a lower point of the two points may be a point on a line of the substrate.
  • An area along which the thickness of the dielectric element decreases toward a connection part with the line of the substrate may be formed in the end portion of the electronic part composed of a dielectric material, and the two points having different heights may be connected by a line disposed along the area.
  • Steps at which the thickness of the dielectric element decreases toward a connection part with a line of the substrate may be formed in the end portion of the electronic part composed of a dielectric material, and the two points having different heights may be connected by a line disposed on the steps.
  • a substrate wherein two points through which a signal flows, are connected using a line on a dielectric element, the two points having different heights and the widths of the line at the positions of the two points having been adjusted on the basis of the thickness of the dielectric element.
  • a higher point of the two points may be a point on a line of an electronic part mounted on a substrate, and a lower point of the two points may be a point on a line of the substrate.
  • An area along which the thickness of the dielectric element decreases toward a connection part with the line of the substrate may be formed in the end portion of the electronic part composed of a dielectric material, and the two points having different heights may be connected by a line disposed along the area.
  • Steps at which the thickness of the dielectric decreases toward a connection part with the line of the substrate may be formed in the end portion of the electronic part composed of a dielectric material, and the two points having different heights may be connected by a line disposed on the steps.
  • connection part it is possible to reduce reflection due to impedance unmatching in a connection part and satisfactorily maintain signal quality in a case where, for example, electronic parts are to be mounted on a substrate.
  • FIG. 1 shows a method for connecting an electronic part and a substrate according to the related art
  • FIG. 2 shows the structure of a surface mount part according to the related art
  • FIG. 3 shows another configuration of a surface mount part according to the related art
  • FIG. 4 shows an example of the configuration including a substrate and a surface mount part that is connected by a connection method according to an embodiment of the present invention
  • FIG. 5 is a sectional view of the structure shown in FIG. 4 ;
  • FIG. 6 is a view when the structure shown in FIG. 4 is viewed from directly above;
  • FIG. 7 shows an image in which discontinuous changes in impedance can be eliminated
  • FIG. 8 shows an example of a case in which a coplanar line is used as a line forming a connection part
  • FIGS. 9A and 9B show a dotted-line portion of FIG. 8 ;
  • FIGS. 10A and 10B show a microstrip line
  • FIG. 11 shows results of calculations of characteristic impedance in a case where a microstrip line structure is adopted
  • FIG. 12 shows examples of lines forming a connection part between a substrate and an electronic part
  • FIG. 13 shows another example of the configuration of the connection part
  • FIG. 14 shows still another example of the configuration of the connection part
  • FIGS. 15A , 15 B, 15 C, and 15 D show examples of surface mount parts
  • FIG. 16 shows a microstrip line model
  • FIG. 17A is a front view of the model of FIG. 16 ;
  • FIG. 17B is a sectional view of the model of FIG. 16 ;
  • FIG. 18 shows a transmission simulation result
  • FIG. 19 shows a model in which substrates having different heights are connected by the present connection method
  • FIG. 20 shows a model in which substrates having different heights are connected using a through hole
  • FIG. 21 shows a model in which substrates having different heights are connected using wire bonding
  • FIG. 22 is a view showing conditions for a model
  • FIG. 23 is another view showing conditions for a model
  • FIG. 24 shows simulation results
  • FIG. 25 shows S21 components at each of frequencies 3 GHz, 6 GHz, and 10 GHz;
  • FIGS. 26A and 26B show an example of the shape of a line on an electronic part side
  • FIGS. 27A and 27B show another example of the shape of the line on the electronic part side
  • FIGS. 28A and 28B show still another example of the shape of the line on the electronic part side
  • FIGS. 29A and 29B show an example of the shape of the line on the electronic part side
  • FIGS. 30A and 30B show another example of the shape of the line on the electronic part side
  • FIG. 31 is a perspective view showing an example of connection in a case where the number of dielectric layers of an electronic part is two;
  • FIG. 32 is a sectional view of the structure shown in FIG. 31 ;
  • FIG. 33 is a perspective view showing an example of a case in which the present connection method is used for connection of a semiconductor package.
  • FIG. 4 is a perspective view showing an example of the configuration including a substrate 1 and a surface mount part 2 , which are connected by a connection method according to an embodiment of the present invention.
  • FIG. 5 is a sectional view showing the structure shown in FIG. 4 .
  • FIG. 6 is a front view when the structure shown in FIG. 4 is viewed from directly above.
  • connection part between the substrate 1 and the surface mount part 2 which are connected by this connection method, is formed in such a manner that a terminal end part that is extended as is kept to be a line shape from the top surface (the surface in parallel with the surface of the substrate 1 ) of the surface mount part 2 is connected to a line 1 A disposed on the substrate 1 .
  • connection method lies in that, as shown in such a manner as to be enclosed using a dotted line of FIG. 5 , by forming a dielectric end 2 A of the surface mount part 2 so as to be a slope, the substrate 1 and the surface mount part 2 are connected to each other while a metal transmission line disposed in a dielectric element along the slope is made to gradually approach the substrate 1 .
  • the surface mount part 2 has a shape such that the cross section thereof in the vertical direction is a trapezoid.
  • the line width of a microstrip line on the side of the surface mount part 2 is adjusted by the characteristic impedance determined from electrical characteristics thereof and the geometric shape thereof.
  • the nearer to the substrate 1 that is, the smaller the height of a position relative to the substrate 1 used as a reference and the smaller the thickness of the dielectric element of the slope on which the surface mount part 2 is mounted, the smaller the line width.
  • the width in the connection part between the line disposed in the dielectric end 2 A and the line 1 A on the substrate 1 is the same as the width of the line 1 A.
  • FIG. 7 An image of capable of eliminating discontinuous changes of characteristic impedance in the connection part and reducing reflection components is shown in FIG. 7 .
  • the recessed portion shows characteristic impedance of a portion (portion floating in air), which is not in contact with the electronic part or the substrate, of the terminal shown in FIGS. 1 , 2 and 3 , through which the electronic part is connected to the substrate.
  • the characteristic impedance in the microstrip line is determined on the basis of Expressions (1A), (1B), (2A), and (2B) described below.
  • Z 0 is the characteristic impedance
  • ⁇ e is the effective dielectric constant
  • ⁇ r is the relative dielectric constant
  • W is the line width
  • d is the dielectric thickness
  • the calculation result of the characteristic impedance in a case where a microstrip line structure is adopted is shown in FIG. 11 .
  • FIG. 12 shows, as lines forming a connection part between a substrate and an electronic part, a strip line, a microstrip line, a strip line, a coplanar line, and a parallel line.
  • FIG. 8 shows an example of a case in which a coplanar line is used as a line forming a connection part between the substrate 1 and the surface mount part 2 .
  • a coplanar line can be used as a line forming a connection part in this manner.
  • FIG. 9A is a sectional view showing a portion enclosed using a dotted line in FIG. 8 .
  • FIG. 9B is a front view showing the top surface of an electronic part of FIG. 8 .
  • the closer the line disposed on the slope to the connection part with the substrate the larger the width of the line.
  • a common substrate material is used.
  • a metal conductor such as, for example, copper
  • a dielectric part for example, phenol, a glass epoxy resin, alumina, or Teflon (registered trademark) is used.
  • connection method can be applied to a case in which the entirety of electronic parts, such as an antenna and an LSI, which are surface mounted on a substrate, is connected onto the substrate.
  • a connection method in which, in the manner described above, at least a part of the side surface of a dielectric element forming the surface mount part 2 is formed as a slope, and a conductor is wired along the slope, thereby connecting the electronic part to the wiring on the substrate will be referred to simply as the present connection method as appropriate.
  • connection method in a case where electronic parts, such as an antenna and a filter circuit, are to be surface mounted onto a substrate that handles a high-speed signal, such as a radio frequency (RF) signal, it becomes possible to reduce reflection due to impedance unmatching in the connection part and to satisfactorily maintain signal quality.
  • the high-speed signal herein refers to a signal having a connection length or a wiring length that exceeds 1/10 of the wavelength of the transmission signal at the maximum frequency.
  • connection line can be handled as a distributed constant circuit.
  • the connection line may be a microstrip line, a strip line, a coplanar line, or a parallel line as long as impedance can be adjusted.
  • the physical shape of the line width of the connection part may be discontinuous as long as impedance is continuously changed in an electrical manner.
  • a rate of change in the impedance at the line length with respect to the wavelength of the transmission frequency becomes a measure.
  • connection part may be configured in such a manner that, even though the entire dielectric end 2 A forming the side surface of the surface mount part 2 as shown in FIG. 4 is not obliquely provided, a part of the side surface thereof may be formed so as to be a slope as shown in FIG. 13 , and the line whose width has been adjusted may be wired on the slope.
  • a through hole may be obliquely provided in the end surface as shown in FIG. 14 , and a line whose width has been adjusted may be wired in the inner side thereof.
  • various parts such as a filter circuit, a resonance circuit, a mixer circuit, and a splitter circuit, shown in FIGS. 15A to 15D , can be used.
  • the present connection method can be applied to not only the connection between a printed wiring substrate and a surface mount part, but also to wiring between parts, wiring between substrates, wiring inside parts, wiring of a multilayered substrate, and semiconductor wiring.
  • the present connection method is effective for wiring inside a multilayered substrate or parts, or effective for wiring connection inside a semiconductor package.
  • the present connection method is effective for a connection between substrates, which handle a high-speed signal, such as in the case of an RF circuit, and parts.
  • the present connection method can be realized using a simple line structure, such as a microstrip line or a coplanar line, and an extra circuit, a connector, and the like are not necessary.
  • the present connection method can be applied to not only surface mount parts, such as a filter and an antenna, but also to overall parts (wiring inside a multilayered substrate, a semiconductor package, or the like) in which an inductive capacity exists between signal lines.
  • FIG. 16 shows a model in a three-dimensional manner.
  • FIG. 17A is a front view of the model of FIG. 16
  • FIG. 17B is a sectional view of the model of FIG. 16 .
  • This model is formed by a signal line, a dielectric substrate, and a GND (formed in such a manner that a signal line is disposed on a substrate formed of a GND layer and a dielectric layer).
  • a test signal is input from an input port, and the transmitted signal is observed at an output port.
  • dB decibel
  • an S-parameter represented by the following Expression (3) is used as S21.
  • the transmission simulation result is shown in FIG. 18 .
  • the horizontal axis of FIG. 18 shows the frequency [GHz], and the vertical axis shows S21 [dB]. As the frequency increases, S21 is slightly decreased. Since the material of the line model is homogenous and the shape of the cross section thereof is fixed, the deterioration is considered to be mainly caused by induced loss of a signal that is transmitted through the substrate. Therefore, in this model in a state close to an ideal state in which impedance matching has been achieved, transmission deterioration is approximately ⁇ 1 dB@10 GHz.
  • FIG. 19 shows a model in which substrates having different heights are connected to each other using the present connection method.
  • FIGS. 20 and 21 each show a model in which substrates having different heights are connected to each other by using a through hole and wire bonding, respectively.
  • FIGS. 22 and 23 show conditions of models shown in FIGS. 19 , 20 and 21 .
  • the models shown in FIGS. 19 , 20 and 21 are such that the section between a position P 1 in a signal line A of a substrate A and a position P 2 in a signal line B of a substrate B arranged so as to overlap the substrate A (dielectric element A), which is indicated by being enclosed using a dotted line in FIG. 22 , are connected by the present connection method, a through hole, and wire bonding, respectively.
  • the conditions of the substrate A configured in such a manner that the dielectric element A is laminated on the GND surface A and the signal line A is disposed on the input side on the dielectric element A, and the substrate B configured in such a manner that the dielectric element B is laminated on the GND surface B and the signal line B is disposed on the dielectric element B are shown in FIG. 23 .
  • the line widths of the signal lines A and B are set to 3.2 mm, the height is set to 0.2 mm, and the total of the line lengths of the signal lines A and B is set to 30 mm.
  • the height of the dielectric elements A and B is set to 1.6 mm, the dielectric constant is set to 7.1 ⁇ 10 ⁇ 12 [F/m], and the induced loss when a signal of 10 GHz is made to flow is set to 0.005.
  • FIG. 24 The results of simulation performed by each connection method under the conditions shown in FIG. 23 are shown in FIG. 24 .
  • the horizontal axis of FIG. 24 indicates the frequency [GHz], and the vertical axis indicates S21 [dB].
  • the values of S21 [dB] at each frequency of 3 GHz, 6 GHz, and 10 GHz are shown in FIG. 25 .
  • FIG. 26A is a front view showing a first shape.
  • FIG. 26B is a sectional view of the structure shown in FIG. 26A .
  • the first shape shown in FIGS. 26A and 26B is the same as that described with reference to FIGS. 4 to 6 . That is, as shown in FIG. 26B , a slope is formed in the end portion of an electronic part, and a line 21 B, which is a part of a line on the electronic part side, is disposed along the slope. The thickness of the dielectric element 22 on the electronic part side at each position of the line 21 B decreases linearly as the line approaches the connection part with the line 11 on the substrate side.
  • the shape when the line 21 B is viewed from directly above is, as shown in FIG. 26A , formed so as to be symmetrical about the axis in the length direction of the line 21 B, and the width is changed linearly between a width W 2 and a width W 1 according to the thickness of the dielectric element 22 at each position.
  • the width W 1 is the width of the line 21 A disposed on the top surface of the dielectric element 22 on the electronic part side
  • the width W 2 is the width of the line 11 A disposed in the dielectric element 12 on the substrate side.
  • FIG. 27A is a front view showing a second shape.
  • FIG. 27B is a sectional view of the structure shown in FIG. 27A .
  • the line 21 B which is a part of a line on the electronic part side, is disposed on these steps.
  • the thickness of the dielectric element 22 on the electronic part side at each position of the line 21 B decreases in a step-like manner as the line approaches the connection part with the line 11 on the substrate side and as the number of steps from the substrate decreases.
  • the shape when the line 21 B is viewed from directly above is, as shown in FIG. 27A , formed symmetrical about the axis of the line 21 B in the length direction, and the width is changed in a step-like manner from the width W 2 to the width W 1 according to the thickness of the dielectric element 22 at each position.
  • FIG. 28A is a front view showing a third shape.
  • FIG. 28B is a sectional view of the structure shown in FIG. 28A .
  • a curved surface whose cross section is formed nearly in a fan shape is formed in the end portion of the electronic part.
  • the line 21 B which is a part of the line on the electronic part side, is disposed along this curved surface.
  • the thickness of the dielectric element 22 on the electronic part side at each position of the line 21 B decreases as the line approaches the connection part with the line 11 on the substrate side.
  • the shape when the line 21 B is viewed from directly above is, as shown in FIG. 28A , formed in a shape symmetrical about the axis of the line 21 B in the length direction, and the width is changed at a predetermined ratio between a width W 2 and a width W 1 .
  • FIG. 29A is a front view showing a fourth shape.
  • FIG. 29B is a sectional view of the structure shown in FIG. 29A .
  • the shape shown in FIG. 29A is the same as the shape described with reference to FIG. 26A .
  • the line 21 B is formed in a shape symmetrical about the axis of the line 21 B in the length direction, and the width is changed linearly between a width W 2 and a width W 1 according to the thickness of the dielectric element 22 at each position.
  • FIG. 29B The shape shown in FIG. 29B is the same as the shape described with reference to FIG. 27B .
  • Five steps are formed in the end portion of an electronic part, and the line 21 B, which is a part of the line on the electronic part side, is disposed on these steps.
  • the thickness of the dielectric element 22 on the electronic part side at each position of the line 21 B decreases in a step-like manner as the line approaches the connection part with the line 11 on the substrate side and as the number of steps from the substrate decreases.
  • FIG. 30A is a front view showing a fifth shape.
  • FIG. 30B is a sectional view of the structure shown in FIG. 30A .
  • the shape shown in FIG. 30A is the same as the shape described with reference to FIG. 27A .
  • the line 21 B is formed in a shape symmetrical about the axis of the line 21 B in the length direction, and the width thereof is changed in a step-like manner between a width W 2 and a width W 1 according to the thickness of the dielectric element 22 at each position.
  • FIG. 30B The shape shown in FIG. 30B is the same as the shape described with reference to FIG. 26B .
  • a slope is formed in the end portion of the electronic part, and the line 21 B, which is a part of the line on the electronic part side, is disposed along the slope.
  • the thickness of the dielectric element 22 on the electronic part side at each position of the line 21 B decreases linearly as the line approaches the connection part with the line 11 on the substrate side.
  • FIG. 31 is a perspective view showing an example of connection in a case where the number of dielectric layers of the electronic part is two.
  • the same components as those shown in FIG. 26 are designated with the same reference numerals.
  • dielectric elements 22 A and 22 B are used in a stacked manner.
  • a line 21 A is disposed on the top surface of a dielectric element 22 B, which is an upper layer, and a line 21 B is disposed in the slope.
  • a GND surface 31 is sandwiched between the dielectric elements 22 A and 22 B.
  • the width of the line 21 B disposed in the slope of the dielectric element 22 B is set to a fixed width.
  • FIG. 32 is a sectional view of the structure shown in FIG. 31 .
  • the slope of the dielectric element 22 A has an angle that is the same as the slope of the dielectric element 22 B with respect to the substrate surface.
  • the thickness of the dielectric element 22 B at each position of the line 21 B is adjusted using the GND surface 31 so that the thickness becomes fixed from the position P 11 that is directly above the boundary between the top surface and the slope of the dielectric element 22 A up to the position P 12 that is directly above the boundary between the top surface and the slope of the dielectric element 22 A.
  • the thickness of the dielectric layer gradually decreases from the position P 12 toward the connection part with the substrate.
  • the present connection method can be applied to various cases in which two points having different heights are connected, for example, not only a case in which a line on an electronic part is connected to a line on a substrate on which the electronic part is mounted, but also a case in which a line on a substrate is connected to a line on another substrate.
  • FIG. 33 is a perspective view showing an example of a case in which the present connection method is used for the connection of a semiconductor package.
  • a semiconductor package 61 is mounted on a substrate 51 , and a chip part 62 , such as an LSI (Large Scale Integration) IC, is mounted thereon. Both the semiconductor package 61 and the chip part 62 have a shape in which the cross section thereof in the vertical direction is formed in the shape of a trapezoid. A plurality of electrodes 62 A are provided on the top surface of the chip part 62 in such a manner as to be exposed.
  • LSI Large Scale Integration
  • Wiring employing the present connection method can be applied to wiring 63 between a line disposed on the top surface of the chip part 62 from the electrode 62 A and a line on the top surface of the semiconductor package 61 and to wiring 64 between a line on the top surface of the semiconductor package 61 and a line on the substrate.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Waveguides (AREA)
  • Structure Of Printed Boards (AREA)
  • Waveguide Connection Structure (AREA)
US12/474,531 2008-06-13 2009-05-29 Connection method and substrate Abandoned US20090309679A1 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9204530B2 (en) 2010-10-25 2015-12-01 Panasonic Corporation Electronic components assembly
US9478839B2 (en) 2012-03-28 2016-10-25 Fujikura Ltd. Wiring board
US9974160B1 (en) * 2016-12-28 2018-05-15 Raytheon Company Interconnection system for a multilayered radio frequency circuit and method of fabrication
WO2018157892A1 (de) * 2017-02-28 2018-09-07 Continental Teves Ag & Co. Ohg Mehrebenen-schaltungsträger
US20230170603A1 (en) * 2021-11-26 2023-06-01 Innolux Corporation Electronic device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6135358B2 (ja) * 2013-07-24 2017-05-31 日本電気株式会社 アンテナ及びアンテナの製造方法
CN207166874U (zh) * 2014-08-29 2018-03-30 株式会社村田制作所 多层电路基板
JP6352839B2 (ja) * 2015-03-10 2018-07-04 日本電信電話株式会社 高周波パッケージ
US9867294B2 (en) * 2015-05-22 2018-01-09 Ciena Corporation Multi-width waveguides
US20170085243A1 (en) * 2015-09-21 2017-03-23 Intel Corporation Impedance matching interconnect

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5184095A (en) * 1991-07-31 1993-02-02 Hughes Aircraft Company Constant impedance transition between transmission structures of different dimensions
US6331806B1 (en) * 1996-04-24 2001-12-18 Honda Giken Kogyo Kabushiki Kaisha Microwave circuit package and edge conductor structure
US6737931B2 (en) * 2002-07-19 2004-05-18 Agilent Technologies, Inc. Device interconnects and methods of making the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2708669B2 (ja) 1992-07-01 1998-02-04 三菱電機株式会社 連続鋼板処理ラインの切断制御装置
JPH0615310U (ja) * 1992-07-28 1994-02-25 株式会社東芝 高周波回路基板
JP2000216510A (ja) 1999-01-25 2000-08-04 Nec Corp プリント配線板及びその製造方法並びにプリント配線板におけるコネクタインダクタンス要因の波形歪み低減法
FI106414B (fi) * 1999-02-02 2001-01-31 Nokia Networks Oy Laajakaistainen impedanssisovitin

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5184095A (en) * 1991-07-31 1993-02-02 Hughes Aircraft Company Constant impedance transition between transmission structures of different dimensions
US6331806B1 (en) * 1996-04-24 2001-12-18 Honda Giken Kogyo Kabushiki Kaisha Microwave circuit package and edge conductor structure
US6737931B2 (en) * 2002-07-19 2004-05-18 Agilent Technologies, Inc. Device interconnects and methods of making the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9204530B2 (en) 2010-10-25 2015-12-01 Panasonic Corporation Electronic components assembly
US9478839B2 (en) 2012-03-28 2016-10-25 Fujikura Ltd. Wiring board
US9974160B1 (en) * 2016-12-28 2018-05-15 Raytheon Company Interconnection system for a multilayered radio frequency circuit and method of fabrication
WO2018157892A1 (de) * 2017-02-28 2018-09-07 Continental Teves Ag & Co. Ohg Mehrebenen-schaltungsträger
US20230170603A1 (en) * 2021-11-26 2023-06-01 Innolux Corporation Electronic device

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JP2010021505A (ja) 2010-01-28
KR20090129957A (ko) 2009-12-17
US8334730B2 (en) 2012-12-18
JP4656212B2 (ja) 2011-03-23
US20120182083A1 (en) 2012-07-19

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