TWI839005B

TWI839005B - Amplifying circuit

Info

Publication number: TWI839005B
Application number: TW111146684A
Authority: TW
Inventors: 陳智聖; 趙宇軒
Original assignee: 立積電子股份有限公司
Priority date: 2022-12-02
Filing date: 2022-12-06
Publication date: 2024-04-11
Also published as: TW202425523A

Abstract

An amplifying circuit includes a first transistor, a second transistor and a switching device. A control end of the first transistor is coupled to an input terminal of the amplifying circuit, a first end of the first transistor is coupled to a first reference end, where the input terminal of the amplifying circuit receives a first radio frequency (RF) signal. A first end of the second transistor is coupled to a second end of the first transistor, a second end of the second transistor is coupled to an output terminal of the amplifying circuit, where the output terminal of the amplifying circuit outputs an amplified signal. The first transistor amplifies the first RF signal to generate a second RF signal. The switching device performs a switching operation to transmit the second RF signal to one of the first end and the control end of the second transistor.

Description

Amplifier circuit

本發明是有關於一種放大電路，且特別是有關於一種可在兩種不同的工作模式間進行切換的放大電路。 The present invention relates to an amplifier circuit, and in particular to an amplifier circuit that can switch between two different operating modes.

在習知的技術領域中，可應用單級或多級放大電路。單級放大電路可滿足低功率消耗的要求，惟其提供的增益可能有限。多級放大電路可提供較佳的增益，惟可能消耗較高的功率。此外，為了解決上述的問題，舉例而言，可應用兩級放大器來建構放大電路。然而，在兩級放大器的電路架構下，放大電路操作的仍可能具有線性度不佳的問題。 In the known technical field, a single-stage or multi-stage amplifier circuit can be applied. A single-stage amplifier circuit can meet the requirements of low power consumption, but the gain it provides may be limited. A multi-stage amplifier circuit can provide better gain, but may consume higher power. In addition, to solve the above problems, for example, a two-stage amplifier can be applied to construct an amplifier circuit. However, under the circuit architecture of the two-stage amplifier, the operation of the amplifier circuit may still have the problem of poor linearity.

本發明提供放大電路的諸多實施例，可在至少兩種不同的工作模式間進行切換，從而較佳的兼顧功率消耗、增益、及/或線性度。 The present invention provides a plurality of embodiments of an amplifier circuit that can switch between at least two different operating modes, thereby better balancing power consumption, gain, and/or linearity.

本發明實施例的放大電路包括第一電晶體、第二電晶體以及切換裝置。第一電晶體具有第一端、第二端以及控制端。第一電晶體的控制端耦接至放大電路的輸入端，第一電晶體的第一端耦接至第一參考端，其中放大電路的輸入端接收第一射頻訊號。第二電晶體具有第一端、第二端以及控制端。第二電晶體的第一端耦接至第一電晶體的第二端，第二電晶體的第二端耦接至放大電路的輸出端，其中放大電路的該輸出端輸出放大訊號。切換裝置耦接至第一電晶體的第二端、第二電晶體的第一端以及第二電晶體的控制端。其中，第一電晶體放大第一射頻訊號以在第一電晶體的第二端產生第二射頻訊號。切換裝置執行切換動作以傳遞第二射頻訊號至第二電晶體的第一端以及第二電晶體的控制端的其中之一者。 The amplifier circuit of the embodiment of the present invention includes a first transistor, a second transistor and a switching device. The first transistor has a first end, a second end and a control end. The control end of the first transistor is coupled to the input end of the amplifier circuit, and the first end of the first transistor is coupled to the first reference end, wherein the input end of the amplifier circuit receives a first radio frequency signal. The second transistor has a first end, a second end and a control end. The first end of the second transistor is coupled to the second end of the first transistor, and the second end of the second transistor is coupled to the output end of the amplifier circuit, wherein the output end of the amplifier circuit outputs an amplified signal. The switching device is coupled to the second end of the first transistor, the first end of the second transistor and the control end of the second transistor. The first transistor amplifies the first radio frequency signal to generate a second radio frequency signal at the second end of the first transistor. The switching device performs a switching action to transmit a second radio frequency signal to one of the first end of the second transistor and the control end of the second transistor.

本發明另一實施例的放大電路包括輸入端、輸出端、第一電晶體、第二電晶體、第一電感、第一開關、第二開關、第一電容以及第三開關。輸入端用以接收第一射頻訊號。輸出端用以輸出放大訊號。第一電晶體具有第一端、第二端以及控制端，其中第一電晶體的控制端耦接放大電路的輸入端，第一電晶體的第一端接至第一參考端。第二電晶體具有第一端、第二端以及控制端，其中第二電晶體的第二端耦接至放大電路的輸出端。第一電感耦接在第一電晶體的第二端以及第二電晶體的第一端間。第一開關耦接在第一電晶體的第二端與第二電晶體的控制端間。第二開關與第一電感並聯耦接。第三開關與第一電容串聯耦接，第一電容與第三開關耦接於第二電晶體的第一端與第二參考端間。 The amplifier circuit of another embodiment of the present invention includes an input terminal, an output terminal, a first transistor, a second transistor, a first inductor, a first switch, a second switch, a first capacitor and a third switch. The input terminal is used to receive a first radio frequency signal. The output terminal is used to output an amplified signal. The first transistor has a first terminal, a second terminal and a control terminal, wherein the control terminal of the first transistor is coupled to the input terminal of the amplifier circuit, and the first terminal of the first transistor is connected to the first reference terminal. The second transistor has a first terminal, a second terminal and a control terminal, wherein the second terminal of the second transistor is coupled to the output terminal of the amplifier circuit. The first inductor is coupled between the second terminal of the first transistor and the first terminal of the second transistor. The first switch is coupled between the second terminal of the first transistor and the control terminal of the second transistor. The second switch is coupled in parallel with the first inductor. The third switch is coupled in series with the first capacitor, and the first capacitor and the third switch are coupled between the first terminal of the second transistor and the second reference terminal.

基於上述，本發明的實施例藉由切換裝置可使放大電路在不同的模式間進行切換。如此一來，放大電路可視需求適應性的切換，例如可工作在一般模式或低電流模式，從而提升放大電路的工作效益。 Based on the above, the embodiment of the present invention can switch the amplifier circuit between different modes by means of a switching device. In this way, the amplifier circuit can switch adaptively according to the needs, for example, it can work in a normal mode or a low current mode, thereby improving the working efficiency of the amplifier circuit.

100、200、300、400、500、700、800:放大電路 100, 200, 300, 400, 500, 700, 800: amplifier circuit

110、210、310、410、510、710、810:切換裝置 110, 210, 310, 410, 510, 710, 810: Switching device

820:中間匹配網路 820: Intermediate matching network

840:輸入匹配網路 840: Input matching network

830:輸出匹配網路 830: Output matching network

BVE1、BVE2:偏壓訊號端 BVE1, BVE2: Bias signal terminal

C1~C7、CO1、CO2:電容 C1~C7, CO1, CO2: Capacitor

EIN:輸入端 EIN: Input terminal

EOUT:輸出端 EOUT: output terminal

L1~L4、LI1、LI2:電感 L1~L4, LI1, LI2: Inductor

N1、N2:節點 N1, N2: nodes

R1、R2:操作電阻 R1, R2: operating resistors

RA1、RA2:電阻 RA1, RA2: resistors

RFI、RF2:射頻訊號 RFI, RF2: radio frequency signal

RFO:放大訊號 RFO: Amplify the signal

SW1~SW8:開關 SW1~SW8: switch

T1、T2、T3、T4:電晶體 T1, T2, T3, T4: transistors

VC1~VC6:控制訊號 VC1~VC6: control signal

VDD:電源電壓訊號 VDD: power voltage signal

VG1、VG2:偏壓訊號 VG1, VG2: bias signal

VR1~VR5:參考端 VR1~VR5: Reference terminal

圖1繪示本發明一實施例的放大電路的示意圖。 FIG1 is a schematic diagram of an amplifier circuit of an embodiment of the present invention.

圖2繪示本發明一實施例的放大電路的電路示意圖。 FIG2 is a schematic diagram of an amplifier circuit of an embodiment of the present invention.

圖3繪示本發明另一實施例的放大電路的電路示意圖。 FIG3 is a circuit diagram of an amplifier circuit of another embodiment of the present invention.

圖3A以及圖3B繪示圖3中放大電路在不同工作模式下的動作方式的示意圖。 FIG. 3A and FIG. 3B are schematic diagrams showing the operation of the amplifying circuit in FIG. 3 in different working modes.

圖4至圖8繪示本發明多個實施例的放大電路的電路示意圖。 Figures 4 to 8 show schematic circuit diagrams of amplifier circuits of various embodiments of the present invention.

請參照圖1，圖1繪示本發明一實施例的放大電路100的示意圖。放大電路100包括輸入端EIN及輸出端EOUT，其中輸入端EIN用以接收射頻訊號RFI，經放大後在輸出端EOUT輸出放大訊號RFO。放大電路100包括電晶體T1、T2以及切換裝置110。在一些實施例中，電晶體T1包括控制端、第一端及第二端，其中控制端耦接至放大電路100的輸入端EIN，第一端耦接至參考端VR1，且第二端耦接至切換裝置110。切換裝置110耦接在電晶體T1與電晶體T2之間。具體而言，電晶體T2包括控制端、第一端及第二端，其中第一端可經由切換裝置110耦接至電晶體T1的第二端。電晶體T2的第二端耦接至放大電路100的輸出端EOUT。進一步講，電晶體T2的控制端亦可經由切換裝置110耦接至電晶體T1的第二端。 Please refer to FIG. 1, which shows a schematic diagram of an amplifier circuit 100 of an embodiment of the present invention. The amplifier circuit 100 includes an input terminal EIN and an output terminal EOUT, wherein the input terminal EIN is used to receive a radio frequency signal RFI, and after amplification, an amplified signal RFO is output at the output terminal EOUT. The amplifier circuit 100 includes transistors T1, T2, and a switching device 110. In some embodiments, the transistor T1 includes a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the input terminal EIN of the amplifier circuit 100, the first terminal is coupled to the reference terminal VR1, and the second terminal is coupled to the switching device 110. The switching device 110 is coupled between the transistor T1 and the transistor T2. Specifically, the transistor T2 includes a control terminal, a first terminal, and a second terminal, wherein the first terminal can be coupled to the second terminal of the transistor T1 via the switching device 110. The second end of transistor T2 is coupled to the output end EOUT of the amplifier circuit 100. Furthermore, the control end of transistor T2 can also be coupled to the second end of transistor T1 via the switching device 110.

在一些實施例中，電晶體T1可用以放大射頻訊號RFI，並在電晶體T1的第二端產生另一射頻訊號RF2，即第二射頻訊號RF2。切換裝置110可執行切換動作，以使得第二射頻訊號RF2選擇性的傳遞至電晶體T2的第一端或傳遞至電晶體T2的控制端，從而實現放大電路100不同的工作模式。電晶體T2可根據第二射頻訊號RF2以在放大電路100的輸出端EOUT上產生放大訊號RFO。在細節上，放大電路100可工作在一般模式或是低電流模式。在一般模式中，切換裝置110可選擇性的將第二射頻訊號RF2傳遞至電晶體T2的第一端。在低電流模式中，切換裝置110可選擇性的將第二射頻訊號RF2傳遞至電晶體T2的控制端。 In some embodiments, the transistor T1 can be used to amplify the radio frequency signal RFI and generate another radio frequency signal RF2 at the second end of the transistor T1, i.e., the second radio frequency signal RF2. The switching device 110 can perform a switching operation so that the second radio frequency signal RF2 is selectively transmitted to the first end of the transistor T2 or to the control end of the transistor T2, thereby realizing different operating modes of the amplifier circuit 100. The transistor T2 can generate an amplified signal RFO at the output end EOUT of the amplifier circuit 100 according to the second radio frequency signal RF2. In detail, the amplifier circuit 100 can operate in a normal mode or a low current mode. In the normal mode, the switching device 110 can selectively transmit the second radio frequency signal RF2 to the first end of the transistor T2. In the low current mode, the switching device 110 can selectively transmit the second radio frequency signal RF2 to the control terminal of the transistor T2.

請參照圖2，圖2繪示本發明一實施例的放大電路200的電路示意圖。在放大電路200中，切換裝置210耦接於電晶體T1的第二端、電晶體T2的第一端、以及電晶體T2的控制端。在本實施例中，切換裝置210包括電感L1、開關SW1~SW3、以及電容C1。如圖2所示，電感L1耦接在電晶體T1的第二端與電晶體T2的第一端間。開關SW2與電感L1並聯耦接。開關SW1耦接在電晶體T1的第二端與電晶體T2的控制端間。開關SW3與電容C1串聯耦接於電晶體T2的第一端與參考端VR2間。在進一步的實施例中，電感L1可包括第一端及第二端，其中第一端耦接於電晶體T1的第二端，且第二端耦接於電晶體T2的第一端。開關SW2可包含第一端、第二端、及控制端，其中開關SW2的第一端耦接於電感L1的第一端，開關SW2的第二端耦接於電感L1的第二端，亦即，開關SW2與電感L1並聯耦接。 Please refer to FIG. 2, which shows a circuit diagram of an amplifier circuit 200 of an embodiment of the present invention. In the amplifier circuit 200, the switching device 210 is coupled to the second end of the transistor T1, the first end of the transistor T2, and the control end of the transistor T2. In this embodiment, the switching device 210 includes an inductor L1, switches SW1~SW3, and a capacitor C1. As shown in FIG. 2, the inductor L1 is coupled between the second end of the transistor T1 and the first end of the transistor T2. The switch SW2 is coupled in parallel with the inductor L1. The switch SW1 is coupled between the second end of the transistor T1 and the control end of the transistor T2. The switch SW3 and the capacitor C1 are coupled in series between the first end of the transistor T2 and the reference end VR2. In a further embodiment, the inductor L1 may include a first end and a second end, wherein the first end is coupled to the second end of the transistor T1, and the second end is coupled to the first end of the transistor T2. The switch SW2 may include a first end, a second end, and a control end, wherein the first end of the switch SW2 is coupled to the first end of the inductor L1, and the second end of the switch SW2 is coupled to the second end of the inductor L1, that is, the switch SW2 is coupled in parallel with the inductor L1.

在一些實施例中，舉例而言，開關SW1、開關SW2、及/或開關SW3可實施為電晶體開關。開關SW1~SW3可分別受控於多個控制訊號VC1~VC3，以分別被導通或截止。舉例而言，開關SW2的控制端可用以接收控制訊號VC2，且根據該控制訊號VC2而導通或截止。類似的，開關SW1及開關SW3的控制端可分別用以接收控制訊號VC1及VC3，且分別根據該控制訊號VC1及VC3而導通或截止。 In some embodiments, for example, switch SW1, switch SW2, and/or switch SW3 may be implemented as transistor switches. Switches SW1-SW3 may be controlled by a plurality of control signals VC1-VC3 to be turned on or off, respectively. For example, the control end of switch SW2 may be used to receive control signal VC2, and turned on or off according to the control signal VC2. Similarly, the control ends of switches SW1 and SW3 may be used to receive control signals VC1 and VC3, respectively, and turned on or off according to the control signals VC1 and VC3, respectively.

在一些實施例中，參考端VR1以及VR2可以是相同的接地端，或者也可以是不同的端點。應注意，在圖2所示的實施例中，開關SW3位於電晶體T2的第一端與電容C1之間，然而本發明不限於此，在其他實施例中，開關SW3以及電容C1的位置可互換。也就是說，電容C1可位於電晶體T2的第一端與開關SW3之間。 In some embodiments, the reference terminals VR1 and VR2 may be the same ground terminal, or may be different terminals. It should be noted that in the embodiment shown in FIG. 2 , the switch SW3 is located between the first terminal of the transistor T2 and the capacitor C1, but the present invention is not limited thereto. In other embodiments, the positions of the switch SW3 and the capacitor C1 may be interchanged. In other words, the capacitor C1 may be located between the first terminal of the transistor T2 and the switch SW3.

當放大電路200操作在一般模式時，開關SW2可被導通，且開關SW1可被截止。在此情形中，處於導通狀態的開關SW2形成電感L1的旁路(bypass)電路。對第二射頻訊號RF2而言，在電晶體T1的第二端與電晶體T2的第一端之間形成低阻抗路徑，且在電晶體T1的第二端與電晶體T2的控制端之間形成高阻抗路徑。因此，第二射頻訊號RF2實質上可經由處於導通狀態的開關SW2傳遞至電晶體T2的第一端，以在放大電路200的輸出端EOUT產生放大訊號RFO。在上述一般模式中，電晶體T1與電晶體T2呈疊接(cascode)型態，使得放大電路200具有較佳的輸入輸出隔絕性，減少輸入訊號與輸出訊號之間的耦合，從而使得放大電路200可工作於更大的頻寬。在該一般模式中，開關SW3可被截止。 When the amplifier circuit 200 operates in the normal mode, the switch SW2 can be turned on and the switch SW1 can be turned off. In this case, the switch SW2 in the on state forms a bypass circuit of the inductor L1. For the second RF signal RF2, a low impedance path is formed between the second end of the transistor T1 and the first end of the transistor T2, and a high impedance path is formed between the second end of the transistor T1 and the control end of the transistor T2. Therefore, the second RF signal RF2 can be substantially transmitted to the first end of the transistor T2 via the switch SW2 in the on state to generate the amplified signal RFO at the output end EOUT of the amplifier circuit 200. In the above general mode, transistor T1 and transistor T2 are in a cascode type, so that the amplifier circuit 200 has better input-output isolation, reduces the coupling between the input signal and the output signal, and thus allows the amplifier circuit 200 to operate at a larger bandwidth. In this general mode, the switch SW3 can be turned off.

在一些情形中，例如為了降低功率消耗，放大電路200可工作於低電流模式，在此情形中，放大電路200可改變電晶體T1與電晶體T2的耦接關係，以達成期望的增益。當放大電路200操作在低電流模式時，開關SW2可被截止，且開關SW1可被導通。在此情形中，對第二射頻訊號RF2而言，在電晶體T1的第二端與電晶體T2的第一端之間形成高阻抗路徑，且該高阻抗路徑包含電感L1，以及在電晶體T1的第二端與電晶體T2的控制端之間形成低阻抗路徑。因此，第二射頻訊號RF2實質上可經由處於導通狀態的開關SW1傳送至電晶體T2的控制端，以在放大電路200的輸出端EOUT產生放大訊號RFO。在上述低電流模式中，電晶體T1與電晶體T2呈串接(cascade)型態，使得放大電路200輸入端EIN的射頻訊號RFI依序經電晶體T1及電晶體T2兩級放大後，在輸出端EOUT產生放大訊號RFO，從而達成期望的增益。在此低電流模式中，開關SW2處於截止狀態，電感L1可實質上阻隔第二射頻訊號RF2被傳送至電晶體T2的第一端，亦即電感L1對第二射頻訊號RF2實質上為高阻抗狀態，用以減少第二射頻訊號RF2經由電感L1的損耗。此外，在低電流模式中，開關SW3可被導通，使得電晶體T2的第一端經由電容C1耦接至參考端VR2，其中電容C1對第二射頻訊號RF2實質上為低阻抗狀態。舉例而言，電感L1對第二射頻訊號RF2的阻抗可為高於第一預設值的高阻抗狀態，電容C1對第二射頻訊號RF2的阻抗為低於第二預設值的低阻抗狀態，其中第一預設值大於第二預設值。 In some cases, for example, to reduce power consumption, the amplifier circuit 200 may operate in a low current mode, in which case the amplifier circuit 200 may change the coupling relationship between the transistor T1 and the transistor T2 to achieve a desired gain. When the amplifier circuit 200 operates in the low current mode, the switch SW2 may be turned off, and the switch SW1 may be turned on. In this case, for the second RF signal RF2, a high impedance path is formed between the second end of the transistor T1 and the first end of the transistor T2, and the high impedance path includes the inductor L1, and a low impedance path is formed between the second end of the transistor T1 and the control end of the transistor T2. Therefore, the second RF signal RF2 can be transmitted to the control end of the transistor T2 via the switch SW1 in the on state to generate the amplified signal RFO at the output end EOUT of the amplifier circuit 200. In the above low current mode, transistor T1 and transistor T2 are connected in series (cascade) so that the RF signal RFI at the input terminal EIN of the amplifier circuit 200 is amplified by transistor T1 and transistor T2 in sequence, and then an amplified signal RFO is generated at the output terminal EOUT, thereby achieving the desired gain. In this low current mode, the switch SW2 is in the off state, and the inductor L1 can substantially block the second RF signal RF2 from being transmitted to the first terminal of the transistor T2, that is, the inductor L1 is substantially in a high impedance state to the second RF signal RF2, so as to reduce the loss of the second RF signal RF2 through the inductor L1. In addition, in the low current mode, the switch SW3 can be turned on, so that the first end of the transistor T2 is coupled to the reference end VR2 via the capacitor C1, wherein the capacitor C1 is substantially in a low impedance state to the second radio frequency signal RF2. For example, the impedance of the inductor L1 to the second radio frequency signal RF2 can be a high impedance state higher than a first preset value, and the impedance of the capacitor C1 to the second radio frequency signal RF2 is a low impedance state lower than a second preset value, wherein the first preset value is greater than the second preset value.

附帶一提的，在上述一般模式中，電晶體T1以及電晶體T2呈疊接關係，電晶體T1以及電晶體T2可共用直流電流。進一步講，在低電流模式中，電感L1可容許直流通過，使得即使電晶體T1以及電晶體T2呈串接關係仍可共用直流電流，藉此減少功率消耗。 Incidentally, in the above-mentioned general mode, transistor T1 and transistor T2 are in a stacked relationship, and transistor T1 and transistor T2 can share the DC current. Furthermore, in the low current mode, inductor L1 can allow the DC to pass, so that even if transistor T1 and transistor T2 are in a series relationship, they can still share the DC current, thereby reducing power consumption.

如上所述，在一般模式中，放大電路200的電晶體T1與電晶體T2呈疊接(cascode)型態，使得放大電路200可在較大操作電流的情況下，提供較大的增益。另一方面，為減低功率消耗，放大電路200可工作在低電流模式，亦即工作於較小的操作電流，藉由切換裝置210的切換動作來改變電晶體T1與電晶體T2的耦接關係，使得電晶體T1與電晶體T2呈串接(cascade)型態，從而達成期望的增益。因此，本案實施例的放大電路可因應不同的操作電流來達成期望的增益，從而提升系統的整體效益。 As described above, in the normal mode, the transistor T1 and the transistor T2 of the amplifier circuit 200 are in a cascaded form, so that the amplifier circuit 200 can provide a larger gain under a larger operating current. On the other hand, in order to reduce power consumption, the amplifier circuit 200 can operate in a low current mode, that is, operate at a smaller operating current, and change the coupling relationship between the transistor T1 and the transistor T2 by the switching action of the switching device 210, so that the transistor T1 and the transistor T2 are in a cascade form, thereby achieving the desired gain. Therefore, the amplifier circuit of the embodiment of the present case can achieve the desired gain in response to different operating currents, thereby improving the overall efficiency of the system.

請參照圖3，圖3繪示本發明另一實施例的放大電路300 的電路示意圖。放大電路300包括電晶體T1、T2以及切換裝置310。放大電路300與放大電路200的電路架構相類似，相同的部分不多贅述。與放大電路200不相同的，放大電路300中的切換裝置310中另包括電容C2。電容C2與開關SW1串接於電晶體T1的第二端與電晶體T2的控制端間。在圖3的實施例中，電容C2耦接在開關SW1與電晶體T2的控制端間，在其他實施例中，電容C2與開關SW1的位置可互換。也就是說，開關SW1可耦接在電容C2與電晶體T2的控制端間。關於放大電路300的動作細節，請參照圖3A以及圖3B，其分別繪示放大電路300在不同工作模式下的動作方式的示意圖。 Please refer to FIG. 3, which shows a circuit diagram of an amplifier circuit 300 of another embodiment of the present invention. The amplifier circuit 300 includes transistors T1, T2 and a switching device 310. The amplifier circuit 300 is similar to the amplifier circuit 200 in circuit architecture, and the same parts are not described in detail. Unlike the amplifier circuit 200, the switching device 310 in the amplifier circuit 300 further includes a capacitor C2. The capacitor C2 and the switch SW1 are connected in series between the second end of the transistor T1 and the control end of the transistor T2. In the embodiment of FIG. 3, the capacitor C2 is coupled between the switch SW1 and the control end of the transistor T2. In other embodiments, the positions of the capacitor C2 and the switch SW1 can be interchanged. That is, the switch SW1 can be coupled between the capacitor C2 and the control end of the transistor T2. For details of the operation of the amplifier circuit 300, please refer to FIG. 3A and FIG. 3B, which respectively show schematic diagrams of the operation of the amplifier circuit 300 in different working modes.

在圖3A中，放大電路300操作在一般模式，亦即，放大電路300可工作於較大的操作電流，從而獲得較高的增益。在此情形中，開關SW2可被導通，開關SW1、SW3可被截止，放大電路300的電晶體T1、T2呈疊接(cascode)狀態。電晶體T1放大所接收的射頻訊號RFI以產生射第二頻訊號RF2。第二射頻訊號RF2可經由導通的開關SW2被傳送至電晶體T2的第一端。電晶體T2可根據第二射頻訊號RF2來產生放大訊號RFO。在本實施例中，開關SW2對第二射頻訊號RF2實質上呈低阻抗，開關SW1對第二射頻訊號RF2實質上呈高阻抗。 In FIG. 3A , the amplifier circuit 300 operates in a normal mode, that is, the amplifier circuit 300 can operate at a larger operating current, thereby obtaining a higher gain. In this case, the switch SW2 can be turned on, the switches SW1 and SW3 can be turned off, and the transistors T1 and T2 of the amplifier circuit 300 are in a cascode state. The transistor T1 amplifies the received RF signal RFI to generate a second RF signal RF2. The second RF signal RF2 can be transmitted to the first end of the transistor T2 via the turned-on switch SW2. The transistor T2 can generate an amplified signal RFO according to the second RF signal RF2. In this embodiment, the switch SW2 is substantially low impedance to the second RF signal RF2, and the switch SW1 is substantially high impedance to the second RF signal RF2.

在圖3B中，放大電路300操作在低電流模式，亦即，放大電路300可工作於較小的操作電流，以減小功率消耗。在此情形中，開關SW2可被截止，開關SW1、SW3可被導通。放大電路 300的電晶體T1、T2呈串接(cascade)狀態。電晶體T1放大所接收的射頻訊號RFI以產生第二射頻訊號RF2。第二射頻訊號RF2可經由導通的開關SW1以及電容C2被傳送至電晶體T2的控制端。電晶體T2可根據第二射頻訊號RF2來產生放大訊號RFO。在本實施例中，電容C2對第二射頻訊號RF2實質上呈低阻抗狀態，且電容C2可用以阻隔傳輸訊號的直流成分。舉例而言，電容C2對第二射頻訊號RF2的阻抗為低於第三預設值的低阻抗狀態，其中第一預設值大於第三預設值。如上所述，電容C1對第二射頻訊號RF2的阻抗為低於第二預設值的低阻抗狀態，其中第二預設值以及第三預設值可相同或不同，並可分別取決於電容C1以及C2的電容值。 In FIG. 3B , the amplifier circuit 300 operates in a low current mode, that is, the amplifier circuit 300 can operate at a smaller operating current to reduce power consumption. In this case, the switch SW2 can be turned off, and the switches SW1 and SW3 can be turned on. The transistors T1 and T2 of the amplifier circuit 300 are in a cascade state. The transistor T1 amplifies the received RF signal RFI to generate a second RF signal RF2. The second RF signal RF2 can be transmitted to the control end of the transistor T2 via the turned-on switch SW1 and the capacitor C2. The transistor T2 can generate an amplified signal RFO according to the second RF signal RF2. In this embodiment, the capacitor C2 is substantially in a low impedance state to the second RF signal RF2, and the capacitor C2 can be used to block the DC component of the transmission signal. For example, the impedance of capacitor C2 to the second RF signal RF2 is in a low impedance state lower than the third preset value, wherein the first preset value is greater than the third preset value. As described above, the impedance of capacitor C1 to the second RF signal RF2 is in a low impedance state lower than the second preset value, wherein the second preset value and the third preset value may be the same or different and may depend on the capacitance values of capacitors C1 and C2, respectively.

在上述實施方式中，當開關SW1、SW2、及/或SW3導通時，對第二射頻訊號RF2為低阻抗狀態。 In the above implementation, when switches SW1, SW2, and/or SW3 are turned on, the second radio frequency signal RF2 is in a low impedance state.

請參照圖4，圖4繪示本發明另一實施例的放大電路的電路示意圖。放大電路400包括電晶體T1、T2以及切換裝置410。放大電路400與放大電路300的電路架構相類似，相同的部分不多贅述。與放大電路300不相同的，放大電路400中的切換裝置410中另包括開關SW4。如圖4所示，在開關SW3與電容C1之間可存在節點N1(亦即，開關SW3與電容C1可皆耦接至節點N1)，且開關SW4可耦接在節點N1與電晶體T的控制端間。進一步講，電晶體T2的第一端、開關SW3、電容C1、及參考端VR2可依序耦接，且節點N1位於開關SW3與電容C1之間。在本實施例中，開關SW4受控於控制訊號VC4以被導通或被截止。在進一步的實施例中，當開關SW2導通時，開關SW4亦導通，使電晶體T2的控制端經由電容C1耦接至參考端VR2，在此情形中，開關SW3截止。另一方面，當開關SW2截止時，開關SW4亦截止，使電晶體T2的控制端可與節點N1隔離。在此情形中，開關SW3導通，使得電晶體T2的第一端經由電容C1耦接至參考端VR2。 Please refer to FIG. 4, which shows a circuit diagram of an amplifier circuit of another embodiment of the present invention. The amplifier circuit 400 includes transistors T1, T2 and a switching device 410. The amplifier circuit 400 is similar to the amplifier circuit 300 in circuit architecture, and the same parts are not described in detail. Unlike the amplifier circuit 300, the switching device 410 in the amplifier circuit 400 further includes a switch SW4. As shown in FIG. 4, a node N1 may exist between the switch SW3 and the capacitor C1 (that is, the switch SW3 and the capacitor C1 may both be coupled to the node N1), and the switch SW4 may be coupled between the node N1 and the control terminal of the transistor T. Furthermore, the first terminal of the transistor T2, the switch SW3, the capacitor C1, and the reference terminal VR2 may be coupled in sequence, and the node N1 is located between the switch SW3 and the capacitor C1. In this embodiment, the switch SW4 is controlled by the control signal VC4 to be turned on or off. In a further embodiment, when the switch SW2 is turned on, the switch SW4 is also turned on, so that the control end of the transistor T2 is coupled to the reference end VR2 via the capacitor C1, in which case the switch SW3 is turned off. On the other hand, when the switch SW2 is turned off, the switch SW4 is also turned off, so that the control end of the transistor T2 can be isolated from the node N1. In this case, the switch SW3 is turned on, so that the first end of the transistor T2 is coupled to the reference end VR2 via the capacitor C1.

在上述實施例中，開關SW1、SW2、SW3、及/或SW4可利用相同導電型態的電晶體(例如皆為N型電晶體或皆為P型電晶體)來建構，在此狀態下，控制訊號VC1與VC3可為同步同相訊號，控制訊號VC2與VC4可為同步同相訊號。進一步講，控制訊號VC1與VC2可為同步反相訊號。然而，本發明不限於此，在其他實施例中，開關SW1、SW2、SW3、及/或SW4可利用不同導電型態的電晶體(例如一部分為N型電晶體，另一部分為P型電晶體)來建構。 In the above embodiments, switches SW1, SW2, SW3, and/or SW4 can be constructed using transistors of the same conductivity type (for example, all N-type transistors or all P-type transistors). In this state, control signals VC1 and VC3 can be synchronous in-phase signals, and control signals VC2 and VC4 can be synchronous in-phase signals. Furthermore, control signals VC1 and VC2 can be synchronous inverted signals. However, the present invention is not limited thereto. In other embodiments, switches SW1, SW2, SW3, and/or SW4 can be constructed using transistors of different conductivity types (for example, one part is an N-type transistor and the other part is a P-type transistor).

請參照圖5，圖5繪示本發明另一實施例的放大電路500的電路示意圖。放大電路500類似於放大電路300，差異在於放大電路500的切換裝置510另包括操作電阻R1及R2。操作電阻R1可耦接在開關SW1的第一端與第二端間。操作電阻R2可耦接在開關SW2的第一端與第二端間。 Please refer to FIG. 5, which shows a circuit diagram of an amplifier circuit 500 of another embodiment of the present invention. The amplifier circuit 500 is similar to the amplifier circuit 300, except that the switching device 510 of the amplifier circuit 500 further includes operating resistors R1 and R2. The operating resistor R1 can be coupled between the first end and the second end of the switch SW1. The operating resistor R2 can be coupled between the first end and the second end of the switch SW2.

請參照圖6A至圖6C，圖6A至圖6C繪示本發明另一實施例的放大電路600的不同實施方式的電路示意圖。放大電路600類似於圖2的放大電路200，差異在於放大電路600還包括電晶體 T3及開關SW5。詳細而言，電晶體T3的第一端耦接至電晶體T1的第一端，電晶體T3的第二端耦接至電晶體T1的第二端，且電晶體T3的控制端耦接至電晶體T1的控制端，如圖6A所示，開關SW5可耦接於電晶體T3的第二端與電晶體T1的第二端之間。然而，本發明不限於此，在其他實施例中，開關SW5可耦接於電晶體T3的控制端與電晶體T1的控制端之間(如圖6B所示)，或者耦接於電晶體T3的第一端與電晶體T1的第一端之間(如圖6C所示)。 Please refer to FIG. 6A to FIG. 6C , which are circuit diagrams of different implementations of an amplifier circuit 600 of another embodiment of the present invention. The amplifier circuit 600 is similar to the amplifier circuit 200 of FIG. 2 , except that the amplifier circuit 600 further includes a transistor T3 and a switch SW5. Specifically, the first end of the transistor T3 is coupled to the first end of the transistor T1, the second end of the transistor T3 is coupled to the second end of the transistor T1, and the control end of the transistor T3 is coupled to the control end of the transistor T1. As shown in FIG. 6A , the switch SW5 can be coupled between the second end of the transistor T3 and the second end of the transistor T1. However, the present invention is not limited thereto. In other embodiments, the switch SW5 may be coupled between the control end of the transistor T3 and the control end of the transistor T1 (as shown in FIG. 6B ), or coupled between the first end of the transistor T3 and the first end of the transistor T1 (as shown in FIG. 6C ).

請參照圖7，圖7繪示本發明另一實施例的放大電路700的電路示意圖。放大電路700類似於圖6A的放大電路600，差異在於放大電路700還包括電晶體T4及開關SW6。詳細而言，電晶體T4與電晶體T2的耦接關係類似於圖6A中電晶體T3與電晶體T1的耦接關係，在此不加贅述。如圖7所示，開關SW6可耦接於電晶體T4的控制端與電晶體T2的控制端之間。然而，本發明不限於此，在其他實施例中，開關SW6可耦接於電晶體T4的第二端與電晶體T2的第二端之間，或者耦接於電晶體T4的第一端與電晶體T2的第一端之間。 Please refer to FIG. 7, which shows a circuit diagram of an amplifier circuit 700 of another embodiment of the present invention. The amplifier circuit 700 is similar to the amplifier circuit 600 of FIG. 6A, except that the amplifier circuit 700 further includes a transistor T4 and a switch SW6. In detail, the coupling relationship between transistor T4 and transistor T2 is similar to the coupling relationship between transistor T3 and transistor T1 in FIG. 6A, which will not be elaborated here. As shown in FIG. 7, the switch SW6 can be coupled between the control end of transistor T4 and the control end of transistor T2. However, the present invention is not limited thereto, and in other embodiments, the switch SW6 can be coupled between the second end of transistor T4 and the second end of transistor T2, or between the first end of transistor T4 and the first end of transistor T2.

仍參照圖7，當放大電路700工作在一般模式時，開關SW2導通且SW1截止，電晶體T1第一端的第二射頻訊號RF2傳遞至電晶體T2的第一端。在此情形中，為獲得期望的增益及較佳的線性度，開關SW5可被導通，使得用來產生第二射頻訊號RF2的等效電晶體的尺寸增加(亦即，電晶體T1與電晶體T3的尺寸之和)。進一步講，SW6亦可被導通，使得用來產生輸出訊號RFO的等效電晶體的尺寸增加(亦即，電晶體T2與電晶體T4的尺寸之和)，藉此可提升放大電路700的線性度。在上述實施例中，開關SW5及/或SW6可為電晶體開關，例如P型或N型的電晶體，且開關SW5及SW6可分別受控於控制訊號VC5及VC6。 Still referring to FIG. 7 , when the amplifier circuit 700 operates in the normal mode, the switch SW2 is turned on and the switch SW1 is turned off, and the second RF signal RF2 at the first end of the transistor T1 is transmitted to the first end of the transistor T2. In this case, in order to obtain the desired gain and better linearity, the switch SW5 can be turned on, so that the size of the equivalent transistor used to generate the second RF signal RF2 is increased (that is, the sum of the sizes of the transistor T1 and the transistor T3). Furthermore, SW6 can also be turned on, so that the size of the equivalent transistor used to generate the output signal RFO is increased (that is, the sum of the sizes of the transistor T2 and the transistor T4), thereby improving the linearity of the amplifier circuit 700. In the above embodiment, the switches SW5 and/or SW6 may be transistor switches, such as P-type or N-type transistors, and the switches SW5 and SW6 may be controlled by control signals VC5 and VC6, respectively.

以下請參照圖8，圖8繪示本發明的放大電路800的電路示意圖。放大電路800包括電晶體T1、T2、及切換裝置810。電晶體T1及T2類似於前述任一實施例，切換裝置810與圖3的切換裝置310具有類似的電路架構，在此已不多贅述。 Please refer to FIG. 8 below, which shows a schematic diagram of the amplifier circuit 800 of the present invention. The amplifier circuit 800 includes transistors T1, T2, and a switching device 810. Transistors T1 and T2 are similar to any of the aforementioned embodiments, and the switching device 810 has a similar circuit structure to the switching device 310 of FIG. 3, which will not be described in detail here.

如圖8所示，放大電路800更包括電容C5、輸入匹配網路840、中間匹配網路820、輸出匹配網路830。在一些實施例中，電容C5耦接至放大電路800的輸入端EIN，用以阻隔射頻訊號RFI中的直流成分。輸入匹配網路840可經由電容C5耦接至放大電路800的輸入端EIN。輸入匹配網路840可與電容C5串聯耦接，且用作放大電路800的輸入阻抗匹配元件。舉例而言，輸入匹配網路840可包括開關SW7以及電感LI1、LI2。電感LI1、LI2可串聯耦接在射頻訊號RFI的傳遞路徑上，且開關SW7可與電感LI1並聯耦接，用以根據需求改變輸入匹配網路840的阻抗值。在一些實施例中，中間匹配網路820可耦接於電晶體T1與T2之間。詳細而言，中間匹配網路820可耦接在切換裝置810與電晶體T2的控制端間。在細節上，中間匹配網路820可包括電感L2、電容C3及C4。電感L2耦接在電晶體T1的第二端與電晶體T2的控制端間，且可與切換裝置810的電容C2串聯。如圖8所示，在切換裝置810的開關SW1與電容C2之間存在節點N2，亦即，開關SW1與電容C2皆耦接至節點N2。在圖8所示實施例中，電感L2可耦接於開關SW1與節點N2之間，且電容C3可耦接在節點N2與參考端VR3間，然而本發明不限於此。在其他實施例中，電感L2可耦接於與節點N2與電容C2之間。電容C4可耦接在電晶體T2的控制端與參考端VR4間。在該實施例中，中間匹配網路820可用作電晶體T1與T2間的阻抗匹配元件。在一些實施例中，輸出匹配網路830可耦接至放大電路800的輸出端EOUT，用作放大電路800的輸出阻抗匹配元件。輸出匹配網路830可包括開關SW8以及電容CO1、CO2。電容CO1、CO2可並聯耦接在放大訊號RFO的傳遞路徑上，且開關SW8可與電容CO1串聯耦接，用以根據需求改變輸出匹配網路830的阻抗值。 As shown in FIG8 , the amplifier circuit 800 further includes a capacitor C5, an input matching network 840, an intermediate matching network 820, and an output matching network 830. In some embodiments, the capacitor C5 is coupled to the input terminal EIN of the amplifier circuit 800 to block the DC component in the radio frequency signal RFI. The input matching network 840 can be coupled to the input terminal EIN of the amplifier circuit 800 via the capacitor C5. The input matching network 840 can be coupled in series with the capacitor C5 and used as an input impedance matching element of the amplifier circuit 800. For example, the input matching network 840 can include a switch SW7 and inductors LI1 and LI2. Inductors LI1 and LI2 may be coupled in series on the transmission path of the radio frequency signal RFI, and switch SW7 may be coupled in parallel with inductor LI1 to change the impedance value of the input matching network 840 as required. In some embodiments, the intermediate matching network 820 may be coupled between transistors T1 and T2. In detail, the intermediate matching network 820 may be coupled between the switching device 810 and the control terminal of the transistor T2. In detail, the intermediate matching network 820 may include an inductor L2, capacitors C3 and C4. The inductor L2 is coupled between the second terminal of the transistor T1 and the control terminal of the transistor T2, and may be connected in series with the capacitor C2 of the switching device 810. As shown in FIG8 , there is a node N2 between the switch SW1 and the capacitor C2 of the switching device 810, that is, the switch SW1 and the capacitor C2 are both coupled to the node N2. In the embodiment shown in FIG8 , the inductor L2 may be coupled between the switch SW1 and the node N2, and the capacitor C3 may be coupled between the node N2 and the reference terminal VR3, but the present invention is not limited thereto. In other embodiments, the inductor L2 may be coupled between the node N2 and the capacitor C2. The capacitor C4 may be coupled between the control terminal of the transistor T2 and the reference terminal VR4. In this embodiment, the intermediate matching network 820 may be used as an impedance matching element between the transistors T1 and T2. In some embodiments, the output matching network 830 may be coupled to the output terminal EOUT of the amplifier circuit 800 and used as an output impedance matching element of the amplifier circuit 800. The output matching network 830 may include a switch SW8 and capacitors CO1 and CO2. Capacitors CO1 and CO2 may be coupled in parallel to the transmission path of the amplified signal RFO, and the switch SW8 may be coupled in series with the capacitor CO1 to change the impedance value of the output matching network 830 as required.

如圖8所示，放大電路800更包括電阻RA1及電阻RA2，其中電晶體T1的控制端可經由電阻RA1耦接至偏壓訊號端BVE1，以接收偏壓訊號VG1。電晶體T2的控制端可經由電阻RA2耦接至偏壓訊號端BVE2，以接收偏壓訊號VG2。在一些實施例中，偏壓訊號VG1及VG2可為直流訊號。放大電路800更包括電容C7及電感L4，其中電容C7可耦接在電晶體T1的控制端與第一端間，電感L4可耦接在電晶體T1的第一端與參考端VR1間。放大電路800更包括電感L3及電容C6，其中電晶體T2(例如，電晶體T2的第二端)可經由電感L3耦接至電源電壓端，以接收電源電壓訊號VDD。電容C6的一端可耦接至電感L3，另一端可耦接至參考端VR5。在本實施例中，放大電路800的輸出端EOUT處可另設置電容以耦接至任一參考端。 As shown in FIG8 , the amplifier circuit 800 further includes a resistor RA1 and a resistor RA2, wherein the control terminal of the transistor T1 can be coupled to the bias signal terminal BVE1 via the resistor RA1 to receive the bias signal VG1. The control terminal of the transistor T2 can be coupled to the bias signal terminal BVE2 via the resistor RA2 to receive the bias signal VG2. In some embodiments, the bias signals VG1 and VG2 can be DC signals. The amplifier circuit 800 further includes a capacitor C7 and an inductor L4, wherein the capacitor C7 can be coupled between the control terminal and the first terminal of the transistor T1, and the inductor L4 can be coupled between the first terminal of the transistor T1 and the reference terminal VR1. The amplifier circuit 800 further includes an inductor L3 and a capacitor C6, wherein the transistor T2 (for example, the second end of the transistor T2) can be coupled to the power voltage terminal via the inductor L3 to receive the power voltage signal VDD. One end of the capacitor C6 can be coupled to the inductor L3, and the other end can be coupled to the reference terminal VR5. In this embodiment, a capacitor can be set at the output terminal EOUT of the amplifier circuit 800 to couple to any reference terminal.

在上述實施例中，參考端VR1~VR5可為相同的參考接地端，也可分別是不同的端點。此外，需說明的是，在本揭露內容中，序數詞(例如，第一、第二、第三...)僅用以區別功能或位置，不表示順序及數量。 In the above embodiment, the reference terminals VR1~VR5 can be the same reference ground terminal, or they can be different terminals. In addition, it should be noted that in the present disclosure, ordinal numbers (e.g., first, second, third...) are only used to distinguish functions or positions, and do not indicate order and quantity.

綜上所述，本發明在放大電路中設置切換裝置，其中切換裝置可根據放大電路的工作模式，以使放大電路可因應不同的應用需求呈疊接模式(cascode)或是串接模式(cascade)。舉例而言，當放大電路在疊接模式(cascode)中，可提供較佳的輸入輸出隔絕性，減少輸入訊號與輸出訊號之間的耦合，從而使得放大電路可工作於更大的頻寬。當放大電路在串接模式(cascade)中，可提供相對高的放大增益。進一步講，在上述模式中，放大電路的電晶體可共用直流電流。因此，本發明放大電路可提升系統的工作效能，且具有相對低的消耗功率。 In summary, the present invention sets a switching device in the amplifier circuit, wherein the switching device can be based on the working mode of the amplifier circuit, so that the amplifier circuit can be in a cascade mode or a series mode according to different application requirements. For example, when the amplifier circuit is in the cascade mode, it can provide better input-output isolation and reduce the coupling between the input signal and the output signal, so that the amplifier circuit can operate at a larger bandwidth. When the amplifier circuit is in the cascade mode, it can provide a relatively high amplification gain. Furthermore, in the above mode, the transistors of the amplifier circuit can share a DC current. Therefore, the amplifier circuit of the present invention can improve the working performance of the system and has a relatively low power consumption.

100:放大電路 100: Amplifier circuit

110:切換裝置 110: Switch device

EIN:輸入端 EIN: Input terminal

EOUT:輸出端 EOUT: output terminal

RFI、RF2:射頻訊號 RFI, RF2: radio frequency signal

RFO:放大訊號 RFO: amplifies the signal

T1、T2:電晶體 T1, T2: transistors

VR1:參考端 VR1: Reference terminal

Claims

An amplifier circuit includes: a first transistor having a first end, a second end and a control end, the control end of the first transistor being coupled to the input end of the amplifier circuit, the first end of the first transistor being coupled to a first reference end, wherein the input end of the amplifier circuit receives a first radio frequency signal; a second transistor having a first end, a second end and a control end, the first end of the second transistor being coupled to the second end of the first transistor, the second end of the second transistor being coupled to the output end of the amplifier circuit, wherein the output end of the amplifier circuit outputs an amplified signal; and a switching device being coupled to the second end of the first transistor, the first end of the second transistor and the control end of the second transistor, The first transistor amplifies the first RF signal to generate a second RF signal at the second end of the first transistor, and the switching device performs a switching action to transmit the second RF signal to one of the first end of the second transistor and the control end of the second transistor.

An amplifier circuit as described in claim 1, wherein the switching device includes: a first inductor coupled between the second end of the first transistor and the first end of the second transistor; a first switch coupled between the second end of the first transistor and the control end of the second transistor; a second switch coupled in parallel with the first inductor; a first capacitor; and a third switch coupled in series with the first capacitor between the first end of the second transistor and a second reference end.

The amplifier circuit as described in claim 2, wherein the switching device further comprises: A second capacitor coupled in series with the first switch between the second end of the first transistor and the control end of the second transistor.

An amplifier circuit as described in claim 3, wherein the first switch and the second switch are controlled by a first control signal and a second control signal respectively to be turned on or off, wherein when the first switch is turned off and the second switch is turned on, the second RF signal is transmitted to the first end of the second transistor via the second switch, when the first switch is turned on and the second switch is turned off, the second RF signal is transmitted to the control end of the second transistor via the first switch.

An amplifier circuit as described in claim 1, wherein the first transistor and the second transistor share a DC current.

An amplifier circuit as described in claim 4, wherein when the second RF signal is transmitted to the control terminal of the second transistor, the first inductor is in a high impedance state with respect to the second RF signal, the first capacitor is in a low impedance state with respect to the second RF signal, and the second capacitor is in a low impedance state with respect to the second RF signal.

An amplifier circuit as described in claim 6, wherein when the first switch is turned on, the first switch is in a low impedance state for the second RF signal; when the second switch is turned on, the second switch is in a low impedance state for the second RF signal; when the third switch is turned on, the third switch is in a low impedance state for the second RF signal.

An amplifier circuit as described in claim 4, wherein the third switch is controlled by a third control signal, and the third switch is turned on or off according to the third control signal. When the first switch is turned on, the third switch is turned on, so that the second transistor is coupled to the second reference terminal via the first capacitor.

The amplifier circuit as described in claim 8, wherein the switching device further comprises: a fourth switch, wherein the first end of the second transistor, the third switch, the first capacitor and the second reference end are coupled in sequence, the third switch and the first capacitor are coupled at a node, and the fourth switch is coupled between the node and the control end of the second transistor.

An amplifier circuit as described in claim 9, wherein the fourth switch is controlled by a fourth control signal, and the fourth switch is turned on or off according to the fourth control signal. When the second switch is turned on, the fourth switch is turned on, so that the control terminal of the second transistor is coupled to the second reference terminal via the first capacitor.

An amplifier circuit as described in claim 4, wherein the switching device further comprises: a first operating resistor coupled between the first end and the second end of the first switch; and a second operating resistor coupled between the first end and the second end of the second switch.

The amplifier circuit as described in claim 1 further includes: a third transistor having a first end, a second end and a control end, the first end of the third transistor being coupled to the first end of the first transistor, the second end of the third transistor being coupled to the second end of the first transistor, and the control end of the third transistor being coupled to the control end of the first transistor; and a fifth switch being coupled between the first end of the first transistor and the first end of the third transistor, or between the second end of the first transistor and the second end of the third transistor, or between the control end of the first transistor and the control end of the third transistor.

The amplifier circuit as described in claim 1 further includes: a fourth transistor having a first end, a second end and a control end, the first end of the fourth transistor being coupled to the first end of the second transistor, the second end of the fourth transistor being coupled to the second end of the second transistor, and the control end of the fourth transistor being coupled to the control end of the second transistor; and a sixth switch being coupled between the first end of the second transistor and the first end of the fourth transistor, or between the second end of the second transistor and the second end of the fourth transistor, or between the control end of the second transistor and the control end of the fourth transistor.

An amplifier circuit as described in claim 13, wherein the control end of the first transistor is coupled to a first bias signal end, the first bias signal end is used to receive a first bias signal, and the control end of the second transistor is coupled to a second bias signal end, the second bias signal end is used to receive a second bias signal.

The amplifier circuit as described in claim 14 further includes: a first resistor; and a second resistor, wherein the control end of the first transistor is coupled to the first bias signal end via the first resistor, and the control end of the second transistor is coupled to the second bias signal end via the second resistor.

The amplifier circuit as described in claim 3 further includes: An intermediate matching network, including: A second inductor, coupled between the second end of the first transistor and the control end of the second transistor, and coupled in series with the second capacitor; A third capacitor, wherein the first switch and the second capacitor are coupled to a node together, and the third capacitor is coupled between the node and a third reference terminal; A fourth capacitor, coupled between the control end of the second transistor and a fourth reference terminal.

The amplifier circuit as described in claim 3 further includes: an input matching network coupled to the input end of the amplifier circuit; and an output matching network coupled to the output end of the amplifier circuit.

An amplifier circuit as described in claim 14, wherein the second end of the second transistor is coupled to a first power voltage end for receiving a first power voltage signal.

An amplifier circuit includes: an input terminal for receiving a first radio frequency signal; an output terminal for outputting an amplified signal; a first transistor having a first terminal, a second terminal and a control terminal, wherein the control terminal of the first transistor is coupled to the input terminal, and the first terminal of the first transistor is connected to a first reference terminal; a second transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the second transistor is coupled to the output terminal; a first inductor coupled between the second terminal of the first transistor and the first terminal of the second transistor; a first switch coupled between the second terminal of the first transistor and the control terminal of the second transistor; a second switch coupled in parallel with the first inductor; a first capacitor; and a third switch coupled in series with the first capacitor, and the first capacitor and the third switch are coupled between the first terminal of the second transistor and a second reference terminal.

The amplifier circuit as described in claim 19 further includes: A second capacitor coupled in series with the first switch between the second end of the first transistor and the control end of the second transistor.