CN118137985A - amplifying circuit - Google Patents

Abstract

The amplifying circuit comprises a first transistor, a second transistor and a switching device. The control end of the first transistor is coupled to the input end of the amplifying circuit, and the first end of the first transistor is coupled to the first reference end, wherein the input end of the amplifying circuit receives the first radio frequency signal. The first end of the second transistor is coupled to the second end of the first transistor, and the second end of the second transistor is coupled to the output end of the amplifying circuit, wherein the output end of the amplifying circuit outputs the amplified signal. The first transistor amplifies the first radio frequency signal to generate a second radio frequency signal at a second terminal of the first transistor. The switching device performs a switching operation to transmit the second radio frequency signal to one of the first terminal of the second transistor and the control terminal of the second transistor.

Description

Amplifying circuit

Technical Field

The present invention relates to an amplifying circuit, and more particularly, to an amplifying circuit capable of switching between two different operation modes.

Background

In the known art, single-stage or multi-stage amplification circuits may be applied. Single stage amplification circuits can meet the low power consumption requirements, but may provide limited gain. The multi-stage amplification circuit may provide better gain but may consume higher power. In addition, in order to solve the above-described problems, for example, a two-stage amplifier may be applied to construct an amplifying circuit. However, under the circuit architecture of the two-stage amplifier, the operation of the amplifying circuit may still have a problem of poor linearity.

Disclosure of Invention

The invention provides various embodiments of the amplifying circuit, which can be switched between at least two different working modes, so that the power consumption, the gain and/or the linearity are better considered.

The amplifying circuit of the embodiment of the invention comprises a first transistor, a second transistor and a switching device. The first transistor has a first terminal, a second terminal, and a control terminal. The control end of the first transistor is coupled to the input end of the amplifying circuit, and the first end of the first transistor is coupled to the first reference end, wherein the input end of the amplifying circuit receives the first radio frequency signal. The second transistor has a first terminal, a second terminal, and a control terminal. The first end of the second transistor is coupled to the second end of the first transistor, and the second end of the second transistor is coupled to the output end of the amplifying circuit, wherein the output end of the amplifying circuit outputs the amplified signal. The switching device is coupled to the second end of the first transistor, the first end of the second transistor and the control end of the second transistor. The first transistor amplifies the first radio frequency signal to generate a second radio frequency signal at a second end of the first transistor. The switching device performs a switching operation to transmit the second radio frequency signal to one of the first terminal of the second transistor and the control terminal of the second transistor.

An amplifying circuit according to another embodiment of the present invention includes an input terminal, an output terminal, a first transistor, a second transistor, a first inductor, a first switch, a second switch, a first capacitor, and a third switch. The input end is used for receiving a first radio frequency signal. The output end is used for outputting an amplified signal. The first transistor has a first end, a second end and a control end, wherein the control end of the first transistor is coupled to the input end of the amplifying circuit, and the first end of the first transistor is connected to the first reference end. The second transistor has a first end, a second end and a control end, wherein the second end of the second transistor is coupled to the output end of the amplifying circuit. The first inductor is coupled between the second end of the first transistor and the first end of the second transistor. The first switch is coupled between the second end of the first transistor and the control end of the second transistor. The second switch is coupled in parallel with the first inductor. The third switch is coupled in series with the first capacitor, and the first capacitor and the third switch are coupled between the first end of the second transistor and the second reference end.

Based on the above, the embodiment of the invention can switch the amplifying circuit between different modes by the switching device. In this way, the amplifying circuit can be adaptively switched according to requirements, for example, the amplifying circuit can work in a normal mode or a low-current mode, so that the working benefit of the amplifying circuit is improved.

Drawings

Fig. 1 is a schematic diagram of an amplifying circuit according to an embodiment of the invention.

Fig. 2 is a schematic circuit diagram of an amplifying circuit according to an embodiment of the invention.

Fig. 3 is a schematic circuit diagram of an amplifying circuit according to another embodiment of the invention.

Fig. 3A and fig. 3B are schematic diagrams illustrating operation modes of the amplifying circuit in fig. 3 in different operation modes.

Fig. 4 to 8 are schematic circuit diagrams of amplifying circuits according to various embodiments of the present invention.

[ Symbolic description ]

100. 200, 300, 400, 500, 700, 800: Amplifying circuit

110. 210, 310, 410, 510, 710, 810: Switching device

820: Intermediate matching network

840: Input matching network

830: Output matching network

BVE1, BVE2: bias signal terminal

C1-C7, CO1, CO2: capacitance device

EIN: input terminal

EOUT: an output terminal

L1 to L4, LI1, LI2: inductance

N1, N2: node

R1 and R2: operating resistor

RA1, RA2: resistor

RFI, RF2: radio frequency signal

RFO: amplifying a signal

SW1 to SW8: switch

T1, T2, T3, T4: transistor with a high-voltage power supply

VC 1-VC 6: control signal

VDD: supply voltage signal

VG1, VG2: bias signal

VR 1-VR 5: reference terminal

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of an amplifying circuit 100 according to an embodiment of the invention. The amplifying circuit 100 includes an input end EIN and an output end EOUT, wherein the input end EIN is configured to receive the radiofrequency signal RFI, and the amplified signal RFO is output at the output end EOUT after being amplified. The amplifying circuit 100 includes transistors T1, T2 and a switching device 110. In some embodiments, the transistor T1 includes a control terminal coupled to the input terminal EIN of the amplifying circuit 100, a first terminal coupled to the reference terminal VR1, and a second terminal coupled to the switching device 110. The switching device 110 is coupled between the transistors T1 and T2. Specifically, the transistor T2 includes a control terminal, a first terminal and a second terminal, wherein the first terminal can be coupled to the second terminal of the transistor T1 through the switching device 110. A second terminal of the transistor T2 is coupled to the output terminal EOUT of the amplifying circuit 100. Further, the control terminal of the transistor T2 may also be coupled to the second terminal of the transistor T1 via the switching device 110.

In some embodiments, the transistor T1 may be configured to amplify the radiofrequency signal RFI and generate another radiofrequency signal RF2, i.e., a second radiofrequency signal RF2, at a second terminal of the transistor T1. The switching device 110 may perform a switching operation to selectively transfer the second radio frequency signal RF2 to the first terminal of the transistor T2 or to the control terminal of the transistor T2, so as to implement different operation modes of the amplifying circuit 100. The transistor T2 generates the amplified signal RFO at the output EOUT of the amplifying circuit 100 according to the second radio frequency signal RF2. In detail, the amplifying circuit 100 may operate in a normal mode or a low current mode. In the normal mode, the switching device 110 selectively transmits the second radio frequency signal RF2 to the first terminal of the transistor T2. In the low current mode, the switching device 110 selectively transmits the second radio frequency signal RF2 to the control terminal of the transistor T2.

Referring to fig. 2, fig. 2 is a schematic circuit diagram of an amplifying circuit 200 according to an embodiment of the invention. In the amplifying circuit 200, the switching device 210 is coupled to the second terminal of the transistor T1, the first terminal of the transistor T2, and the control terminal of the transistor T2. In the present embodiment, the switching device 210 includes an inductor L1, switches SW1 to SW3, and a capacitor C1. As shown in fig. 2, the inductor L1 is coupled between the second end of the transistor T1 and the first end of the transistor T2. Switch SW2 is coupled in parallel with inductor L1. The switch SW1 is coupled between the second terminal of the transistor T1 and the control terminal of the transistor T2. The switch SW3 and the capacitor C1 are coupled in series between the first terminal of the transistor T2 and the reference terminal VR 2. In a further embodiment, the inductor L1 may include a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the transistor T1, and the second terminal is coupled to the first terminal of the transistor T2. The switch SW2 may comprise a first terminal, a second terminal, and a control terminal, wherein the first terminal of the switch SW2 is coupled to the first terminal of the inductor L1, and the second terminal of the switch SW2 is coupled to the second terminal of the inductor L1, that is, the switch SW2 is coupled in parallel with the inductor L1.

In some embodiments, for example, switch SW1, switch SW2, and/or switch SW3 may be implemented as transistor switches. The switches SW1 to SW3 are controlled by a plurality of control signals VC1 to VC3, respectively, to be turned on or off, respectively. For example, the control terminal of the switch SW2 may be configured to receive the control signal VC2, and be turned on or turned off according to the control signal VC 2. Similarly, the control terminals of the switch SW1 and the switch SW3 can be used for receiving the control signals VC1 and VC3, respectively, and are turned on or turned off according to the control signals VC1 and VC3, respectively.

In some embodiments, the reference terminals VR1 and VR2 may be the same ground terminal, or may be different end points. It should be noted that in the embodiment shown in fig. 2, the switch SW3 is located between the first end of the transistor T2 and the capacitor C1, however, the present invention is not limited thereto, and in other embodiments, the positions of the switch SW3 and the capacitor C1 may be interchanged. That is, the capacitor C1 may be located between the first terminal of the transistor T2 and the switch SW 3.

When the amplifying circuit 200 operates in the normal mode, the switch SW2 may be turned on and the switch SW1 may be turned off. In this case, the switch SW2 in the on state forms a bypass (bypass) circuit of the inductor L1. For the second radio frequency signal RF2, a low impedance path is formed between the second terminal of the transistor T1 and the first terminal of the transistor T2, and a high impedance path is formed between the second terminal of the transistor T1 and the control terminal of the transistor T2. Therefore, the second RF signal RF2 can be substantially transferred to the first terminal of the transistor T2 via the switch SW2 in the on state to generate the amplified signal RFO at the output terminal EOUT of the amplifying circuit 200. In the above-mentioned general mode, the transistor T1 and the transistor T2 are in a cascode (cascode) configuration, so that the amplifying circuit 200 has better input/output isolation, and reduces the coupling between the input signal and the output signal, thereby enabling the amplifying circuit 200 to operate with a larger bandwidth. In this general mode, the switch SW3 may be turned off.

In some cases, for example, to reduce power consumption, the amplifying circuit 200 may operate in a low current mode, in which case the amplifying circuit 200 may change the coupling relationship of the transistor T1 and the transistor T2 to achieve a desired gain. When the amplifying circuit 200 operates in the low current mode, the switch SW2 may be turned off and the switch SW1 may be turned on. In this case, for the second radio frequency signal RF2, a high impedance path is formed between the second terminal of the transistor T1 and the first terminal of the transistor T2, and the high impedance path includes the inductance L1, and a low impedance path is formed between the second terminal of the transistor T1 and the control terminal of the transistor T2. Therefore, the second RF signal RF2 can be substantially transmitted to the control terminal of the transistor T2 via the switch SW1 in the on state to generate the amplified signal RFO at the output terminal EOUT of the amplifying circuit 200. In the low current mode, the transistor T1 and the transistor T2 are connected in series (cascades), so that the rf signal RFI at the input end EIN of the amplifying circuit 200 is amplified by the transistor T1 and the transistor T2 in two stages in sequence, and then an amplified signal RFO is generated at the output end EOUT, thereby achieving the desired gain. In the low current mode, the switch SW2 is turned off, and the inductor L1 substantially blocks the second RF signal RF2 from being transmitted to the first terminal of the transistor T2, i.e. the inductor L1 is substantially in a high impedance state to the second RF signal RF2, so as to reduce the loss of the second RF signal RF2 through the inductor L1. In addition, in the low current mode, the switch SW3 may be turned on, such that the first terminal of the transistor T2 is coupled to the reference terminal VR2 via the capacitor C1, wherein the capacitor C1 is substantially in a low impedance state for the second radio frequency signal RF 2. For example, the impedance of the inductor L1 to the second RF signal RF2 may be in a high impedance state higher than a first preset value, and the impedance of the capacitor C1 to the second RF signal RF2 is in a low impedance state lower than a second preset value, wherein the first preset value is greater than the second preset value.

Incidentally, in the above-mentioned general mode, the transistor T1 and the transistor T2 are in a stacked relationship, and the transistor T1 and the transistor T2 may share a direct current. Further, in the low current mode, the inductor L1 can allow direct current to pass through, so that even though the transistor T1 and the transistor T2 are in a series connection, the direct current can be shared, thereby reducing power consumption.

As described above, in the normal mode, the transistor T1 and the transistor T2 of the amplifying circuit 200 are in a cascode (cascode) configuration, so that the amplifying circuit 200 can provide a larger gain under a larger operation current. On the other hand, to reduce the power consumption, the amplifying circuit 200 can operate in a low current mode, i.e. a smaller operation current, and the coupling relationship between the transistor T1 and the transistor T2 is changed by the switching operation of the switching device 210, so that the transistor T1 and the transistor T2 are in a cascade (cascades) mode, thereby achieving the desired gain. Therefore, the amplifying circuit of the embodiment can achieve the expected gain according to different operation currents, thereby improving the overall benefit of the system.

Referring to fig. 3, fig. 3 is a schematic circuit diagram of an amplifying circuit 300 according to another embodiment of the invention. The amplifying circuit 300 includes transistors T1, T2 and a switching device 310. The amplifying circuit 300 is similar to the circuit structure of the amplifying circuit 200, and the same parts will not be repeated. Unlike the amplifying circuit 200, the switching device 310 in the amplifying circuit 300 further includes a capacitor C2. The capacitor C2 and the switch SW1 are connected in series between the second terminal of the transistor T1 and the control terminal of the transistor T2. In the embodiment of fig. 3, the capacitor C2 is coupled between the switch SW1 and the control terminal of the transistor T2, and in other embodiments, the positions of the capacitor C2 and the switch SW1 are interchangeable. That is, the switch SW1 can be coupled between the capacitor C2 and the control terminal of the transistor T2. For details of the operation of the amplifying circuit 300, please refer to fig. 3A and fig. 3B, which respectively show schematic diagrams of the operation modes of the amplifying circuit 300 in different operation modes.

In fig. 3A, the amplifying circuit 300 operates in a normal mode, i.e., the amplifying circuit 300 can operate at a larger operation current, thereby obtaining a higher gain. In this case, the switch SW2 may be turned on, the switches SW1 and SW3 may be turned off, and the transistors T1 and T2 of the amplifying circuit 300 are in a cascode (cascode) state. The transistor T1 amplifies the received radio frequency signal RF1 to generate a second radio frequency signal RF2. The second radio frequency signal RF2 may be transmitted to the first terminal of the transistor T2 via the on switch SW 2. The transistor T2 may generate the amplified signal RFO according to the second radio frequency signal RF2. In the present embodiment, the switch SW2 has a substantially low impedance to the second RF signal RF2, and the switch SW1 has a substantially high impedance to the second RF signal RF2.

In fig. 3B, the amplifying circuit 300 operates in a low current mode, i.e., the amplifying circuit 300 may operate at a smaller operating current to reduce power consumption. In this case, the switch SW2 may be turned off and the switches SW1, SW3 may be turned on. The transistors T1 and T2 of the amplifying circuit 300 are in a cascode (cascades) state. The transistor T1 amplifies the received radio frequency signal RF1 to generate a second radio frequency signal RF2. The second RF signal RF2 can be transmitted to the control terminal of the transistor T2 via the on switch SW1 and the capacitor C2. The transistor T2 may generate the amplified signal RFO according to the second radio frequency signal RF2. In the present embodiment, the capacitor C2 is in a substantially low impedance state to the second RF signal RF2, and the capacitor C2 can be used to block the dc component of the transmission signal. For example, the impedance of the capacitor C2 to the second radio frequency signal RF2 is in a low impedance state lower than a third preset value, wherein the first preset value is greater than the third preset value. As described above, the impedance of the capacitor C1 to the second radio frequency signal RF2 is in a low impedance state lower than the second preset value, wherein the second preset value and the third preset value may be the same or different and may depend on the capacitance values of the capacitors C1 and C2, respectively.

In the above embodiment, when the switches SW1, SW2 and/or SW3 are turned on, the second radio frequency signal RF2 is in a low impedance state.

Referring to fig. 4, fig. 4 is a schematic circuit diagram of an amplifying circuit according to another embodiment of the invention. The amplifying circuit 400 includes transistors T1, T2 and a switching device 410. The amplifying circuit 400 is similar to the circuit structure of the amplifying circuit 300, and the same parts will not be repeated. Unlike the amplifying circuit 300, the switching device 410 of the amplifying circuit 400 further includes a switch SW4. As shown in fig. 4, a node N1 may be present between the switch SW3 and the capacitor C1 (i.e., the switch SW3 and the capacitor C1 may both be coupled to the node N1), and the switch SW4 may be coupled between the node N1 and the control terminal of the transistor T2. Further, the first terminal of the transistor T2, the switch SW3, the capacitor C1 and the reference terminal VR2 can be sequentially coupled, and the node N1 is located between the switch SW3 and the capacitor C1. In the present embodiment, the switch SW4 is controlled by the control signal VC4 to be turned on or turned off. In a further embodiment, when the switch SW2 is turned on, the switch SW4 is also turned on, so that the control terminal of the transistor T2 is coupled to the reference terminal VR2 via the capacitor C1, in which case the switch SW3 is turned off. On the other hand, when the switch SW2 is turned off, the switch SW4 is also turned off, so that the control terminal of the transistor T2 can be isolated from the node N1. In this case, the switch SW3 is turned on, so that the first terminal of the transistor T2 is coupled to the reference terminal VR2 via the capacitor C1.

In the above embodiments, the switches SW1, SW2, SW3 and/or SW4 may be implemented by transistors of the same conductivity type (e.g. N-type transistors or P-type transistors), and in this state, the control signals VC1 and VC3 may be synchronous in-phase signals, and the control signals VC2 and VC4 may be synchronous in-phase signals. Further, the control signals VC1 and VC2 may be synchronous and inverted signals. However, the present invention is not limited thereto, and in other embodiments, the switches SW1, SW2, SW3, and/or SW4 may be implemented with transistors of different conductivity types (e.g., N-type transistors for one portion and P-type transistors for another portion).

Referring to fig. 5, fig. 5 is a circuit diagram of an amplifying circuit 500 according to another embodiment of the invention. The amplifying circuit 500 is similar to the amplifying circuit 300 except that the switching device 510 of the amplifying circuit 500 further includes operating resistors R1 and R2. The operating resistor R1 may be coupled between the first terminal and the second terminal of the switch SW 1. The operating resistor R2 may be coupled between the first terminal and the second terminal of the switch SW 2.

Referring to fig. 6A to 6C, fig. 6A to 6C are schematic circuit diagrams illustrating different implementations of an amplifying circuit 600 according to another embodiment of the invention. The amplifying circuit 600 is similar to the amplifying circuit 200 of fig. 2, except that the amplifying circuit 600 further includes a transistor T3 and a switch SW5. In detail, the first terminal of the transistor T3 is coupled to the first terminal of the transistor T1, the second terminal of the transistor T3 is coupled to the second terminal of the transistor T1, and the control terminal of the transistor T3 is coupled to the control terminal of the transistor T1, as shown in fig. 6A, the switch SW5 may be coupled between the second terminal of the transistor T3 and the second terminal of the transistor T1. However, the present invention is not limited thereto, and in other embodiments, the switch SW5 may be coupled between the control terminal of the transistor T3 and the control terminal of the transistor T1 (as shown in fig. 6B), or coupled between the first terminal of the transistor T3 and the first terminal of the transistor T1 (as shown in fig. 6C).

Referring to fig. 7, fig. 7 is a schematic circuit diagram of an amplifying circuit 700 according to another embodiment of the invention. The amplifying circuit 700 is similar to the amplifying circuit 600 of fig. 6A, except that the amplifying circuit 700 further includes a transistor T4 and a switch SW6. In detail, the coupling relationship between the transistor T4 and the transistor T2 is similar to that between the transistor T3 and the transistor T1 in fig. 6A, and the description is omitted herein. As shown in fig. 7, the switch SW6 may be coupled between the control terminal of the transistor T4 and the control terminal of the transistor T2. However, the present invention is not limited thereto, and in other embodiments, the switch SW6 may be coupled between the second terminal of the transistor T4 and the second terminal of the transistor T2, or between the first terminal of the transistor T4 and the first terminal of the transistor T2.

Still referring to fig. 7, when the amplifying circuit 700 operates in the normal mode, the switch SW2 is turned on and the switch SW1 is turned off, and the second radio frequency signal RF2 at the first terminal of the transistor T1 is transferred to the first terminal of the transistor 2. In this case, to obtain the desired gain and better linearity, the switch SW5 may be turned on, so that the size of the equivalent transistor (i.e., the sum of the sizes of the transistor T1 and the transistor T3) used to generate the second radio frequency signal RF2 increases. Further, SW6 can also be turned on, so that the size of the equivalent transistor for generating the output signal RFO is increased (i.e., the sum of the sizes of the transistor T2 and the transistor T4), thereby improving the linearity of the amplifying circuit 700. In the above embodiments, the switches SW5 and/or SW6 may be transistor switches, such as P-type or N-type transistors, and the switches SW5 and SW6 may be controlled by the control signals VC5 and VC6, respectively.

Referring to fig. 8, fig. 8 is a circuit diagram of an amplifying circuit 800 according to the present invention. The amplifying circuit 800 includes transistors T1, T2 and a switching device 810. The transistors T1 and T2 are similar to any of the above embodiments, and the switching device 810 and the switching device 310 of fig. 3 have similar circuit structures and are not repeated here.

As shown in fig. 8, the amplifying circuit 800 further includes a capacitor C5, an input matching network 840, an intermediate matching network 820, and an output matching network 830. In some embodiments, the capacitor C5 is coupled to the input EIN of the amplifying circuit 800 for blocking the dc component of the rf signal RFI. The input matching network 840 may be coupled to an input EIN of the amplifying circuit 800 via a capacitor C5. The input matching network 840 may be coupled in series with the capacitor C5 and function as an input impedance matching element for the amplifying circuit 800. For example, the input matching network 840 may include a switch SW7 and inductors LI1, LI2. The inductors LI1 and LI2 may be coupled in series in a transmission path of the radiofrequency signal RFI, and the switch SW7 may be coupled in parallel with the inductor LI1 for changing the impedance value of the input matching network 840 according to the requirement. In some embodiments, an intermediate matching network 820 may be coupled between transistors T1 and T2. In detail, the intermediate matching network 820 may be coupled between the switching device 810 and the control terminal of the transistor T2. In detail, the intermediate matching network 820 may include an inductance L2, a capacitance C3, and a capacitance C4. The inductor L2 is coupled between the second terminal of the transistor T1 and the control terminal of the transistor T2, and can be connected in series with the capacitor C2 of the switching device 810. As shown in fig. 8, a node N2 exists between the switch SW1 and the capacitor C2 of the switching device 810, i.e., the switch SW1 and the capacitor C2 are both coupled to the node N2. In the embodiment shown in fig. 8, the inductor L2 may be coupled between the switch SW1 and the node N2, and the capacitor C3 may be coupled between the node N2 and the reference terminal VR3, but the invention is not limited thereto. In other embodiments, the inductor L2 may be coupled between the node N2 and the capacitor C2. The capacitor C4 may be coupled between the control terminal of the transistor T2 and the reference terminal VR 4. In this embodiment, the intermediate matching network 820 may be used as an impedance matching element between the transistors T1 and T2. In some embodiments, the output matching network 830 may be coupled to the output EOUT of the amplifying circuit 800, serving as an output impedance matching element of the amplifying circuit 800. The output matching network 830 may include a switch SW8 and capacitors CO1, CO2. The capacitors CO1 and CO2 may be coupled in parallel to a transmission path of the amplified signal RFO, and the switch SW8 may be coupled in series with the capacitor CO 1to change the impedance value of the output matching network 830 according to the requirement.

As shown in fig. 8, the amplifying circuit 800 further includes a resistor RA1 and a resistor RA2, wherein the control terminal of the transistor T1 is coupled to the bias signal terminal BVE1 through the resistor RA1 to receive the bias signal VG1. The control terminal of the transistor T2 is coupled to the bias signal terminal BVE2 via a resistor RA2 to receive the bias signal VG2. In some embodiments, the bias signals VG1 and VG2 can be dc signals. The amplifying circuit 800 further includes a capacitor C7 and an inductor L4, wherein the capacitor C7 can be coupled between the control terminal and the first terminal of the transistor T1, and the inductor L4 can be coupled between the first terminal of the transistor T1 and the reference terminal VR 1. The amplifying circuit 800 further includes an inductor L3 and a capacitor C6, wherein the transistor T2 (e.g., a second terminal of the transistor T2) can be coupled to the supply voltage terminal via the inductor L3 to receive the supply voltage signal VDD. One end of the capacitor C6 may be coupled to the inductor L3, and the other end may be coupled to the reference terminal VR5. In this embodiment, a capacitor may be further disposed at the output end EOUT of the amplifying circuit 800 to be coupled to any reference end.

In the above embodiment, the reference terminals VR1 to VR5 may be the same reference ground terminal, or may be different terminals. Furthermore, it should be noted that, in the present disclosure, ordinal words (e.g., first, second, third …) are merely used to distinguish between functions or positions, and do not indicate a sequence or a number.

In summary, the switching device is disposed in the amplifying circuit according to the operation mode of the amplifying circuit, so that the amplifying circuit can be in a cascade mode (cascade) or a cascade mode (cascade) according to different application requirements. For example, when the amplifying circuit is in a cascode mode (cascode), the amplifying circuit can provide better input/output isolation, and reduce the coupling between the input signal and the output signal, so that the amplifying circuit can work with a larger bandwidth. When the amplifying circuit is in a cascade mode (cascades), a relatively high amplifying gain can be provided. Further, in the above mode, the transistors of the amplifying circuit may share a direct current. Therefore, the amplifying circuit can improve the working efficiency of the system and has relatively low power consumption.

Claims (20)

1. An amplifying circuit, comprising:

A first transistor having a first end, a second end and a control end, wherein the control end of the first transistor is coupled to the input end of the amplifying circuit, the first end of the first transistor is coupled to a first reference end, and the input end of the amplifying circuit receives a first radio frequency signal;

A second transistor having a first end, a second end and a control end, wherein the first end of the second transistor is coupled to the second end of the first transistor, and the second end of the second transistor is coupled to the output end of the amplifying circuit, wherein the output end of the amplifying circuit outputs an amplifying signal; and

A switching device coupled to the second end of the first transistor, the first end of the second transistor and the control end of the second transistor,

The first transistor amplifies the first radio frequency signal to generate a second radio frequency signal at a second end of the first transistor, and the switching device performs a switching operation to transmit the second radio frequency signal to one of the first end of the second transistor and a control end of the second transistor.

2. The amplifying circuit of claim 1, wherein the switching means comprises:

A first inductor coupled between the second end of the first transistor and the first end of the second transistor;

a first switch coupled between the second end of the first transistor and the control end of the second transistor;

A second switch coupled in parallel with the first inductor;

A first capacitor; and

A third switch is coupled in series with the first capacitor between the first terminal of the second transistor and a second reference terminal.

3. The amplifying circuit of claim 2, wherein the switching means further comprises:

and a second capacitor coupled in series with the first switch between the second end of the first transistor and the control end of the second transistor.

4. The amplifying circuit of claim 3, wherein the first switch and the second switch are controlled by a first control signal and a second control signal, respectively, to be turned on or off,

Wherein when the first switch is turned off and the second switch is turned on, the second RF signal is transferred to the first terminal of the second transistor through the second switch,

When the first switch is turned on and the second switch is turned off, the second radio frequency signal is transmitted to the control end of the second transistor through the first switch.

5. The amplifying circuit of claim 1, wherein the first transistor and the second transistor share a direct current.

6. The amplifying circuit of claim 4, wherein the first inductor is in a high impedance state for the second rf signal, the first capacitor is in a low impedance state for the second rf signal, and the second capacitor is in a low impedance state for the second rf signal when the second rf signal is transferred to the control terminal of the second transistor.

7. The amplifying circuit of claim 6, wherein when the first switch is turned on, the first switch is in a low impedance state for the second rf signal; when the second switch is turned on, the second switch is in a low impedance state for the second radio frequency signal; when the third switch is turned on, the third switch is in a low impedance state for the second radio frequency signal.

8. The amplifying circuit according to claim 4, wherein the third switch is controlled by a third control signal, the third switch is turned on or off according to the third control signal, and when the first switch is turned on, the third switch is turned on to enable the second transistor to be coupled to the second reference terminal through the first capacitor.

9. The amplifying circuit of claim 8, wherein the switching means further comprises:

the first end of the second transistor, the third switch, the first capacitor and the second reference end are coupled in sequence, the third switch and the first capacitor are coupled to a node, and the fourth switch is coupled between the node and the control end of the second transistor.

10. The amplifying circuit according to claim 9, wherein a fourth switch is controlled by a fourth control signal, the fourth switch is turned on or off according to the fourth control signal, and when the second switch is turned on, the fourth switch is turned on to enable the control terminal of the second transistor to be coupled to the second reference terminal through the first capacitor.

11. The amplifying circuit of claim 4, wherein the switching means further comprises:

a first operating resistor coupled between the first end and the second end of the first switch; and

And a second operating resistor coupled between the first end and the second end of the second switch.

12. The amplifying circuit of claim 1, further comprising:

A third transistor having a first end, a second end and a control end, the first end of the third transistor being coupled to the first end of the first transistor, the second end of the third transistor being coupled to the second end of the first transistor, the control end of the third transistor being coupled to the control end of the first transistor; and

A fifth switch coupled between the first end of the first transistor and the first end of the third transistor, or between the second end of the first transistor and the second end of the third transistor, or between the control end of the first transistor and the control end of the third transistor.

13. The amplifying circuit of claim 1, further comprising:

A fourth transistor having a first end, a second end and a control end, the first end of the fourth transistor being coupled to the first end of the second transistor, the second end of the fourth transistor being coupled to the second end of the second transistor, the control end of the fourth transistor being coupled to the control end of the second transistor; and

A sixth switch coupled between the first end of the second transistor and the first end of the fourth transistor, or between the second end of the second transistor and the second end of the fourth transistor, or between the control end of the second transistor and the control end of the fourth transistor.

14. The amplifying circuit of claim 13, wherein the control terminal of the first transistor is coupled to a first bias signal terminal for receiving a first bias signal, and the control terminal of the second transistor is coupled to a second bias signal terminal for receiving a second bias signal.

15. The amplifying circuit of claim 14, further comprising:

A first resistor; and

A second resistor is arranged between the first resistor and the second resistor,

The control end of the first transistor is coupled to the first bias signal end through the first resistor, and the control end of the second transistor is coupled to the second bias signal end through the second resistor.

16. The amplifying circuit of claim 3, further comprising:

An intermediate matching network, comprising:

a second inductor coupled between the second end of the first transistor and the control end of the second transistor and coupled in series with the second capacitor;

a third capacitor, wherein the first switch and the second capacitor are coupled to a node together, the third capacitor being coupled between the node and a third reference terminal;

A fourth capacitor coupled between the control terminal of the second transistor and a fourth reference terminal.

17. The amplifying circuit of claim 3, further comprising:

An input matching network coupled to the input of the amplifying circuit; and

An output matching network is coupled to the output end of the amplifying circuit.

18. The amplifying circuit of claim 14, wherein the second terminal of the second transistor is coupled to a first supply voltage terminal for receiving a first supply voltage signal.

19. An amplifying circuit, comprising:

An input end for receiving a first RF signal;

An output end for outputting an amplified signal;

A first transistor having a first end, a second end and a control end, wherein the control end of the first transistor is coupled to the input end, and the first end of the first transistor is connected to a first reference end;

a second transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the second transistor is coupled to the output terminal;

a first inductor coupled between the second end of the first transistor and the first end of the second transistor;

a first switch coupled between the second end of the first transistor and the control end of the second transistor;

A second switch coupled in parallel with the first inductor;

A first capacitor; and

And a third switch coupled in series with the first capacitor, the first capacitor and the third switch being coupled between the first terminal of the second transistor and a second reference terminal.

20. The amplifying circuit of claim 19, further comprising:

and a second capacitor coupled in series with the first switch between the second end of the first transistor and the control end of the second transistor.