TWI741326B - Source driver and output buffer thereof - Google Patents

Abstract

A source driver includes an output buffer and a feedback circuit. The output buffer includes an input stage circuit, an output stage circuit, a rising control circuit, and a falling control circuit. The input stage circuit correspondingly generates a first gate control voltage and a second gate control voltage according to an input voltage and a feedback voltage. The output stage circuit correspondingly generates an output voltage according to the first gate control voltage and the second gate control voltage. The feedback circuit generates and outputs the feedback voltage corresponding to the output voltage to the input stage circuit. The rising control circuit and the falling control circuit compare the input voltage with the feedback voltage, and pull down (or pull up) the first gate control voltage and the second gate control voltage according to the comparison result.

Description

Source driver and its output buffer

The present invention relates to a display device, and more particularly to a source driver and its output buffer.

Generally speaking, the source driver is used to drive multiple data lines (or source lines) of the display panel. The source driver is configured with a plurality of driving channel circuits, and each of the driving channel circuits drives a corresponding one of the data lines through a different output buffer. The source driver is equipped with an output buffer, which can gain the analog voltage of the digital-to-analog converter and output it to the data line (or called the source line) of the display panel. As the resolution and/or frame rate of the display panel becomes higher, the charging time for one scan line becomes shorter and shorter. In order to drive (charge or discharge) a pixel in a short time, the output buffer needs a sufficiently high drive capability. That is, the output buffer needs a sufficiently high slew rate (Slew Rate). In order to increase the slew rate, the tail current of the conventional output buffer is increased. An increase in tail current means an increase in power consumption.

The present invention provides a source driver and an output buffer thereof, which can selectively overdrive the output buffer during a period of driving a pixel (pixel) to improve the slew rate of the output voltage.

The embodiment of the present invention provides a source driver. The source driver includes an output buffer and a feedback circuit. The output buffer includes an input stage circuit, an output stage circuit, a rise control circuit and a fall control circuit. The first input terminal of the input stage circuit receives the input voltage of the output buffer. The second input terminal of the input stage circuit is coupled to the output terminal of the feedback circuit to receive the first feedback voltage. The input stage circuit is configured to generate a first gating voltage and a second gating voltage corresponding to the input voltage and the first feedback voltage. The output stage circuit is coupled to the input stage circuit to receive the first gating voltage and the second gating voltage. The output stage circuit is used for generating the output voltage of the output buffer to the data line of the display panel according to the first gating voltage and the second gating voltage. The output terminal of the output stage circuit is coupled to the input terminal of the feedback circuit. The rise control circuit is used to compare the input voltage with the first feedback voltage to obtain the first comparison result. When the first comparison result indicates that the first feedback voltage is going to be increased, the rising control circuit pulls down the first gating voltage and the second gating voltage during the first transient period. The drop control circuit is used to compare the input voltage with the first feedback voltage to obtain a second comparison result. When the second comparison result indicates that the first feedback voltage is about to be pulled down, the down control circuit pulls up the first gating voltage and the second gating voltage during the second transient period. The feedback circuit is used for generating and outputting the first feedback voltage related to the output voltage to the second input terminal of the input stage circuit.

The embodiment of the present invention provides an output buffer, and the output buffer includes an output Entry circuit, output stage circuit, rise control circuit and fall control circuit. The input stage circuit has a first input terminal and a second input terminal. The first input terminal of the input stage circuit receives the input voltage of the output buffer, and the second input terminal of the input stage circuit is used to receive the first feedback voltage of the output buffer . The input stage circuit generates a first gate control voltage and a second gate control voltage corresponding to the input voltage and the first feedback voltage. The output stage circuit is coupled to the input stage circuit to receive the first gating voltage and the second gating voltage, and the output stage circuit is used to generate the output voltage of the output buffer corresponding to the first gating voltage and the second gating voltage. The rise control circuit is used to compare the input voltage with the first feedback voltage to obtain the first comparison result. When the first comparison result indicates that the first feedback voltage is going to be increased, the rising control circuit pulls down the first gating voltage and the second gating voltage during the first transient period. The drop control circuit is used to compare the input voltage with the first feedback voltage to obtain a second comparison result. When the second comparison result indicates that the first feedback voltage is about to be pulled down, the down control circuit pulls up the first gating voltage and the second gating voltage during the second transient period.

Based on the above, the source driver and its output buffer of the embodiments of the present invention can compare the input voltage with the first feedback voltage. When the comparison result indicates that the first feedback voltage is about to be pulled up, the first gating voltage and the second gating voltage of the output stage circuit of the output buffer are pulled down to increase the slew rate of the output voltage. When the comparison result indicates that the first feedback voltage is going to be pulled down, the first gating voltage and the second gating voltage of the output stage circuit of the output buffer are pulled up to increase the slew rate of the output voltage.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

10: Display device

11: Gate driver

12: Source driver

12_1, 12_2, 12_m: drive channel circuit

13: display panel

100: output buffer

110: Input stage circuit

120: output stage circuit

130: Rise control circuit

131, 132: comparison circuit

140: Descent control circuit

141, 142: Comparison circuit

310, 510: current mirror

800: feedback circuit

810: Feedback voltage generating circuit

811: impedance circuit

1010: Latch

1020: Conversion circuit

1021: quasi-shifter

1022: Digital Analog Converter

1050: control circuit

1310: digital-to-analog conversion circuit

1311: digital analog converter

1312: unit gain buffer

DL_1, DL_2, DL_m: data line

EN, ENB: control signal

N1~N12, P1~P12: Transistor

NGATE, PGATE: gate voltage

P(1,1), P(m,1), P(1,n), P(m,n): pixel circuit

Pc: current pixel data

Pp: previous pixel data

R1, R2, R3, R4: voltage divider resistance

S1, S2, S3, S4, S5: control signal

S210~S270: steps

SL_1, SL_2, SL_n: scan line

SW1: Feedback switch

SW2, SW3, SW4, SW5: switch

T1: During overdrive

T2: During normal driving

VC1, VC2: control voltage

VDDA: system voltage

VFB, VFB1: feedback voltage

VIN: input voltage

VOUT: output voltage

VSSA: Reference voltage

FIG. 1 is a schematic diagram illustrating a circuit block of a display device according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram of a source driver according to an embodiment of the invention.

FIG. 3 is a schematic flowchart of an operation method of an output buffer according to an embodiment of the present invention.

4 is a block diagram illustrating the circuit block diagram of the rising control circuit shown in FIG. 2 according to an embodiment of the present invention.

FIG. 5 is a circuit block diagram illustrating the ascending control circuit shown in FIG. 2 according to another embodiment of the present invention.

FIG. 6 is a circuit block diagram illustrating the descending control circuit shown in FIG. 2 according to an embodiment of the present invention.

FIG. 7 is a circuit block diagram illustrating the descending control circuit shown in FIG. 2 according to another embodiment of the present invention.

FIG. 8 is a schematic block diagram of another circuit of a source driver according to an embodiment of the present invention.

FIG. 9 is a timing diagram of a source driver according to another embodiment of the present invention.

FIG. 10 is a circuit block diagram illustrating the driving channel circuit shown in FIG. 1 according to another embodiment of the present invention.

FIG. 11 is a circuit block diagram illustrating the impedance circuit shown in FIG. 10 according to another embodiment of the present invention.

FIG. 12 is a circuit block diagram illustrating the impedance circuit shown in FIG. 10 according to another embodiment of the present invention.

FIG. 13 is a circuit block diagram illustrating the impedance circuit shown in FIG. 10 according to still another embodiment of the present invention.

FIG. 14 is a circuit block diagram illustrating the impedance circuit shown in FIG. 10 according to another embodiment of the present invention.

The term "coupling (or connection)" used in the full description of the case (including the scope of the patent application) can refer to any direct or indirect connection means. For example, if it is described in the text that the first device is coupled (or connected) to the second device, it should be interpreted as that the first device can be directly connected to the second device, or the first device can be connected through other devices or some This kind of connection means is indirectly connected to the second device. In addition, wherever possible, elements/components/steps with the same reference numbers in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numerals or use the same terms in different embodiments may refer to related descriptions.

FIG. 1 is a schematic diagram illustrating a circuit block of a display device 10 according to an embodiment of the present invention. The display device 10 shown in FIG. 1 includes a gate driver 11, a source driver 12 and a display panel 13. The display panel 13 can be any type of flat panel display, such as a liquid crystal display panel, an organic light emitting diode display panel, or Other display panels. The display panel 13 includes a plurality of scan lines (or gate lines), a plurality of data lines (or source lines), and a plurality of pixel circuits. For example, as shown in FIG. 1, the multiple scan lines include n scan lines SL_1, SL_2,..., SL_n, and the multiple data lines include m data lines DL_1, DL_2,..., DL_m, and the multiple pixels The circuit contains m*n pixel circuits P(1,1),...,P(m,1),...,P(1,n),...,P(m,n), where m and n can be designed according to the design Any integer determined by demand.

The multiple output terminals of the gate driver 11 are coupled to different scan lines of the display panel 13 in a one-to-one manner. The gate driver 11 can scan/drive each scan line of the display panel 13. The gate driver 11 can be any type of gate driver. For example, according to design requirements, the gate driver 11 may be a conventional gate driver or other gate drivers.

The source driver 12 has a plurality of driving channel circuits, for example, m driving channel circuits 12_1, 12_2,..., 12_m shown in FIG. 1. The output terminals of these driving channel circuits 12_1-12_m are coupled to different data lines of the display panel 13 in a one-to-one manner. The driving channel circuits 12_1-12_m can convert digital pixel data into corresponding output voltages (pixel voltages), and output these output voltages to different data lines of the display panel 13 respectively. In accordance with the scanning timing of the gate driver 11, the source driver 12 can write these output voltages into the corresponding pixel circuits of the display panel 13 via the data lines DL_1 to DL_m to display images.

FIG. 2 is a circuit block diagram illustrating the driving channel circuit 12_1 shown in FIG. 1 according to an embodiment of the present invention. The other driving channel circuits 12_2~12_m shown in FIG. 1 can be deduced by referring to the related description of the driving channel circuit 12_1 shown in FIG. Narrated. The driving channel circuit 12_1 shown in FIG. 2 includes an output buffer 100 and a feedback circuit 800. The first input terminal of the output buffer 100 receives the input voltage VIN from the previous circuit (not shown), and the output terminal of the output buffer 100 outputs the output voltage VOUT to the latter circuit (for example, the data line DL_1 of the display panel 13), And the output voltage VOUT is fed back to the input terminal of the feedback circuit 800. According to the output voltage VOUT, the feedback circuit 800 can generate and output the feedback voltage VFB related to the output voltage VOUT to the second input terminal of the output buffer 100.

In the embodiment shown in FIG. 2, the output buffer 100 includes an input stage circuit 110, an output stage circuit 120, a rising control circuit 130 and a falling control circuit 140. According to design requirements, the input stage circuit 110 may include a differential input pair, a gain circuit, and/or other input stage circuits. For example, the input stage circuit 110 may be an input stage circuit of a conventional operational amplifier or an input stage circuit and/or a gain stage circuit of other amplifiers. The first input terminal of the input stage circuit 110 is coupled to the first input terminal of the output buffer 100 to receive the input voltage VIN. The second input terminal of the input stage circuit 110 is coupled to the output terminal of the feedback circuit 800 via the second input terminal of the output buffer 100 to receive the feedback voltage VFB. The input stage circuit 110 can generate the gating voltage PGATE and the gating voltage NGATE corresponding to the input voltage VIN and the feedback voltage VFB.

The first input terminal of the output stage circuit 120 is coupled to the first output terminal of the input stage circuit 110 to receive the gating voltage PGATE. The second input terminal of the output stage circuit 120 is coupled to the second output terminal of the input stage circuit 110 to receive the gating voltage NGATE. The output terminal of the output stage circuit 120 is coupled to the output terminal of the output buffer 100. The output stage circuit 120 can generate correspondingly according to the gating voltage PGATE and the gating voltage NGATE The output voltage VOUT of the output buffer 100. In an embodiment, the output voltage VOUT may be provided to the data line DL_1 of the display panel 13. The output terminal of the output stage circuit 120 is coupled to the input terminal of the feedback circuit 800 to provide an output voltage VOUT.

In the embodiment shown in FIG. 2, the output stage circuit 120 includes a transistor P1 and a transistor N1. The control terminal (eg, gate) of the transistor P1 is coupled to the first output terminal of the input stage circuit 110 to receive the gate control voltage PGATE. The first terminal (for example, the source) of the transistor P1 is coupled to the system voltage VDDA. The level of the system voltage VDDA can be determined according to design requirements. The second terminal (for example, the drain) of the transistor P1 is coupled to the output terminal of the output stage circuit 120, wherein the output terminal of the output stage circuit 120 outputs the output voltage VOUT. The control terminal (eg, gate) of the transistor N1 is coupled to the second output terminal of the input stage circuit 110 to receive the gate control voltage NGATE. The first terminal (for example, the source) of the transistor N1 is coupled to the reference voltage VSSA. The level of the reference voltage VSSA can be determined according to design requirements. The second terminal (for example, the drain) of the transistor N1 is coupled to the output terminal of the output stage circuit 120 and the second terminal of the transistor P1.

The output stage circuit 120 shown in FIG. 2 is an example. In any case, the implementation of the output stage circuit 120 should not be limited to the embodiment shown in FIG. 2. According to design requirements, the output stage circuit 120 may include any type of output circuit. For example, in other embodiments, the output stage circuit 120 may be the output stage circuit of a conventional operational amplifier or the output stage circuit of other amplifiers.

FIG. 3 is a schematic flowchart of an operation method of an output buffer according to an embodiment of the present invention. Please refer to Figure 2 and Figure 3. In step S210, the input stage circuit 110 is configured according to the input voltage VIN and the feedback voltage VFB of the output buffer 100 Correspondingly, the first gating voltage (for example, the gating voltage PGATE) and the second gating voltage (for example, the gating voltage NGATE) are generated. In step S220, the output stage circuit 120 correspondingly generates the output voltage VOUT of the output buffer 100 according to the gating voltage PGATE and the gating voltage NGATE. In step S230, the up control circuit 130 compares the input voltage VIN with the feedback voltage VFB to obtain a first comparison result, and the down control circuit 140 compares the input voltage VIN with the feedback voltage VFB to obtain a second comparison result.

When the first comparison result indicates that the feedback voltage VFB is about to be pulled up (step S240 is "to be pulled up"), the rising control circuit 130 can pull down the gate control voltage PGATE and the gate control voltage NGATE ( Step S250). When the rising control circuit 130 pulls down the gate voltage NGATE, the turn-off state of the transistor N1 can be ensured to avoid short-circuit current. When the rising control circuit 130 pulls down the gate control voltage PGATE, the current flowing through the transistor P1 can be temporarily increased to accelerate the pulling up of the output voltage VOUT. Therefore, the slew rate of the output voltage VOUT can be increased.

According to design requirements, in some embodiments, step S250 may include the following operations. When the input voltage VIN is greater than the feedback voltage VFB, the up control circuit 130 can pull down the gating voltage PGATE and the gating voltage NGATE. When the input voltage VIN is less than or equal to the feedback voltage VFB, the rising control circuit 130 may not adjust the gating voltage PGATE and the gating voltage NGATE.

When the first comparison result and the second comparison result both indicate that the feedback voltage VFB will not be changed (step S240 is "no change"), the rising control circuit 130 and the falling control circuit 140 may not adjust the gate voltage PGATE and gating voltage NGATE (step S260). When the rising control circuit 130 and the falling control circuit 140 do not interfere with the gate voltage PGATE and the gate voltage NGATE, the level of the gate voltage PGATE and the level of the gate voltage NGATE are determined by the input stage circuit 110.

When the second comparison result indicates that the feedback voltage VFB is about to be pulled down (step S240 is “to be pulled down”), the down control circuit 140 can pull up the gate voltage PGATE and the gate voltage NGATE ( Step S270). When the falling control circuit 140 raises the gate voltage PGATE, the turn-off state of the transistor P1 can be ensured to avoid short-circuit current. When the drop control circuit 140 pulls up the gate voltage NGATE, the current flowing through the transistor N1 can be temporarily increased to accelerate the pull down of the output voltage VOUT. Therefore, the slew rate of the output voltage VOUT can be improved.

According to design requirements, in some embodiments, step S270 may include the following operations. When the input voltage VIN is less than the feedback voltage VFB, the drop control circuit 140 can increase the gate voltage PGATE and the gate voltage NGATE. When the input voltage VIN is greater than or equal to the feedback voltage VFB, the drop control circuit 140 may not adjust the gate voltage PGATE and the gate voltage NGATE.

According to different design requirements, the implementation of the blocks of the ascending control circuit 130 and/or the descending control circuit 140 can be hardware, firmware, software (program) or the foregoing three. A combination of more than one of them. In terms of hardware, the blocks of the above-mentioned rising control circuit 130 and/or the falling control circuit 140 can be implemented in a logic circuit on an integrated circuit. The phase of the above-mentioned rising control circuit 130 and/or the falling control circuit 140 Related functions can be implemented as hardware using hardware description languages (for example, Verilog HDL or VHDL) or other suitable programming languages. For example, the related functions of the ascending control circuit 130 and/or the descending control circuit 140 may be implemented in one or more controllers, microcontrollers, microprocessors, and application-specific integrated circuits (Application-specific integrated circuit). ASIC), digital signal processor (DSP), Field Programmable Gate Array (FPGA) and/or various logic blocks, modules and circuits in other processing units.

In the embodiment shown in FIG. 2, the input terminal of the feedback circuit 800 is coupled to the output terminal of the output stage circuit 120 to receive the output voltage VOUT. The output terminal of the feedback circuit 800 is coupled to the second input terminal of the input stage circuit 110. The feedback circuit 800 generates and outputs a feedback voltage VFB related to the output voltage VOUT to the second input terminal of the input stage circuit 110 according to the output voltage VOUT.

FIG. 4 is a block diagram illustrating the circuit block diagram of the rising control circuit 130 shown in FIG. 2 according to an embodiment of the present invention. In the embodiment shown in FIG. 4, the rising control circuit 130 includes a comparison circuit 131, a transistor N2, and a transistor N3. The comparison circuit 131 can compare the input voltage VIN and the feedback voltage VFB to generate the control voltage VC1 as the first comparison result. The control terminal (eg, gate) of the transistor N2 is coupled to the output terminal of the comparison circuit 131 to receive the control voltage VC1. The first terminal (for example, the source) of the transistor N2 is coupled to the reference voltage VSSA. The second terminal (for example, the drain) of the transistor N2 is coupled to the first input terminal of the output stage circuit 120 to receive the gate voltage PGATE. The control terminal (such as the gate) of the transistor N3 is coupled to the output terminal of the comparison circuit 131 to receive the control Control voltage VC1. The first terminal (for example, the source) of the transistor N3 is coupled to the reference voltage VSSA. The second terminal (for example, the drain) of the transistor N3 is coupled to the second input terminal of the output stage circuit 120 to receive the gating voltage NGATE.

When the input voltage VIN is greater than the feedback voltage VFB, the comparison circuit 131 can turn on the transistor N2 and the transistor N3 by the control voltage VC1 to pull down the gate voltage PGATE and the gate voltage NGATE. When the input voltage VIN is less than or equal to the feedback voltage VFB, the comparison circuit 131 can turn off the transistor N2 and the transistor N3 by the control voltage VC1, so the rising control circuit 130 can not interfere (do not adjust) the gate control Voltage PGATE and gating voltage NGATE.

In the embodiment shown in FIG. 4, the comparison circuit 131 includes a transistor N4, a transistor N5, and a current mirror 310. The control terminal (such as the gate) of the transistor N4 is coupled to the input voltage VIN. The first terminal (for example, the source) of the transistor N4 is coupled to the feedback voltage VFB. The main current end of the current mirror 310 is coupled to the second end (for example, the drain) of the transistor N4. The slave current terminal of the current mirror 310 is coupled to the output terminal of the comparison circuit 131, wherein the output terminal of the comparison circuit 131 can provide the control voltage VC1 to the transistor N2 and the transistor N3. The control terminal (eg, gate) of the transistor N5 is coupled to the output terminal of the comparison circuit 131. The first terminal (for example, the source) of the transistor N5 is coupled to the reference voltage VSSA. The second terminal (for example, the drain) of the transistor N5 is coupled to the slave current terminal of the current mirror 310 and the control terminal of the transistor N5.

In the embodiment shown in FIG. 4, the current mirror 310 includes a transistor P2 and a transistor P3. The first terminal (for example, the source) of the transistor P2 is coupled to the system voltage VDDA. The second end (e.g. drain) and control end (e.g. gate) of transistor P2 are coupled to the current The main current end of the mirror 310. The first terminal (for example, the source) of the transistor P3 is coupled to the system voltage VDDA. The second terminal (for example, the drain) of the transistor P3 is coupled to the slave current terminal of the current mirror 310. The control terminal (such as the gate) of the transistor P3 is coupled to the control terminal of the transistor P2.

FIG. 5 is a circuit block diagram illustrating the ascending control circuit 130 shown in FIG. 2 according to another embodiment of the present invention. In the embodiment shown in FIG. 5, the rising control circuit 130 includes a comparison circuit 132, a transistor N2, and a transistor N3. The comparison circuit 132, the transistor N2, and the transistor N3 shown in FIG. 5 can be deduced by analogy with reference to the related description of the comparison circuit 131, the transistor N2 and the transistor N3 shown in FIG.

In the embodiment shown in FIG. 5, the comparison circuit 132 includes a transistor N6, a transistor N7, a transistor N8, a transistor N9, a transistor P4, and a current mirror 310. The control terminal (such as the gate) of the transistor N6 is coupled to the input voltage VIN. The first terminal (for example, the source) of the transistor N6 is coupled to the feedback voltage VFB. The control terminal (such as the gate) of the transistor N7 is controlled by the control signal EN. The first terminal (for example, the source) of the transistor N7 is coupled to the second terminal (for example, the drain) of the transistor N6.

The main current end of the current mirror 310 is coupled to the second end (for example, the drain) of the transistor N7. The slave current terminal of the current mirror 310 is coupled to the output terminal of the comparison circuit 132, wherein the output terminal of the comparison circuit 132 can provide the control voltage VC1 to the transistor N2 and the transistor N3. The current mirror 310 shown in FIG. 5 can be deduced by referring to the related description of the current mirror 310 shown in FIG. 4, so the details are not repeated here.

The control terminal (such as the gate) of the transistor P4 is controlled by the control signal EN. The first terminal (for example, the source) of the transistor P4 is coupled to the system voltage VDDA. Transistor P4 The second terminal (for example, the drain) of φ is coupled to the enable terminal of the current mirror 310. That is, the second end of the transistor P4 is coupled to the control end of the transistor P2 and the control end of the transistor P3. The control terminal (such as the gate) of the transistor N8 is coupled to the output terminal of the comparison circuit 132. The first terminal (for example, the source) of the transistor N8 is coupled to the reference voltage VSSA. The second terminal (for example, the drain) of the transistor N8 is coupled to the slave current terminal of the current mirror 310 and the control terminal of the transistor N8. The control terminal (such as the gate) of the transistor N9 is controlled by the control signal ENB. The control signal ENB is an inverted signal of the control signal EN. The first terminal (for example, the source) of the transistor N9 is coupled to the reference voltage VSSA. The second terminal (for example, the drain) of the transistor N9 is coupled to the control terminal of the transistor N8.

When the control signal EN is at a high voltage level (such as the level of the system voltage VDDA or other levels), that is, when the control signal ENB is at a low voltage level (such as the level of the reference voltage VSSA or other levels), The transistor N7 is turned on, and the transistor P4 and the transistor N9 are turned off. At this time, the operation of the comparison circuit 132 shown in FIG. 5 is similar to the operation of the comparison circuit 131 shown in FIG. 4. When the control signal EN is at a low voltage level (that is, the control signal ENB is at a high voltage level), the transistor N7 is turned off, and the transistor P4 and the transistor N9 are turned on. At this time, the comparison circuit 132 shown in FIG. 5 is blocked. Disable, and the control voltage VC1 is pulled down to a low voltage level. When the control voltage VC1 is pulled down to a low voltage level, the transistor N2 and the transistor N3 will be turned off. Therefore, when the control signal EN (control signal ENB) disables the rise control circuit 130, the rise control circuit 130 may not interfere (do not adjust) the gate voltage PGATE and the gate voltage NGATE.

In some application scenarios, after the feedback voltage VFB is pulled down, the feedback voltage VFB may be lower than (less than) the input voltage VIN during a specific period, and then the level of the feedback voltage VFB returns to be consistent with the input voltage VIN after the specific period ends. Generally speaking, the specific period is very short. Through the control of the control signal EN (control signal ENB), the rising control circuit 130 can be disabled during the specific period and enabled outside the specific period. Therefore, the malfunction of the rising control circuit 130 in the specific period can be avoided.

FIG. 6 is a circuit block diagram illustrating the descending control circuit 140 shown in FIG. 2 according to an embodiment of the present invention. In the embodiment shown in FIG. 6, the drop control circuit 140 includes a comparison circuit 141, a transistor P5, and a transistor P6. The comparison circuit 141 can compare the input voltage VIN and the feedback voltage VFB to generate the control voltage VC2 as the second comparison result. The control terminal (eg, gate) of the transistor P5 is coupled to the output terminal of the comparison circuit 141 to receive the control voltage VC2. The first terminal (for example, the source) of the transistor P5 is coupled to the system voltage VDDA. The second terminal (for example, the drain) of the transistor P5 is coupled to the first input terminal of the output stage circuit 120 to receive the gating voltage PGATE. The control terminal (eg, gate) of the transistor P6 is coupled to the output terminal of the comparison circuit 141 to receive the control voltage VC2. The first terminal (for example, the source) of the transistor P6 is coupled to the system voltage VDDA. The second terminal (for example, the drain) of the transistor P6 is coupled to the second input terminal of the output stage circuit 120 to receive the gating voltage NGATE.

When the input voltage VIN is less than the feedback voltage VFB, the comparison circuit 141 can turn on the transistor P5 and the transistor P6 by the control voltage VC2 to increase the gate voltage PGATE and the gate voltage NGATE. When the input voltage VIN is greater than or equal to the feedback voltage VFB, the comparison circuit 141 can be cut by the control voltage VC2. The transistor P5 and the transistor P6 are turned off, so the drop control circuit 140 may not interfere (do not adjust) the gate voltage PGATE and the gate voltage NGATE.

In the embodiment shown in FIG. 6, the comparison circuit 141 includes a transistor P7, a transistor P8 and a current mirror 510. The control terminal (such as the gate) of the transistor P7 is coupled to the input voltage VIN. The first terminal (for example, the source) of the transistor P7 is coupled to the feedback voltage VFB. The main current end of the current mirror 510 is coupled to the second end (for example, the drain) of the transistor P7. The slave current terminal of the current mirror 510 is coupled to the output terminal of the comparison circuit 141, wherein the output terminal of the comparison circuit 141 can provide the control voltage VC2 to the transistor P5 and the transistor P6. The control terminal (such as the gate) of the transistor P8 is coupled to the output terminal of the comparison circuit 141. The first terminal (for example, the source) of the transistor P8 is coupled to the system voltage VDDA. The second terminal (for example, the drain) of the transistor P8 is coupled to the slave current terminal of the current mirror 510 and the control terminal of the transistor P8.

In the embodiment shown in FIG. 6, the current mirror 510 includes a transistor N10 and a transistor N11. The first terminal (for example, the source) of the transistor N10 is coupled to the reference voltage VSSA. The second terminal (for example, the drain) and the control terminal (for example, the gate) of the transistor N10 are coupled to the main current terminal of the current mirror 510. The first terminal (for example, the source) of the transistor N11 is coupled to the reference voltage VSSA. The second terminal (for example, the drain) of the transistor N11 is coupled to the slave current terminal of the current mirror 510. The control terminal (eg, gate) of the transistor N11 is coupled to the control terminal of the transistor N10.

FIG. 7 is a circuit block diagram illustrating the descending control circuit 140 shown in FIG. 2 according to another embodiment of the present invention. In the embodiment shown in FIG. 7, the drop control circuit 140 includes a comparison circuit 142, a transistor P5, and a transistor P6. Figure 7 shows the comparison circuit 142, the transistor P5 and the transistor P6 can be deduced by referring to the related description of the comparison circuit 141, the transistor P5 and the transistor P6 shown in FIG.

In the embodiment shown in FIG. 7, the comparison circuit 142 includes a transistor P9, a transistor P10, a transistor P11, a transistor P12, a transistor N12, and a current mirror 510. The control terminal (such as the gate) of the transistor P9 is coupled to the input voltage VIN. The first terminal (for example, the source) of the transistor P9 is coupled to the feedback voltage VFB. The control terminal (such as the gate) of the transistor P10 is controlled by the control signal ENB. The first terminal (for example, the source) of the transistor P10 is coupled to the second terminal (for example, the drain) of the transistor P9.

The main current end of the current mirror 510 is coupled to the second end (for example, the drain) of the transistor P10. The slave current terminal of the current mirror 510 is coupled to the output terminal of the comparison circuit 142, wherein the output terminal of the comparison circuit 142 can provide the control voltage VC2 to the transistor P5 and the transistor P6. The current mirror 510 shown in FIG. 7 can be deduced by referring to the related description of the current mirror 510 shown in FIG. 6, so it is not repeated here.

The control terminal (such as the gate) of the transistor N12 is controlled by the control signal ENB. The first terminal (for example, the source) of the transistor N12 is coupled to the reference voltage VSSA. The second terminal (for example, the drain) of the transistor N12 is coupled to the enable terminal of the current mirror 510. That is, the second terminal of the transistor N12 is coupled to the control terminal of the transistor N10 and the control terminal of the transistor N11. The control terminal (such as the gate) of the transistor P11 is coupled to the output terminal of the comparison circuit 142. The first terminal (for example, the source) of the transistor P11 is coupled to the system voltage VDDA. The second terminal (for example, the drain) of the transistor P11 is coupled to the slave current terminal of the current mirror 510 and the control terminal of the transistor P11. The control terminal (such as the gate) of the transistor P12 is controlled by the control signal EN. The control signal EN is an inverted signal of the control signal ENB. The first terminal (for example, the source) of the transistor P12 is coupled to the system voltage VDDA. The second terminal (for example, the drain) of the transistor P12 is coupled to the control terminal of the transistor P11.

When the control signal EN is at a high voltage level (such as the level of the system voltage VDDA or other levels), that is, when the control signal ENB is at a low voltage level (such as the level of the reference voltage VSSA or other levels), The transistor P10 is turned on, and the transistor N12 and the transistor P12 are turned off. At this time, the operation of the comparison circuit 142 shown in FIG. 7 is similar to the operation of the comparison circuit 141 shown in FIG. 6. When the control signal EN is at a low voltage level (that is, the control signal ENB is at a high voltage level), the transistor P10 is turned off, and the transistor N12 and the transistor P12 are turned on. At this time, the comparison circuit 142 shown in FIG. 7 is blocked. Disable, and the control voltage VC2 is pulled up to a high voltage level. When the control voltage VC2 is pulled up to a high voltage level, the transistor P5 and the transistor P6 will be turned off. Therefore, when the control signal EN (control signal ENB) disables the down control circuit 140, the down control circuit 140 may not interfere (do not adjust) the gate voltage PGATE and the gate voltage NGATE.

In some application scenarios, after the feedback voltage VFB is pulled up, the feedback voltage VFB may exceed (greater than) the input voltage VIN for a specific period, and then the level of the feedback voltage VFB returns to Consistent with the input voltage VIN. Generally speaking, the specific period is very short. Through the control of the control signal EN (control signal ENB), the falling control circuit 140 can be disabled during the specific period and enabled outside the specific period. Therefore, the malfunction of the falling control circuit 140 in the specific period can be avoided.

FIG. 8 illustrates the feedback circuit 800 shown in FIG. 2 according to an embodiment of the present invention Schematic diagram of the circuit block. In the embodiment shown in FIG. 8, the feedback circuit 800 includes a feedback switch SW1 and a feedback voltage generating circuit 810. The first terminal of the feedback switch SW1 is coupled to the second input terminal of the input stage circuit 110 of the output buffer 100. The second terminal of the feedback switch SW1 is coupled to the output terminal of the output stage circuit 120 of the output buffer 100. The feedback switch SW1 is controlled by the control signal S1. The feedback switch SW1 is turned off during the overdrive period and turned on during the normal drive period. When the feedback switch SW1 is turned on, the output buffer 100 is equivalent to a unity gain buffer. At this time, the output voltage VOUT is used as the feedback voltage VFB to be fed back to the second input terminal of the input stage circuit 110 of the output buffer 100. Therefore, the output voltage VOUT can follow the input voltage VIN.

The output terminal of the feedback voltage generating circuit 810 is coupled to the second input terminal of the input stage circuit 110 of the output buffer 100. The input terminal of the feedback voltage generating circuit 810 is coupled to the output terminal of the output stage circuit 120 of the output buffer 100 to receive the output voltage VOUT. During the over-driving period, the feedback voltage generating circuit 810 can generate and output the feedback voltage VFB related to the output voltage VOUT to the second input terminal of the input stage circuit 110 of the output buffer 100. When the input voltage VIN is in the "rising mode", the feedback voltage VFB is lower than the output voltage VOUT. When the input voltage VIN is in the "falling mode", the feedback voltage VFB is higher than the output voltage VOUT. Therefore, the output buffer 100 can be overdriven during the overdrive period to increase the slew rate of the output voltage VOUT. During the normal driving period, the feedback voltage generating circuit 810 may not output the feedback voltage VFB to the second input terminal of the output buffer 100. That is, the feedback voltage generating circuit 810 may not interfere with the second input terminal of the output buffer 100 during the normal driving period.

In the embodiment shown in FIG. 8, the feedback voltage generating circuit 810 includes a switch SW2, a switch SW3, a voltage dividing resistor R1, and an impedance circuit 811. The switch SW2 is controlled by the control signal S2, and the switch SW3 is controlled by the control signal S3. During the overdrive period, the switch SW2 and the switch SW3 are turned on. During the normal driving period, the switch SW2 and the switch SW3 are turned off. The first terminal of the switch SW2 is coupled to the output terminal of the output stage circuit 120 of the output buffer 100. The first terminal of the switch SW3 is coupled to the second input terminal of the input stage circuit 110 of the output buffer 100.

The first end of the voltage dividing resistor R1 is coupled to the second end of the switch SW2. The second end of the voltage dividing resistor R1 is coupled to the second end of the switch SW3. The impedance circuit 811 is coupled to the second end of the voltage dividing resistor R1 to provide impedance. The voltage dividing resistor R1 and the impedance circuit 811 can perform a voltage dividing operation to generate a feedback voltage VFB1 related to the output voltage VOUT. Wherein, when the switch SW3 is turned on, the feedback voltage VFB1 is transmitted to the second input terminal of the input stage circuit 110 as the feedback voltage VFB. When the switch SW3 is turned off, the feedback voltage generating circuit 810 may not interfere with the second input terminal of the input stage circuit 110.

FIG. 9 is a timing diagram of a source driver according to another embodiment of the present invention. The horizontal axis shown in FIG. 9 represents time, and the vertical axis represents signal level. Please refer to Figure 5, Figure 7, Figure 8 and Figure 9 at the same time. When the input voltage VIN is in the rising mode, the impedance circuit 811 outputs a feedback voltage VFB1 lower than the output voltage VOUT. During the overdrive period T1, the control signal S2 and the control signal S3 are at a high logic level, and the control signal S1 is at a low logic level, so the switch SW2 and the switch SW3 are turned on, and the switch SW1 is not turned on, which is lower than the output voltage VOUT. The feedback voltage VFB1 is provided to the second input terminal of the input stage circuit 110 of the output buffer 100 through the switch SW3. Thus, in During the overdrive period, the T1 output voltage VOUT can be higher than the target standard level. When the input voltage VIN is in the falling mode, the impedance circuit 811 outputs a feedback voltage VFB1 higher than the output voltage VOUT. That is, the feedback voltage VFB1 higher than the output voltage VOUT is provided to the second input terminal of the input stage circuit 110 of the output buffer 100 through the switch SW3 during the overdrive period T1 (the feedback switch SW1 is turned off at this time). Therefore, the T1 output voltage VOUT can be lower than the target level during the overdrive period.

During the normal driving period T2, the control signal S2 and the control signal S3 are at a low logic level, and the control signal S1 is at a high logic level. Therefore, the switch SW2 and the switch SW3 are not turned on, and the switch SW1 is turned on, and the feedback voltage VFB1 is not It is provided to the second input terminal of the input stage circuit 110 of the output buffer 100. Therefore, during the normal driving period T2, the output voltage VOUT can be restored to the target level (for example, the level of the input voltage VIN). The operation timing of the control signal EN for the rising control circuit 130 and the falling control circuit 140 has been described in FIGS. 5 and 7, and will not be repeated.

FIG. 10 is a circuit block diagram illustrating the driving channel circuit 12_1 shown in FIG. 1 according to another embodiment of the present invention. The other driving channel circuits 12_2 to 12_m shown in FIG. 1 can be deduced by referring to the related description of the driving channel circuit 12_1 shown in FIG. The driving channel circuit 12_1 shown in FIG. 10 includes a latch 1010, a conversion circuit 1020, an output buffer 100, and a feedback circuit 800. The latch 1010 can provide the current pixel data Pc to the conversion circuit 1020. The latch 1010 may be any type of latch. For example, according to design requirements, the latch 1010 may be a conventional wire latch or other latches.

The conversion circuit 1020 can convert the current pixel data Pc into an analog voltage (with Hereinafter referred to as the input voltage VIN), and output the input voltage VIN to the output buffer 100. In the embodiment shown in FIG. 10, the conversion circuit 1020 may include a level shifter (leve1 shifter) 1021 and a digital to analog converter (DAC) 1022. The level shifter 1021 can increase the voltage swing of the current pixel data Pc, and the digital-to-analog converter 1022 can convert the current pixel data into the input voltage VIN. The digital-to-analog converter 1022 can output the input voltage VIN to the output buffer 100. In other embodiments, the quasi-shifter 1021 may be omitted due to design requirements, so that the digital-to-analog converter 1022 can directly receive the current pixel data Pc.

The output buffer 100 shown in FIG. 10 can be deduced by analogy with reference to the related descriptions in FIGS. 2 to 9, so the details are not described again. The first input terminal (for example, a non-inverting input terminal) of the output buffer 100 is coupled to the output terminal of the digital-to-analog converter 1022 to receive the input voltage VINT. The output terminal of the output buffer 100 can generate an output voltage VOUT to the data line DL_1 of the display panel 13 and the input terminal of the feedback circuit 800. According to the output voltage VOUT, the feedback circuit 800 can generate and output a feedback voltage VFB related to the output voltage VOUT to the second input terminal (for example, an inverting input terminal) of the output buffer 100. The feedback circuit 800 shown in FIG. 10 can be deduced by analogy with reference to the related descriptions of FIGS. 2 to 9, so it will not be repeated.

According to the requirements of the application environment, the control circuit 1050 can selectively divide a scan line period (a period during which a pixel circuit is turned on) into an overdrive period and a normal drive period. Based on the control circuit 1050 controlling the feedback switch SW1 and the feedback voltage generating circuit 810, the output buffer 100 can be The data line DL_1 is overdriven during the overdriving period, and the data line DL_1 is normally driven during the normal driving period. The output buffer 100 can overdrive the data line DL_1 of the display panel 13 during the overdrive period to increase the slew rate of the output voltage VOUT. Based on this, the internal electrical parameters of the output buffer 100, such as tail current, do not need to be adjusted/changed in order to increase the slew rate.

According to the requirements of the application environment, the control circuit 1050 can also selectively use one scan line period (a period during which a pixel circuit is turned on) as a normal driving period. That is, the overdrive operation performed by the output buffer 100 on the data line DL_1 can be selectively disabled.

Regarding the time length of the over-driving period, it can be selectively set according to the requirements of the application environment. In the embodiment shown in FIG. 1, the data line DL_1 is coupled to the near pixel circuit (for example, the pixel circuit P(1,1)) and the far pixel circuit (for example, the pixel circuit P(1,n)) of the display panel 13. The distance from the near pixel circuit to the source driver 12 is smaller than the distance from the far pixel circuit to the source driver 12. Generally speaking, the time constant of the far pixel circuit is greater than the time constant of the near pixel circuit. Based on design requirements, the control circuit 1050 can dynamically adjust the time length of the over-driving period according to the position of the pixel circuit in the display panel 13 (the distance from the pixel circuit to the source driver 12). For example, the time length of the overdrive period related to the near pixel circuit is smaller than the time length of the overdrive period related to the far pixel circuit.

The feedback switch SW1 is controlled by the control signal S1 of the control circuit 1050. The control circuit 1050 turns off the feedback switch SW1 during the over-driving period, and turns on the feedback switch SW1 during the normal driving period. When the feedback switch SW1 is on, the output voltage VOUT It is used as the feedback voltage VFB to be fed back to the second input terminal of the output buffer 100. Therefore, the output voltage VOUT can follow the input voltage VIN.

During the over-driving period, the feedback voltage generating circuit 810 can generate and output the feedback voltage VFB related to the output voltage VOUT to the second input terminal of the output buffer 100. When the input voltage VIN is in the "rising mode", the feedback voltage VFB is lower than the output voltage VOUT. When the input voltage VIN is in the "falling mode", the feedback voltage VFB is higher than the output voltage VOUT. Therefore, the output buffer 100 can overdrive the data line DL_1 of the display panel 13 during the overdrive period to increase the slew rate of the output voltage VOUT. During the normal driving period, the feedback voltage generating circuit 810 may not output the feedback voltage VFB1 to the second input terminal of the output buffer 100. That is, the feedback voltage generating circuit 810 may not interfere with the second input terminal of the output buffer 100 during the normal driving period.

In the embodiment shown in FIG. 10, "the input voltage VIN is in the rising mode" can be defined as "the input voltage VIN corresponding to the current pixel data Pc is greater than the input voltage VIN corresponding to the previous pixel data", and "the input voltage VIN is in the The falling mode" can be defined as "the input voltage VIN corresponding to the current pixel data Pc is less than the input voltage VIN corresponding to the previous pixel data". The previous pixel data can be understood as the current pixel data Pc in the previous scan line period. In contrast, the current pixel data Pc is the pixel data in the current scan line period. The control circuit 1050 can check the current pixel data Pc and the previous pixel data to determine whether the input voltage VIN should be pulled up or pulled down.

When the current pixel data Pc is greater than the previous pixel data and the channel circuit is driven When 12_1 operates in positive polarity, the control circuit 1050 can determine that "the input voltage VIN is going to be pulled up." Alternatively, when the current pixel data Pc is less than the previous pixel data and the driving channel circuit 12_1 is operating in negative polarity, the control circuit 1050 may determine that "the input voltage VIN is to be raised". That is, the input voltage VIN is in the rising mode. When the input voltage VIN is in the rising mode, the control circuit 1050 controls the feedback voltage generating circuit 810 so that the feedback voltage VFB1 is lower than the output voltage VOUT. The feedback voltage VFB1 is provided to the second input terminal of the output buffer 100 as the feedback voltage VFB during the over-driving period (the feedback switch SW1 is turned off at this time). Therefore, the output voltage VOUT1 can be higher than the target level during the over-driving period. The target standard level may meet the level of the input voltage VIN. The feedback voltage VFB1 will not be provided to the second input terminal of the output buffer 100 during the normal driving period (the feedback switch SW1 is turned on at this time). Therefore, the output voltage VOUT can be restored to the target level (for example, the level of the input voltage VIN) during the normal driving period.

When the current pixel data Pc is less than the previous pixel data and the driving channel circuit 12_1 is operating in positive polarity, the control circuit 1050 can determine that "the input voltage VIN is to be pulled down." Alternatively, when the current pixel data Pc is greater than the previous pixel data and the driving channel circuit 12_1 is operating in negative polarity, the control circuit 1050 may determine that "the input voltage VIN is to be pulled down." That is, the input voltage VIN is in a falling mode. When the input voltage VIN is in the falling mode, the control circuit 1050 controls the feedback voltage generating circuit 810 so that the feedback voltage VFB1 is higher than the output voltage VOUT. The feedback voltage VFB1 is provided to the second input terminal of the output buffer 100 as the feedback voltage VFB during the over-driving period (the feedback switch SW1 is turned off at this time). Therefore, during the overdrive period, the output voltage VOUT Can be lower than the target standard position. The target standard level may meet the level of the input voltage VIN. The feedback voltage VFB1 will not be provided to the second input terminal of the output buffer 100 during the normal driving period (the feedback switch SW1 is turned on at this time). Therefore, the output voltage VOUT can be restored to the target level (for example, the level of the input voltage VIN) during the normal driving period.

In other embodiments, according to design requirements (for some special display panels), when the current pixel data Pc is less than the previous pixel data and the driving channel circuit 12_1 operates in positive polarity, the control circuit 1050 can determine that "the input voltage VIN is to be pulled up." ". Alternatively, when the current pixel data Pc is greater than the previous pixel data and the driving channel circuit 12_1 operates in negative polarity, the control circuit 1050 may determine that "the input voltage VIN is to be pulled up." That is, the input voltage VIN is in the rising mode.

In other embodiments, according to different design requirements (for some special display panels), when the current pixel data Pc is greater than the previous pixel data and the driving channel circuit 12_1 is operating in positive polarity, the control circuit 1050 can determine that "the input voltage VIN is to be Pull down. Alternatively, when the current pixel data Pc is less than the previous pixel data and the driving channel circuit 12_1 is operating in negative polarity, the control circuit 1050 may determine that "the input voltage VIN is to be pulled down." That is, the input voltage VIN is in a falling mode.

FIG. 11 is a circuit block diagram illustrating the impedance circuit 811 shown in FIG. 10 according to an embodiment of the present invention. In the embodiment shown in FIG. 11, the impedance circuit 811 includes a voltage dividing resistor R2, a switch SW4, and a switch SW5. The first end of the voltage dividing resistor R2 is coupled to the second end of the voltage dividing resistor R1. The resistance ratio of the voltage divider resistor R1 to the voltage divider resistor R2 can be determined according to design requirements. The voltage dividing resistor R1 and the voltage dividing resistor R2 can perform a voltage dividing operation to generate a feedback voltage VFB1 related to the output voltage VOUT.

The first end of the switch SW4 and the first end of the switch SW5 are commonly coupled to the second end of the voltage dividing resistor R2. The second terminal of the switch SW4 is coupled to the reference voltage VSSA. According to design requirements, the reference voltage VSSA can be any voltage lower than the output voltage VOUT, such as the ground voltage or other fixed voltages. The second end of the switch SW5 is coupled to the system voltage VDDA. According to design requirements, the system voltage VDDA can be any voltage higher than the output voltage VIN. The switch SW4 is controlled by the control signal S4 of the control circuit 1050, and the switch SW5 is controlled by the control signal S5 of the control circuit 1050. When the input voltage VIN is in the rising mode, the control circuit 1050 turns on the switch SW4 and turns off the switch SW5. When the input voltage VIN is in the falling mode, the control circuit 1050 turns off the switch SW4 and turns on the switch SW5.

FIG. 12 is a circuit block diagram illustrating the impedance circuit 811 shown in FIG. 10 according to another embodiment of the present invention. In the embodiment shown in FIG. 12, the impedance circuit 811 includes a voltage dividing resistor R3, a voltage dividing resistor R4, a switch SW4, and a switch SW5. The first end of the switch SW4 is coupled to the second end of the voltage dividing resistor R1. The first end of the voltage dividing resistor R3 is coupled to the second end of the switch SW4. The second end of the voltage dividing resistor R3 is coupled to the reference voltage VSSA. According to design requirements, the reference voltage VSSA can be any voltage lower than the output voltage VOUT, such as the ground voltage or other fixed voltages. The switch SW4 is controlled by the control signal S4 of the control circuit 1050. When the input voltage VIN is in the rising mode, the control circuit 1050 turns on the switch SW4. When the input voltage VIN is in the falling mode, the control circuit 1050 turns off the switch SW4.

The first end of the switch SW5 is coupled to the second end of the voltage dividing resistor R1. The first end of the voltage dividing resistor R4 is coupled to the second end of the switch SW5. The second end of the divider resistor R4 Coupled to the system voltage VDDA. According to design requirements, the system voltage VDDA can be any voltage higher than the output voltage VOUT. The switch SW5 is controlled by the control signal S5 of the control circuit 1050. When the input voltage VIN is in the rising mode, the control circuit 1050 turns off the switch SW5. When the input voltage VIN is in the falling mode, the control circuit 1050 turns on the switch SW5.

The resistance value of the voltage divider R3 and the resistance value of the voltage divider R4 can be determined according to design requirements. For example, the resistance value of the voltage dividing resistor R3 may be different from the resistance value of the voltage dividing resistor R4. Therefore, when the input voltage VIN is in the rising mode, the voltage dividing resistor R1 and the voltage dividing resistor R3 can provide the first resistance ratio. When the input voltage VIN is in the falling mode, the voltage dividing resistor R1 and the voltage dividing resistor R4 can provide a second resistance ratio, where the second resistance ratio is different from the first resistance ratio.

FIG. 13 is a circuit block diagram illustrating the impedance circuit 811 shown in FIG. 10 according to still another embodiment of the present invention. In the embodiment shown in FIG. 13, the impedance circuit 811 includes a voltage divider resistor R2 and a digital-to-analog conversion circuit 1310. The first end of the voltage dividing resistor R2 is coupled to the second end of the voltage dividing resistor R1. The voltage divider resistor R2 shown in FIG. 13 can be deduced by analogy with reference to the relevant description of the voltage divider resistor R2 shown in FIG. 11, so it will not be repeated.

The control circuit 1050 can record the current pixel data Pc in the previous scan line period as the previous pixel data Pp. The input terminal of the digital-to-analog conversion circuit 1310 is coupled to the control circuit 1050 to receive the previous pixel data Pp. The output terminal of the digital-to-analog conversion circuit 1310 is coupled to the second terminal of the voltage dividing resistor R2. The digital-to-analog conversion circuit 1310 can convert the previous pixel data Pp into the previous voltage Vp. The digital-to-analog conversion circuit 1310 can output the previous voltage Vp to the second end of the voltage dividing resistor R2. When currently When the pixel data Pc is greater than the previous pixel data Pp and the driving channel circuit 12_1 operates in positive polarity, the input voltage VIN related to the current pixel data Pc is greater than the previous voltage Vp related to the previous pixel data Pp, so that the feedback voltage VFB1 is lower than the output voltage VOUT. When the current pixel data Pc is less than the previous pixel data Pp and the driving channel circuit 12_1 operates in positive polarity, the input voltage VIN related to the current pixel data Pc is less than the previous voltage Vp related to the previous pixel data Pp, so that the feedback voltage VFB1 is higher than The output voltage VOUT.

When the current pixel data Pc is less than the previous pixel data Pp and the driving channel circuit 12_1 operates in negative polarity, the input voltage VIN related to the current pixel data Pc is greater than the previous voltage Vp related to the previous pixel data Pp, so that the feedback voltage VFB1 is lower than The output voltage VOUT. When the current pixel data Pc is greater than the previous pixel data Pp and the driving channel circuit 12_1 operates in negative polarity, the input voltage Vi related to the current pixel data Pc is less than the previous voltage Vp related to the previous pixel data Pp, so that the feedback voltage VFB1 is higher than The output voltage VOUT.

In other embodiments, according to different design requirements (for some special display panels), when the current pixel data Pc is smaller than the previous pixel data Pp and the driving channel circuit 12_1 operates in positive polarity, the input voltage VIN related to the current pixel data Pc It is greater than the previous voltage Vp related to the previous pixel data Pp, so that the feedback voltage VFB1 is lower than the output voltage VOUT. When the current pixel data Pc is greater than the previous pixel data Pp and the driving channel circuit 12_1 operates in positive polarity, the input voltage Vi related to the current pixel data Pc is less than the previous voltage Vp related to the previous pixel data Pp, so that the feedback voltage VFB1 is higher than The output voltage VOUT.

In other embodiments, according to different design requirements (for some special display panels), when the current pixel data Pc is greater than the previous pixel data Pp and the driving channel circuit 12_1 operates in negative polarity, the input voltage VIN related to the current pixel data Pc It is greater than the previous voltage Vp related to the previous pixel data Pp, so that the feedback voltage VFB1 is lower than the output voltage VOUT. When the current pixel data Pc is smaller than the previous pixel data Pp and the driving channel circuit 12_1 operates in negative polarity, the input voltage Vi related to the current pixel data Pc is less than the previous voltage Vp related to the previous pixel data Pp, so that the feedback voltage VFB1 is higher than The output voltage VOUT.

In the embodiment shown in FIG. 13, the digital-to-analog conversion circuit 1310 includes a digital-to-analog converter 1311 and a unit gain buffer 1312. The input terminal of the digital-to-analog converter 1311 is coupled to the control circuit 1050 to receive the previous pixel data Pp. The input terminal of the unit gain buffer 1312 is coupled to the output terminal of the digital-to-analog converter 1311. The output terminal of the unit gain buffer 1312 is coupled to the second terminal of the voltage dividing resistor R2 to provide the previous voltage Vp. The digital-to-analog conversion circuit 1310 can dynamically change to the previous voltage Vp according to the previous pixel data Pp. In other embodiments, the digital-to-analog conversion circuit 1310 can freely set the previous voltage Vp to the system voltage VDDA, the reference voltage VSSA or any other voltage.

FIG. 14 is a circuit block diagram illustrating the impedance circuit 811 shown in FIG. 10 according to another embodiment of the present invention. In the embodiment shown in FIG. 14, the impedance circuit 811 includes a voltage dividing resistor R3, a voltage dividing resistor R4, a switch SW4, a switch SW5, and a digital-to-analog conversion circuit 1310. The voltage dividing resistor R3, voltage dividing resistor R4, switch SW4, and switch SW5 shown in Figure 6 can refer to the voltage dividing resistor R3, voltage dividing resistor R4, and switch SW4 shown in Figure 4 And the related description of the switch SW5 is analogized, so it will not be repeated.

The first end of the voltage dividing resistor R3 is coupled to the second end of the switch SW34. The first end of the voltage dividing resistor R4 is coupled to the second end of the switch SW5. The output end of the digital-to-analog conversion circuit 1310 is coupled to the second end of the voltage dividing resistor R3 and the second end of the voltage dividing resistor R4. The digital-to-analog conversion circuit 1310 can convert the previous pixel data Pp into the previous voltage Vp. The digital-to-analog conversion circuit 1310 can output the previous voltage Vp to the second end of the voltage dividing resistor R3 and the second end of the voltage dividing resistor R4. The digital-to-analog conversion circuit 1310 shown in FIG. 14 can be deduced by referring to the related description of the digital-to-analog conversion circuit 1310 shown in FIG. 13, so it will not be repeated here.

According to different design requirements, the implementation of the blocks of the control circuit 1050 may be hardware, firmware, software (ie, programs), or a combination of more of the three. In terms of hardware, the blocks of the control circuit 1050 described above can be implemented in a logic circuit on an integrated circuit. The above-mentioned related functions of the control circuit 1050 can be implemented as hardware using a hardware description language (for example, Verilog HDL or VHDL) or other suitable programming languages. For example, the related functions of the above-mentioned control circuit 1050 can be implemented in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASIC), digital signal processors (DSP), field programmable Various logic blocks, modules and circuits in a logic gate array (FPGA) and/or other processing units.

In summary, the source driver 12 and its output buffer 100 according to the embodiments of the present invention can selectively change the feedback voltage VFB of the output buffer 100. The period during which one pixel is driven may include an overdrive period and a normal drive period. The feedback circuit 800 in the source driver 12 can be adjusted high (or adjusted during the overdriving period). Low) The feedback voltage VFB of the buffer 100 is output, and the output buffer 100 can compare the input voltage VIN with the feedback voltage VFB. When the comparison result indicates that when the feedback voltage VFB is about to be pulled up, the gating voltage PGATE and the gating voltage NGATE of the output stage circuit 120 of the output buffer 100 are pulled down to increase the slew rate of the output voltage VOUT. When the feedback voltage VFB is about to be pulled down, the gating voltage PGATE and the gating voltage NGATE of the output stage circuit 120 of the output buffer 100 are pulled up to increase the slew rate of the output voltage VOUT. Therefore, the source driver 12 of the present invention can overdrive the output voltage VOUT in a short time.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

12_1: drive channel circuit

100: output buffer

110: Input stage circuit

120: output stage circuit

130: Rise control circuit

140: Descent control circuit

800: feedback circuit

N1, P1: Transistor

NGATE, PGATE: gate voltage

VDDA: system voltage

VFB: Feedback voltage

VIN: input voltage

VOUT: output voltage

VSSA: Reference voltage

Claims (33)

A source driver includes an output buffer and a feedback circuit, wherein the output buffer includes: an input stage circuit having a first input terminal and a second input terminal, wherein the first input stage circuit The input terminal receives an input voltage of the output buffer, the second input terminal of the input stage circuit is coupled to an output terminal of the feedback circuit to receive a first feedback voltage, and the input stage circuit is configured to According to the input voltage and the first feedback voltage, a first gating voltage and a second gating voltage are generated correspondingly; an output stage circuit is coupled to the input stage circuit to receive the first gating voltage and the The second gating voltage is configured to generate an output voltage of the output buffer to a data line of a display panel according to the first gating voltage and the second gating voltage, wherein the output stage circuit An output terminal is coupled to an input terminal of the feedback circuit; a rise control circuit is configured to compare the input voltage with the first feedback voltage to obtain a first comparison result, wherein when the first comparison result Indicates that the first feedback voltage is to be increased, that is, when the input voltage is greater than the first feedback voltage, the rising control circuit pulls down the first gate control voltage and the second gate control during a first transient period Voltage; and a drop control circuit configured to compare the input voltage with the first feedback voltage to obtain a second comparison result, wherein when the second comparison result indicates that the first feedback voltage is to be pulled down, That is, when the input voltage is less than the first feedback voltage, the down control circuit pulls up the first gate control voltage and the second gate control during a second transient period. Voltage, wherein the feedback circuit is used to generate and output the first feedback voltage related to the output voltage to the second input terminal of the input stage circuit. The source driver according to claim 1, wherein the output stage circuit includes: a first transistor having a control terminal coupled to the input stage circuit to receive the first gate control voltage, wherein the first gate control voltage A first end of a transistor is coupled to a system voltage, a second end of the first transistor is coupled to the output end of the output stage circuit; and a second transistor has a control end coupled To the input stage circuit to receive the second gating voltage, wherein a first terminal of the second transistor is coupled to a reference voltage, and a second terminal of the second transistor is coupled to the output stage circuit The output terminal. The source driver as described in item 1 of the scope of patent application, wherein when the input voltage is greater than the first feedback voltage, the rising control circuit pulls down the first gate control voltage and the second gate control voltage, and when When the input voltage is less than or equal to the first feedback voltage, the rising control circuit does not adjust the first gating voltage and the second gating voltage. The source driver according to claim 1, wherein the rising control circuit includes: a comparison circuit configured to compare the input voltage with the first feedback voltage to generate a control voltage as the first comparison Result; a first transistor with a control terminal coupled to an output terminal of the comparison circuit To receive the control voltage, wherein a first terminal of the first transistor is coupled to a reference voltage, and a second terminal of the first transistor is coupled to a first input terminal of the output stage circuit to receive the A first gate control voltage; and a second transistor having a control terminal coupled to the output terminal of the comparison circuit to receive the control voltage, wherein a first terminal of the second transistor is coupled to the reference voltage A second terminal of the second transistor is coupled to a second input terminal of the output stage circuit to receive the second gating voltage. The source driver according to claim 4, wherein the comparison circuit includes: a third transistor having a control terminal coupled to the input voltage, wherein a first terminal of the third transistor is coupled To the first feedback voltage; a current mirror with a main current terminal coupled to a second terminal of the third transistor, wherein a slave current terminal of the current mirror is coupled to the output terminal of the comparison circuit And a fourth transistor having a control terminal coupled to the output terminal of the comparison circuit, wherein a first terminal of the fourth transistor is coupled to the reference voltage, a second of the fourth transistor The terminal is coupled to the slave current terminal of the current mirror. The source driver according to claim 4, wherein the comparison circuit includes: a third transistor having a control terminal coupled to the input voltage, wherein a first terminal of the third transistor is coupled To the first feedback voltage; a fourth transistor with a control terminal controlled by a first control signal, wherein A first end of the fourth transistor is coupled to a second end of the third transistor; a current mirror having a main current end coupled to a second end of the fourth transistor, wherein the current A slave current terminal of the mirror is coupled to the output terminal of the comparison circuit; a fifth transistor having a control terminal controlled by the first control signal, wherein a first terminal of the fifth transistor is coupled to A system voltage, the second end of the fifth transistor is coupled to the uniform energy end of the current mirror; and a sixth transistor having a control end coupled to the output end of the comparison circuit, wherein the sixth transistor A first terminal of the transistor is coupled to the reference voltage, and a second terminal of the sixth transistor is coupled to the slave current terminal of the current mirror. According to the source driver described in claim 6, wherein the comparison circuit further includes: a seventh transistor having a control terminal controlled by a second control signal, wherein a first control signal of the seventh transistor The terminal is coupled to the reference voltage, and a second terminal of the seventh transistor is coupled to the control terminal of the sixth transistor. The source driver as described in item 1 of the scope of patent application, wherein when the input voltage is less than the first feedback voltage, the down control circuit pulls up the first gating voltage and the second gating voltage, and when When the input voltage is greater than or equal to the first feedback voltage, the drop control circuit does not adjust the first gating voltage and the second gating voltage. The source driver according to claim 1, wherein the drop control circuit includes: a comparison circuit configured to compare the input voltage with the first feedback voltage A control voltage is generated as the second comparison result; a first transistor has a control terminal coupled to an output terminal of the comparison circuit to receive the control voltage, wherein a first terminal of the first transistor is coupled Connected to a system voltage, a second terminal of the first transistor is coupled to a first input terminal of the output stage circuit to receive the first gate control voltage; and a second transistor having a control terminal coupled Connected to the output terminal of the comparison circuit to receive the control voltage, wherein a first terminal of the second transistor is coupled to the system voltage, and a second terminal of the second transistor is coupled to the output stage circuit To receive the second gating voltage. The source driver according to claim 9, wherein the comparison circuit includes: a third transistor having a control terminal coupled to the input voltage, wherein a first terminal of the third transistor is coupled To the first feedback voltage; a current mirror with a main current terminal coupled to a second terminal of the third transistor, wherein a slave current terminal of the current mirror is coupled to the output terminal of the comparison circuit And a fourth transistor having a control terminal coupled to the output terminal of the comparison circuit, wherein a first terminal of the fourth transistor is coupled to the system voltage, a second of the fourth transistor The terminal is coupled to the slave current terminal of the current mirror. The source driver according to claim 9, wherein the comparison circuit includes: a third transistor having a control terminal coupled to the input voltage, wherein the first transistor A first terminal of the three transistors is coupled to the first feedback voltage; a fourth transistor has a control terminal controlled by a first control signal, wherein a first terminal of the fourth transistor is coupled To a second end of the third transistor; a current mirror having a main current end coupled to a second end of the fourth transistor, wherein a slave current end of the current mirror is coupled to the comparison circuit The output terminal; a fifth transistor with a control terminal controlled by the first control signal, wherein a first terminal of the fifth transistor is coupled to a reference voltage, the second of the fifth transistor End coupled to the uniform energy end of the current mirror; and a sixth transistor having a control end coupled to the output end of the comparison circuit, wherein a first end of the sixth transistor is coupled to the system Voltage, a second terminal of the sixth transistor is coupled to the slave current terminal of the current mirror. The source driver according to claim 11, wherein the comparison circuit further includes: a seventh transistor having a control terminal controlled by a second control signal, wherein a first control signal of the seventh transistor The terminal is coupled to the system voltage, and a second terminal of the seventh transistor is coupled to the control terminal of the sixth transistor. The source driver according to claim 1, wherein the feedback circuit includes: a feedback switch having a first terminal and a second terminal respectively coupled to the second input terminal of the input stage circuit And the output terminal of the output stage circuit, wherein the feedback switch is turned off during an over-driving period, and the feedback switch is turned on during a normal driving period to transmit the output voltage as the first feedback voltage to the The input stage circuit A second input terminal; and a feedback voltage generating circuit for generating and outputting a second feedback voltage related to the output voltage as the first feedback voltage to the input stage circuit during the overdrive period Second input terminal, and during the normal driving period, the second feedback voltage is not output to the second input terminal of the input stage circuit, wherein when the input voltage is in a rising mode, the second feedback voltage is lower than The output voltage and when the input voltage is in a falling mode, the second feedback voltage is higher than the output voltage. For example, the source driver described in item 13 of the scope of patent application further includes: a digital-to-analog converter coupled to the first input terminal of the input stage circuit for converting a current pixel data into the input voltage, And output the input voltage to the first input terminal of the input stage circuit; wherein "the input voltage is in the rising mode" is defined as "the input voltage corresponding to the current pixel data is greater than that corresponding to a previous pixel data "The input voltage" and "the input voltage is in the falling mode" are defined as "the input voltage corresponding to the current pixel data is less than the input voltage corresponding to the previous pixel data". The source driver according to claim 13, wherein the data line is coupled to a near pixel circuit and a far pixel circuit of the display panel, and the distance from the near pixel circuit to the source driver is smaller than the far pixel circuit The distance to the source driver and the overdrive period related to the near pixel circuit are smaller than the overdrive period related to the far pixel circuit. The source driver according to claim 13, wherein the feedback voltage generating circuit includes: a first switch having a first terminal coupled to the output terminal of the output stage circuit, wherein the first switch Regarding the over-driving period being on, and the first switch being off during the normal driving period; a second switch having a first terminal coupled to the second input terminal of the input stage circuit, wherein the second switch Regarding that the over-driving period is turned on and the second switch is turned off during the normal driving period; a first voltage dividing resistor has a first end coupled to a second end of the first switch, wherein the first A second end of the voltage dividing resistor is coupled to a second end of the second switch; and an impedance circuit is coupled to the second end of the first voltage dividing resistor. The source driver according to claim 16, wherein the impedance circuit includes: a second voltage dividing resistor having a first end coupled to the second end of the first voltage dividing resistor; and a third The switch has a first terminal coupled to a second terminal of the second voltage divider resistor, wherein a second terminal of the third switch is coupled to a reference voltage, the reference voltage is lower than the output voltage, when the The third switch is turned on when the input voltage is in the rising mode, and the third switch is turned off when the input voltage is in the falling mode; and a fourth switch having a first terminal coupled to the second divided voltage The second of resistance Terminal, wherein a second terminal of the fourth switch is coupled to a system voltage, the system voltage is higher than the output voltage, when the input voltage is in the rising mode, the fourth switch is turned off, and when the input voltage is In the falling mode, the fourth switch is turned on. The source driver according to claim 16, wherein the impedance circuit includes: a third switch having a first end coupled to the second end of the first voltage dividing resistor, wherein when the input voltage When in the rising mode, the third switch is turned on, and when the input voltage is in the falling mode, the third switch is turned off; a second voltage divider resistor having a first terminal coupled to a third switch A second terminal, wherein a second terminal of the second voltage divider resistor is coupled to a reference voltage, the reference voltage is lower than the output voltage; a fourth switch having a first terminal coupled to the first voltage divider The second end of the resistor, wherein the fourth switch is off when the input voltage is in the rising mode, and the fourth switch is on when the input voltage is in the falling mode; and a third voltage divider resistor has A first terminal is coupled to a second terminal of the fourth switch, and a second terminal of the third voltage dividing resistor is coupled to a system voltage, the system voltage is higher than the output voltage. The source driver according to claim 16, wherein the impedance circuit includes: a second voltage dividing resistor having a first end coupled to the second end of the first voltage dividing resistor; and a digital bit The analog conversion circuit has an output terminal coupled to the second voltage divider resistor A second terminal of, used to convert a previous pixel data into a previous voltage, and output the previous voltage to the second terminal of the second voltage divider resistor. For the source driver described in claim 19, the digital-to-analog conversion circuit includes: a digital-to-analog converter with an input terminal for receiving the previous pixel data; and a unit gain buffer with an input The terminal is coupled to an output terminal of the digital-to-analog converter, and an output terminal of the unit gain buffer is coupled to the second terminal of the second voltage divider to supply the previous voltage. The source driver according to claim 16, wherein the impedance circuit includes: a third switch having a first end coupled to the second end of the first voltage dividing resistor, wherein when the input voltage When in the rising mode, the third switch is turned on, and when the input voltage is in the falling mode, the third switch is turned off; a second voltage divider resistor having a first terminal coupled to a third switch A second end; a fourth switch having a first end coupled to the second end of the first voltage divider resistor, wherein the fourth switch is turned off when the input voltage is in the rising mode, and when the input The fourth switch is turned on when the voltage is in the falling mode; a third voltage divider resistor has a first end coupled to a second end of the fourth switch; and a digital-to-analog conversion circuit has an output terminal coupled Connect to the second voltage divider resistor A second end of the third voltage divider and a second end of the third voltage divider are used to convert a previous pixel data into a previous voltage, and output the previous voltage to the second end of the second voltage divider and The second end of the third voltage divider resistor. An output buffer includes: an input stage circuit having a first input terminal and a second input terminal, wherein the first input terminal of the input stage circuit is configured to receive an input voltage of the output buffer, The second input terminal of the input stage circuit is configured to receive a first feedback voltage of the output buffer, and the input stage circuit generates a first gate corresponding to the input voltage and the first feedback voltage Control voltage and a second gate control voltage; an output stage circuit coupled to the input stage circuit to receive the first gate control voltage and the second gate control voltage, and is configured to follow the first gate control voltage and The second gating voltage correspondingly generates an output voltage of the output buffer; a rising control circuit is configured to compare the input voltage with the first feedback voltage to obtain a first comparison result, wherein when the first A comparison result indicates that the first feedback voltage is to be raised, that is, when the input voltage is greater than the first feedback voltage, the rise control circuit pulls down the first gate control voltage and the first gate control voltage during a first transient period. Two gate control voltages; and a drop control circuit configured to compare the input voltage with the first feedback voltage to obtain a second comparison result, wherein when the second comparison result indicates that the first feedback voltage is to be Pull down, that is, when the input voltage is less than the first feedback voltage, the down control circuit pulls up the first gating voltage and the second gating voltage during a second transient period. According to the output buffer of claim 22, the output stage circuit includes: a first transistor having a control terminal coupled to the input stage circuit to receive the first gate control voltage, wherein the first gate control voltage A first terminal of a transistor is coupled to a system voltage, a second terminal of the first transistor is coupled to an output terminal of the output stage circuit, and the output terminal of the output stage circuit outputs the output buffer The output voltage of the device; and a second transistor having a control terminal coupled to the input stage circuit to receive the second gating voltage, wherein a first terminal of the second transistor is coupled to a reference voltage , A second end of the second transistor is coupled to the output end of the output stage circuit. The output buffer according to item 22 of the scope of patent application, wherein when the input voltage is greater than the first feedback voltage, the rising control circuit pulls down the first gate control voltage and the second gate control voltage, and when When the input voltage is less than or equal to the first feedback voltage, the rising control circuit does not adjust the first gating voltage and the second gating voltage. The output buffer according to claim 22, wherein the rising control circuit includes: a comparison circuit configured to compare the input voltage with the first feedback voltage to generate a control voltage as the first comparison Result; a first transistor having a control terminal coupled to an output terminal of the comparison circuit to receive the control voltage, wherein a first terminal of the first transistor is coupled to a reference voltage, the first transistor A second end of the crystal is coupled to a first output of the output stage circuit Input terminal to receive the first gate control voltage; and a second transistor having a control terminal coupled to the output terminal of the comparison circuit to receive the control voltage, wherein a first terminal of the second transistor is coupled Connected to the reference voltage, a second terminal of the second transistor is coupled to a second input terminal of the output stage circuit to receive the second gate control voltage. The output buffer according to claim 25, wherein the comparison circuit includes: a third transistor having a control terminal coupled to the input voltage, wherein a first terminal of the third transistor is coupled To the first feedback voltage; a current mirror with a main current terminal coupled to a second terminal of the third transistor, wherein a slave current terminal of the current mirror is coupled to the output terminal of the comparison circuit And a fourth transistor having a control terminal coupled to the output terminal of the comparison circuit, wherein a first terminal of the fourth transistor is coupled to the reference voltage, a second of the fourth transistor The terminal is coupled to the slave current terminal of the current mirror. The output buffer according to claim 25, wherein the comparison circuit includes: a third transistor having a control terminal coupled to the input voltage, wherein a first terminal of the third transistor is coupled To the first feedback voltage; a fourth transistor having a control terminal controlled by a first control signal, wherein a first terminal of the fourth transistor is coupled to a second terminal of the third transistor End; a current mirror with a second main current end coupled to the fourth transistor Terminal, wherein a slave current terminal of the current mirror is coupled to the output terminal of the comparison circuit; a fifth transistor having a control terminal controlled by the first control signal, wherein a first control signal of the fifth transistor One end is coupled to a system voltage, the second end of the fifth transistor is coupled to the uniform energy end of the current mirror; and a sixth transistor has a control end coupled to the output end of the comparison circuit , Wherein a first terminal of the sixth transistor is coupled to the reference voltage, and a second terminal of the sixth transistor is coupled to the slave current terminal of the current mirror. According to the output buffer of claim 27, the comparison circuit further includes: a seventh transistor having a control terminal controlled by a second control signal, wherein a first of the seventh transistor The terminal is coupled to the reference voltage, and a second terminal of the seventh transistor is coupled to the control terminal of the sixth transistor. The output buffer according to item 22 of the scope of patent application, wherein when the input voltage is less than the first feedback voltage, the down control circuit pulls up the first gating voltage and the second gating voltage, and when When the input voltage is greater than or equal to the first feedback voltage, the drop control circuit does not adjust the first gating voltage and the second gating voltage. The output buffer of claim 22, wherein the drop control circuit includes: a comparison circuit configured to compare the input voltage with the first feedback voltage to generate a control voltage as the second comparison Result; a first transistor with a control terminal coupled to an output terminal of the comparison circuit To receive the control voltage, wherein a first terminal of the first transistor is coupled to a system voltage, and a second terminal of the first transistor is coupled to a first input terminal of the output stage circuit to receive the A first gate control voltage; and a second transistor having a control terminal coupled to the output terminal of the comparison circuit to receive the control voltage, wherein a first terminal of the second transistor is coupled to the system voltage A second terminal of the second transistor is coupled to a second input terminal of the output stage circuit to receive the second gating voltage. The output buffer according to claim 30, wherein the comparison circuit includes: a third transistor having a control terminal coupled to the input voltage, wherein a first terminal of the third transistor is coupled To the first feedback voltage; a current mirror with a main current terminal coupled to a second terminal of the third transistor, wherein a slave current terminal of the current mirror is coupled to the output terminal of the comparison circuit And a fourth transistor having a control terminal coupled to the output terminal of the comparison circuit, wherein a first terminal of the fourth transistor is coupled to the system voltage, a second of the fourth transistor The terminal is coupled to the slave current terminal of the current mirror. The output buffer according to claim 30, wherein the comparison circuit includes: a third transistor having a control terminal coupled to the input voltage, wherein a first terminal of the third transistor is coupled To the first feedback voltage; a fourth transistor with a control terminal controlled by a first control signal, wherein A first end of the fourth transistor is coupled to a second end of the third transistor; a current mirror having a main current end coupled to a second end of the fourth transistor, wherein the current A slave current terminal of the mirror is coupled to the output terminal of the comparison circuit; a fifth transistor having a control terminal controlled by the first control signal, wherein a first terminal of the fifth transistor is coupled to A reference voltage, the second end of the fifth transistor is coupled to the uniform energy end of the current mirror; and a sixth transistor having a control end coupled to the output end of the comparison circuit, wherein the sixth transistor A first end of the transistor is coupled to the system voltage, and a second end of the sixth transistor is coupled to the slave current end of the current mirror. According to the output buffer described in claim 32, the comparison circuit further includes: a seventh transistor having a control terminal controlled by a second control signal, wherein a first of the seventh transistor The terminal is coupled to the system voltage, and a second terminal of the seventh transistor is coupled to the control terminal of the sixth transistor.

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