TWI728650B - Semiconductor protection device - Google Patents

Semiconductor protection device Download PDF

Info

Publication number
TWI728650B
TWI728650B TW109101132A TW109101132A TWI728650B TW I728650 B TWI728650 B TW I728650B TW 109101132 A TW109101132 A TW 109101132A TW 109101132 A TW109101132 A TW 109101132A TW I728650 B TWI728650 B TW I728650B
Authority
TW
Taiwan
Prior art keywords
semiconductor
terminal
resistor
source
power supply
Prior art date
Application number
TW109101132A
Other languages
Chinese (zh)
Other versions
TW202042467A (en
Inventor
盧昭正
Original Assignee
盧昭正
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 盧昭正 filed Critical 盧昭正
Publication of TW202042467A publication Critical patent/TW202042467A/en
Application granted granted Critical
Publication of TWI728650B publication Critical patent/TWI728650B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching
    • H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Protection Of Static Devices (AREA)

Abstract

The semiconductor protection device of the invention, comprises a first semiconductor, a second semiconductor, a third semiconductor and a time delay generation, constituting an application circuit with load overload or short-circuit protection function, and is equivalent to the characteristic of a single semiconductor, which avoids the damage caused by overload or short-circuit at both terminals of the load.

Description

半導體保護裝置 Semiconductor protection device

本發明涉及電子技術領域，尤其是涉及一種在直流電路應用過程中負載兩端發生過載或短路時具有保護功能的半導體保護裝置。 The invention relates to the field of electronic technology, and in particular to a semiconductor protection device with a protective function when overload or short-circuit occurs at both ends of a load during the application of a direct current circuit.

如圖1所示，為習知發明電池放電保護裝置，自圖中可知，第二半導體14的集極C連接第一集極電阻15的另一端及第一半導體12的閘極G，第一集極電阻15的一端連接電路正電端V+，第二半導體14的射極E連接第一半導體12的源極S，第二半導體14的基極B連接第一基極電阻16的一端，第一基極電阻16的另一端連接電路負電端V-，圖中的充電裝置100在本發明中不涉及充電原理所以不予贅述；當電池11對負載200執行放電動作中發生過電流時，第一半導體12的汲極D及源極S之間電位急速上升，此時第二半導體14的基極B電位高於射極E而使第二半導體14導通，第一半導體12的閘極G的正電位等於第一半導體12的源極S的正電位，因此第一半導體12開路，此時第一半導體12的汲極電流斷電流，以保護電池11因發生過電流而造成電池11 的損壞，若欲解除第二半導體14的導通狀態只需將負載200解除，即可解除第二半導體14的導通狀態，而恢復第一半導體12的正常狀態，其缺點如下： As shown in Figure 1, it is a conventional invention battery discharge protection device. It can be seen from the figure that the collector C of the second semiconductor 14 is connected to the other end of the first collector resistor 15 and the gate G of the first semiconductor 12. One end of the collector resistor 15 is connected to the positive terminal V+ of the circuit, the emitter E of the second semiconductor 14 is connected to the source S of the first semiconductor 12, and the base B of the second semiconductor 14 is connected to one end of the first base resistor 16. The other end of a base resistor 16 is connected to the negative terminal V- of the circuit. The charging device 100 in the figure does not involve the charging principle in the present invention, so it will not be repeated; when the battery 11 discharges the load 200 when an overcurrent occurs, the first The potential between the drain D and the source S of a semiconductor 12 rises rapidly. At this time, the potential of the base B of the second semiconductor 14 is higher than the emitter E, so that the second semiconductor 14 is turned on, and the gate G of the first semiconductor 12 The positive potential is equal to the positive potential of the source S of the first semiconductor 12, so the first semiconductor 12 is open. At this time, the drain current of the first semiconductor 12 is cut off to protect the battery 11 from overcurrent. If you want to release the conduction state of the second semiconductor 14, you only need to release the load 200 to release the conduction state of the second semiconductor 14 and restore the normal state of the first semiconductor 12. The disadvantages are as follows:

1.將負載200兩端造成短路的原因解除後，要設一個開關將負載200開路(Off)，再將所設的開關導通(On)，電池11才能再供電於負載200，因此造成增加裝置成本及應用上的不便。 1. After removing the cause of the short circuit between the two ends of the load 200, a switch should be set to open the load 200 (Off), and then the set switch can be turned on (On), so that the battery 11 can supply power to the load 200 again, thus increasing the device Cost and application inconvenience.

2.若要恢復正常的電路功能，必需將負載100兩端造成短路原因解除後，將電池11開路，再重新將電池11送電，也要增加一個開關，造成增加裝置成本及應用上的不便。 2. To restore normal circuit functions, it is necessary to remove the cause of the short circuit caused by the load 100, open the battery 11, and then retransmit the battery 11. A switch must be added, which will increase the cost of the device and cause application inconvenience.

本發明的目的：本發明應用第一半導體、第二半導體、第三半導體及延時產生器，達到等同單一半導體功能的三電極特徵，而且能在直流電源電路供電中發生負載短路時第一直流電源得到保護。 The purpose of the present invention: the present invention uses the first semiconductor, the second semiconductor, the third semiconductor and the delay generator to achieve the three-electrode characteristics equivalent to the function of a single semiconductor, and it can be the first direct current when the load is short-circuited in the direct current power supply circuit. The power supply is protected.

當負載發生短路時，本發明應用第二半導體能在極短之時間內執行第一半導體開路動作，達到保護直流電源電路之功能及避免因負載短路而引起之各種災害。 When the load is short-circuited, the application of the second semiconductor in the present invention can perform the open-circuit action of the first semiconductor in a very short time, achieving the function of protecting the DC power circuit and avoiding various disasters caused by the short-circuit of the load.

本發明應用第三半導體及延時產生器，執行本發明在開機時，執行第二半導體延時動作及重置(Reset)時間控制之功能，達到短路原因排除時不必重新再送直流電源的動作。 The present invention uses the third semiconductor and the delay generator to perform the functions of the second semiconductor delay action and reset time control when the present invention is turned on, so as to achieve the action of re-sending the DC power when the cause of the short circuit is eliminated.

本發明有下列之特徵： The present invention has the following characteristics:

1.本發明之第一半導體其負責直流電源之開路與導通供電於負載。 1. The first semiconductor of the present invention is responsible for the open circuit and conduction of the DC power supply to supply power to the load.

2.本發明之第二半導體，其負責控制第一半導體之開路與導通動作，以達到負載兩端發生短路時保護直流電源電路的目的。 2. The second semiconductor of the present invention is responsible for controlling the opening and conducting actions of the first semiconductor to achieve the purpose of protecting the DC power supply circuit when a short-circuit occurs at both ends of the load.

3.本發明之第三半導體，其負責控制第二半導體之開路與導通動作，以達到負載兩端發生短路時保護直流電源電路的目的。 3. The third semiconductor of the present invention is responsible for controlling the opening and conducting actions of the second semiconductor to achieve the purpose of protecting the DC power supply circuit when a short-circuit occurs at both ends of the load.

4.本發明之延時產生器，負責控制之第三半導體之開路與導通動作時間，以達到控制第一半導體順利執行開路與導通動作之時間。 4. The delay generator of the present invention is responsible for controlling the open circuit and conduction time of the third semiconductor, so as to control the time for the first semiconductor to perform the open circuit and conduction smoothly.

5.本發明之第一半導體包括N通道金屬氧化半導體場效電晶體(N Channel Metal Oxide Semiconductor Field Effect Transistor,N Channel MOSFET)或絕緣閘極雙極電晶體(Insulated Gate Bipolar Transistor,IGBT)二者可以根據需求自行選用。 5. The first semiconductor of the present invention includes both N Channel Metal Oxide Semiconductor Field Effect Transistor (N Channel MOSFET) or Insulated Gate Bipolar Transistor (IGBT) You can choose it according to your needs.

6.本發明之第二半導體包括N型電晶體或N通道金屬氧化半導體場效電晶體二者可以根據需求自行選用。 6. The second semiconductor of the present invention includes N-type transistors or N-channel metal oxide semiconductor field effect transistors, which can be selected according to requirements.

7.本發明之第三半導體包括N型電晶體或N通道金屬氧化半導體場效電晶體二者可以根據需求自行選用。 7. The third semiconductor of the present invention includes N-type transistors or N-channel metal oxide semiconductor field effect transistors, which can be selected according to requirements.

8.本發明之延時產生器為一單時間(Single Timer)積體電路或其他同等功能的延時控制積體電路。 8. The delay generator of the present invention is a single timer (Single Timer) integrated circuit or other equivalent delay control integrated circuit.

9.本發明可以選用第一電阻器、第二電阻器、第三電阻器、第一半導體、第二半導體、第三半導體及延時產生器組成具有三端特徵的半導體單體以方便應用。 9. In the present invention, the first resistor, the second resistor, the third resistor, the first semiconductor, the second semiconductor, the third semiconductor and the delay generator can be selected to form a semiconductor monomer with three-terminal characteristics to facilitate application.

10‧‧‧延時產生器 10‧‧‧Delay generator

11‧‧‧第一半導體 11‧‧‧First Semiconductor

12‧‧‧第二半導體 12‧‧‧Second Semiconductor

13‧‧‧第三半導體 13‧‧‧The Third Semiconductor

14‧‧‧第一半導體 14‧‧‧First Semiconductor

15‧‧‧第二半導體 15‧‧‧Second Semiconductor

16‧‧‧第三半導體 16‧‧‧The Third Semiconductor

21‧‧‧第一電阻器 21‧‧‧First resistor

22‧‧‧第二電阻器 22‧‧‧Second resistor

23‧‧‧第三電阻器 23‧‧‧Third resistor

30‧‧‧第一端 30‧‧‧First end

40‧‧‧第二端 40‧‧‧Second end

50‧‧‧第三端 50‧‧‧Third end

60‧‧‧第一開關 60‧‧‧First switch

70‧‧‧第二開關 70‧‧‧Second switch

100‧‧‧負載 100‧‧‧Load

200‧‧‧第一直流電源 200‧‧‧The first DC power supply

300‧‧‧第二直流電源 300‧‧‧Second DC power supply

圖1為習知電池放電保護裝置之實施例。 Fig. 1 is an embodiment of a conventional battery discharge protection device.

圖2為本發明半導體保護裝置第一實施例。 FIG. 2 shows the first embodiment of the semiconductor protection device of the present invention.

圖3為本發明半導體保護裝置第二實施例。 FIG. 3 is a second embodiment of the semiconductor protection device of the present invention.

如圖2所示，為本發明半導體保護裝置第一實施例，自圖中可知，其包括延時產生器10、第一半導體11、第二半導體12、第三半導體13、第一電阻器21(First Resistor,21)、第二電阻器22(Second Resistor,22)及第三電阻器23(Third Resistor,23)，其第一端30(FirstTermina,30)、第二端40(SecondTerminal,40)及第三端50(Third Terminal.50)為對外連接端，其三端在外連接有第一開關60(First Switch,60)、第二開關、負載100(Load,100)、第一直流電源200(First DC Power Source,200)及第二直流電源300(Second DC Power Source,300)。 As shown in FIG. 2, it is the first embodiment of the semiconductor protection device of the present invention. As can be seen from the figure, it includes a delay generator 10, a first semiconductor 11, a second semiconductor 12, a third semiconductor 13, and a first resistor 21 ( First Resistor, 21), second resistor 22 (Second Resistor, 22) and third resistor 23 (Third Resistor, 23), the first terminal 30 (FirstTermina, 30), the second terminal 40 (SecondTerminal, 40) And the third terminal 50 (Third Terminal. 50) is the external connection terminal, and its three terminals are externally connected with the first switch 60 (First Switch, 60), the second switch, the load 100 (Load, 100), and the first DC power supply. 200 (First DC Power Source, 200) and second DC Power Source 300 (Second DC Power Source, 300).

如圖2所示，第一半導體11的閘極G(Gate,G)連接第二半導體12的集極C(Collector,C)及第一電阻器21的一端，第一電阻器21的另一端連接延時產生器的正電壓端VD而構成第一端30。 As shown in FIG. 2, the gate G (Gate, G) of the first semiconductor 11 is connected to the collector C (Collector, C) of the second semiconductor 12 and one end of the first resistor 21, and the other end of the first resistor 21 The positive voltage terminal VD of the delay generator is connected to form the first terminal 30.

如圖2所示，第二半導體12的基極B(Base,B)連接第三半導體13的集極C及第二電阻器22的另一端，第二電阻器22的一端連接第一半導體11的汲極D而成為第二端40。 As shown in FIG. 2, the base B (Base, B) of the second semiconductor 12 is connected to the collector C of the third semiconductor 13 and the other end of the second resistor 22, and one end of the second resistor 22 is connected to the first semiconductor 11 The drain D becomes the second terminal 40.

如圖2所示，第一半導體11的源極S(Source,S)連接第二半導體12的射極E(Emitter,E)、第三半導體13的射極E及延時產生器10的接地端VG而成為第三端50。 As shown in FIG. 2, the source S (Source, S) of the first semiconductor 11 is connected to the emitter E (Emitter, E) of the second semiconductor 12, the emitter E of the third semiconductor 13 and the ground terminal of the delay generator 10 VG becomes the third terminal 50.

如圖2所示，第三電阻器23的一端連接第三半 導體13的基極B，第三電阻器23的另一端連接延時產生器10的電壓輸出端VO，延時產生器10的正電壓端VD連接第一端30。 As shown in Figure 2, one end of the third resistor 23 is connected to the third half The base B of the conductor 13 and the other end of the third resistor 23 are connected to the voltage output terminal VO of the delay generator 10, and the positive voltage terminal VD of the delay generator 10 is connected to the first terminal 30.

如圖2所示，負載100的另一端連接第二端40，負載100的一端連接第一開關60另一端，第一開關60的一端連接第一直流電源200的正電端，第一直流電源200的負電端連接第三端50。 As shown in Figure 2, the other end of the load 100 is connected to the second end 40, one end of the load 100 is connected to the other end of the first switch 60, and one end of the first switch 60 is connected to the positive terminal of the first DC power supply 200. The negative terminal of the current source 200 is connected to the third terminal 50.

如圖2所示，第二開關70的另一端連接第一端30，第二開關70的一端連接第二直流電源300的正電端，第二直流電源300的負電端連接第三端50。 As shown in FIG. 2, the other end of the second switch 70 is connected to the first terminal 30, one end of the second switch 70 is connected to the positive terminal of the second DC power supply 300, and the negative terminal of the second DC power supply 300 is connected to the third terminal 50.

如圖2所示，延時產生器10為一單時間積體電路或其他延時控制積體電路，第一半導體11為N通道金屬氧化半導體場效電晶體，第二半導體12為N型電晶體，第三半導體13為N型電晶體。 As shown in FIG. 2, the delay generator 10 is a single-time integrated circuit or other delay-controlled integrated circuit. The first semiconductor 11 is an N-channel metal oxide semiconductor field effect transistor, and the second semiconductor 12 is an N-type transistor. The third semiconductor 13 is an N-type transistor.

如圖2所示，當第一開關60的轉向導通，此時第一直流電源200的正電端供電於負載100到第二端40，而第一直流電源200的負電端連接第三端50。 As shown in Figure 2, when the first switch 60 is turned on, the positive terminal of the first DC power supply 200 supplies power to the load 100 to the second terminal 40, and the negative terminal of the first DC power supply 200 is connected to the third terminal.端50.

如圖2所示，當第一開關60的轉向導通，同時第二開關70轉向導通，此時第二直流電源300的正電端供電於第一端30，從第一端30供電於第一電阻器21到第一半導體11的閘極G及第二半導體12的集極C，因為第二直流電源300的正電端亦供電於延時產生器10的正電端VD，此時延時產生器10的正電輸出端VO輸出一延時正電壓供電於第三電阻器23到第三半導體13的基極B，此時第三半導體13的集極C與射極E導通，因此第二半導體12的集極C與射極E開路，此時第一半導體11的汲極D與源極S導通，第一直流電源200供電於負載100，其延時產生器10的延時正電壓供電時間的長 短，隨負載100的需求及第一半導體11導通時間而定，而不予自限。 As shown in FIG. 2, when the first switch 60 is turned on and the second switch 70 is turned on, the positive terminal of the second DC power supply 300 is supplied to the first terminal 30, and the power is supplied from the first terminal 30 to the first terminal 30. The resistor 21 is connected to the gate G of the first semiconductor 11 and the collector C of the second semiconductor 12, because the positive terminal of the second DC power supply 300 also supplies power to the positive terminal VD of the delay generator 10, at this time the delay generator The positive output terminal VO of 10 outputs a delayed positive voltage to supply power from the third resistor 23 to the base B of the third semiconductor 13. At this time, the collector C and the emitter E of the third semiconductor 13 are turned on, so the second semiconductor 12 The collector C and the emitter E of the first semiconductor 11 are open-circuited. At this time, the drain D and the source S of the first semiconductor 11 are turned on, and the first DC power supply 200 supplies power to the load 100. The delayed positive voltage supply time of the delay generator 10 is longer Short, it depends on the demand of the load 100 and the conduction time of the first semiconductor 11, and is not self-limiting.

如圖2所示，其延時產生器10的延時正電壓的供電時間是等到第一半導體11的汲極D與源極S導通後，其延時產生器10的延時正電壓的供電即為停止，此時第三半導體13的集極C與射極E開路，因此第二半導體12的集極C與射極E開路，第一半導體11的汲極D與源極S導通，第一直流電源200供電於負載100。 As shown in FIG. 2, the power supply time of the delayed positive voltage of the delay generator 10 is after the drain D and the source S of the first semiconductor 11 are turned on, the power supply of the delayed positive voltage of the delay generator 10 is stopped. At this time, the collector C and the emitter E of the third semiconductor 13 are open, so the collector C and the emitter E of the second semiconductor 12 are open, the drain D and the source S of the first semiconductor 11 are turned on, and the first DC power supply 200 supplies power to the load 100.

如圖2所示，當第一端30接有第二直流電源300，第二端40接有第一直流電源200時，第一直流電源200供電於負載100兩端，若將負載100兩端短路，其等同將第一直流電源200直接加於第一半導體11的汲極D與源極S兩端，此時第一半導體11的汲極D與二源極S兩端電壓降上升，第二半導體12的基極B與射極E達到導通電壓時，第二半導體12的集極C與射極E導通，第一半導體11的閘極G與源極S兩端電壓低，於是第一半導體11的汲極D與源極S開路，第一直流電源200不供電於負載100，而達到短路保護第一直流電源200的目的。 As shown in FIG. 2, when the second DC power supply 300 is connected to the first end 30 and the first DC power supply 200 is connected to the second end 40, the first DC power supply 200 supplies power to both ends of the load 100. The two ends are short-circuited, which is equivalent to directly applying the first DC power source 200 to both ends of the drain D and the source S of the first semiconductor 11. At this time, the voltage drop across the drain D and the second source S of the first semiconductor 11 Rising, when the base B and the emitter E of the second semiconductor 12 reach the turn-on voltage, the collector C and the emitter E of the second semiconductor 12 are turned on, and the voltage across the gate G and the source S of the first semiconductor 11 is low. Therefore, the drain D and the source S of the first semiconductor 11 are open, and the first DC power supply 200 does not supply power to the load 100, so that the short-circuit protection of the first DC power supply 200 is achieved.

由上述可知，當第一端30接有第二直流電源300，第二端40接有第一直流電源200時，第一直流電源200供電於負載100兩端，當負載100兩端發生短路，其第一直流電源200受到保護，若將負載100兩端短路的原因去除，將第二開關70轉向開路，再轉向導通，此時延時產生器10的正電壓輸出端VO輸出一延時正電壓使第三半導體13的集極C與射極E導通，第二半導體12的基極B與射極E 兩端電壓低，第二半導體12的集極C與射極E開路，於是第一半導體11的汲極D與源極S導通，亦就是第一直流電源200重新供電於負載100，若將第二開關70轉向開路，第一電阻器21不供電於第一半導體11的閘極G，第一半導體11的汲極D與源極S開路，亦就是第一直流電源200不供電於負載100，而第一端30能達成具有第一半導體11的汲極D與源極S導通與開路的功能。 It can be seen from the above that when the first terminal 30 is connected to the second DC power source 300 and the second terminal 40 is connected to the first DC power source 200, the first DC power source 200 supplies power to both ends of the load 100. Short-circuit, the first DC power supply 200 is protected. If the cause of the short-circuit at both ends of the load 100 is removed, the second switch 70 is turned to open, and then turned on. At this time, the positive voltage output terminal VO of the delay generator 10 outputs a delay The positive voltage turns on the collector C and the emitter E of the third semiconductor 13 and the base B and the emitter E of the second semiconductor 12 The voltage at both ends is low, the collector C and the emitter E of the second semiconductor 12 are open, so the drain D and the source S of the first semiconductor 11 are turned on, that is, the first DC power supply 200 is re-powered to the load 100. The second switch 70 turns to open, the first resistor 21 does not supply power to the gate G of the first semiconductor 11, and the drain D and source S of the first semiconductor 11 are open, that is, the first DC power supply 200 does not supply power to the load. 100, and the first terminal 30 can achieve the function of conducting and opening the drain D and the source S of the first semiconductor 11.

如圖2所示，當第一端30接有第二直流電源300，第二端40接有第一直流電源200時，第一直流電源200供電於負載100兩端，若將負載100加大亦就是增大負載100的電流量，此時第一半導體11的汲極D與源極S之電壓降值大於第二半導體12的基射極導通電壓時，第二半導體12的集極C與射極E導通，第一半導體11的閘極G與源極S兩端電壓低，於是第一半導體11的汲極D與源極S開路，第一直流電源200不供電於負載100，而達到過電流保護第一直流電源200的目的。 As shown in FIG. 2, when the second DC power supply 300 is connected to the first end 30 and the first DC power supply 200 is connected to the second end 40, the first DC power supply 200 supplies power to both ends of the load 100. Increasing means increasing the amount of current of the load 100. At this time, when the voltage drop between the drain D and the source S of the first semiconductor 11 is greater than the base-emitter turn-on voltage of the second semiconductor 12, the collector of the second semiconductor 12 C and emitter E are turned on, the voltage across the gate G and source S of the first semiconductor 11 is low, so the drain D and source S of the first semiconductor 11 are open, and the first DC power supply 200 does not supply power to the load 100 , And achieve the purpose of protecting the first DC power supply 200 from overcurrent.

由上述可知，當第二開關70轉向導通與開路來回切換時，就如同第一端30接上正電壓脈波與零電壓，因此第一端30如同半導體的閘極或基極，而第二端40連接負載100如同半導體的汲極或集極，第三端50連接第一直流電源200與第二直流電源300的負電端如同半導體的源極或射極。 It can be seen from the above that when the second switch 70 is turned on and switched back and forth, it is as if the first terminal 30 is connected with a positive voltage pulse and zero voltage. Therefore, the first terminal 30 is like the gate or base of a semiconductor, and the second terminal 30 is like the gate or base of a semiconductor. The terminal 40 is connected to the load 100 as the drain or collector of a semiconductor, and the third terminal 50 is connected to the negative terminals of the first DC power source 200 and the second DC power source 300 as the source or emitter of the semiconductor.

如圖3所示，為本發明半導體保護裝置第二實施例，自圖中可知，其包括延時產生器10、第一半導體14、第二半導體15、第三半導體16、第一電阻器21、第二電阻器22及第三電阻器23，其第一端30、第二端40及第三端50為對外連接端，其三端對 外連接有第一開關60、第二開關70、負載100、第一直流電源200及第二直流電源300。 As shown in FIG. 3, it is the second embodiment of the semiconductor protection device of the present invention. As can be seen from the figure, it includes a delay generator 10, a first semiconductor 14, a second semiconductor 15, a third semiconductor 16, a first resistor 21, The first end 30, the second end 40 and the third end 50 of the second resistor 22 and the third resistor 23 are external connection ends, and the three ends are The first switch 60, the second switch 70, the load 100, the first DC power supply 200, and the second DC power supply 300 are externally connected.

如圖3所示，第一半導體14的閘極G連接第二半導體15的汲極D及第一電阻器21的一端，第一電阻器21的另一端連接延時產生器10的正電端VD而構成第一端30。 As shown in FIG. 3, the gate G of the first semiconductor 14 is connected to the drain D of the second semiconductor 15 and one end of the first resistor 21, and the other end of the first resistor 21 is connected to the positive terminal VD of the delay generator 10 And constitute the first end 30.

如圖3所示，第二半導體15的閘極G連接第三半導體16的汲極D及第二電阻器22的另一端，第二電阻器22的一端連接第一半導體14的集極C而成為第二端40。 As shown in FIG. 3, the gate G of the second semiconductor 15 is connected to the drain D of the third semiconductor 16 and the other end of the second resistor 22, and one end of the second resistor 22 is connected to the collector C of the first semiconductor 14. Become the second end 40.

如圖3所示，第一半導體14的射極E連接第二半導體15的源極S、第三半導體16的源極S及延時產生器10的接地端VG而成為第三端50。 As shown in FIG. 3, the emitter E of the first semiconductor 14 is connected to the source S of the second semiconductor 15, the source S of the third semiconductor 16 and the ground terminal VG of the delay generator 10 to become the third terminal 50.

如圖3所示，第三電阻器23的一端連接第三半導體16的閘極G，第三電阻器23的另一端連接延時產生器10的正電壓輸出端VO，而其延時產生器10的正電壓端VD連接第一端30。 As shown in FIG. 3, one end of the third resistor 23 is connected to the gate G of the third semiconductor 16, the other end of the third resistor 23 is connected to the positive voltage output terminal VO of the delay generator 10, and the delay generator 10 The positive voltage terminal VD is connected to the first terminal 30.

如圖3所示，負載100的另一端連接第二端40，負載100的一端連接第一開關60另一端，第一開關60的一端連接第一直流電源200的正電端，第一直流電源200的負電端連接第三端50。 As shown in FIG. 3, the other end of the load 100 is connected to the second end 40, one end of the load 100 is connected to the other end of the first switch 60, and one end of the first switch 60 is connected to the positive terminal of the first DC power supply 200. The negative terminal of the current source 200 is connected to the third terminal 50.

如圖3所示，第二開關70的另一端連接第一端30，第二開關70的一端連接第二直流電源300的正電端，第二直流電源300的負電端連接第三端50。 As shown in FIG. 3, the other end of the second switch 70 is connected to the first terminal 30, one end of the second switch 70 is connected to the positive terminal of the second DC power supply 300, and the negative terminal of the second DC power supply 300 is connected to the third terminal 50.

如圖3所示，延時產生器10為一單時間積體電路或其他延時控制積體電路，第一半導體14為絕緣閘極雙極電晶體，第二半導體15為N通道金屬氧化半導體場效電晶體，第三半導體16為N通道金屬氧化半導體場效電晶體。 As shown in FIG. 3, the delay generator 10 is a single-time integrated circuit or other delay-controlled integrated circuit. The first semiconductor 14 is an insulated gate bipolar transistor, and the second semiconductor 15 is an N-channel metal oxide semiconductor field effect. Transistor, the third semiconductor 16 is an N-channel metal oxide semiconductor field effect transistor.

如圖3所示，當第一開關60的轉向導通，此時第一直流電源200的正電端供電於負載100到第二端40，而第一直流電源200的負電端連接第三端50。 As shown in FIG. 3, when the first switch 60 is turned on, the positive terminal of the first DC power supply 200 supplies power to the load 100 to the second terminal 40, and the negative terminal of the first DC power supply 200 is connected to the third terminal.端50.

如圖3所示，當第一開關60的轉向導通，同時第二開關70轉向導通，此時第二直流電源300的正電端供電於第一端30，從第一端30供電於第一電阻器21到第一半導體14的閘極G及第二半導體15的汲極D，因為第二直流電源300的正電端亦供電於延時產生器10的正電端VD，此時延時產生器10的正電輸出端VO輸出一延時正電壓供電於第三電阻器23到第三半導體16的閘極G，此時第三半導體16的汲極D與源極S導通，因此第二半導體15的汲極D與源極S開路，此時第一半導體14的集極C與射極E導通，第一直流電源200供電於負載100，其延時產生器10的延時正電壓的供電時間的長短控制，隨負載100的需求及第一半導體14導通時間而定，而不予自限。 As shown in FIG. 3, when the first switch 60 is turned on and the second switch 70 is turned on, the positive terminal of the second DC power supply 300 is supplied to the first terminal 30, and the power is supplied from the first terminal 30 to the first terminal 30. The resistor 21 is connected to the gate G of the first semiconductor 14 and the drain D of the second semiconductor 15, because the positive terminal of the second DC power supply 300 also supplies power to the positive terminal VD of the delay generator 10, at this time the delay generator The positive output terminal VO of 10 outputs a delayed positive voltage to supply power from the third resistor 23 to the gate G of the third semiconductor 16. At this time, the drain D and the source S of the third semiconductor 16 are turned on, so the second semiconductor 15 The drain D and the source S of the open circuit, the collector C and the emitter E of the first semiconductor 14 are turned on, the first DC power supply 200 supplies power to the load 100, which delays the power supply time of the delayed positive voltage of the generator 10 The length control depends on the demand of the load 100 and the conduction time of the first semiconductor 14 and is not self-limiting.

如圖3所示，其延時產生器10的延時正電壓的供電時間是等到第一半導體14的集極C與射極E導通後，其延時產生器10的延時正電壓的供電即為停止，此時第三半導體16的汲極D與源極S開路，因此第二半導體15的汲極D與源極S開路，第一半導體14的集極C與射極E導通，第一直流電源200供電於負載100。 As shown in FIG. 3, the power supply time of the delay positive voltage of the delay generator 10 is after the collector C and the emitter E of the first semiconductor 14 are turned on, the power supply of the delay positive voltage of the delay generator 10 is stopped. At this time, the drain D and the source S of the third semiconductor 16 are open, so the drain D and the source S of the second semiconductor 15 are open, the collector C and the emitter E of the first semiconductor 14 are turned on, and the first DC power supply 200 supplies power to the load 100.

如圖3所示，當第一端30接有第二直流電源300，第二端40接有第一直流電源200時，第一直流電源200供電於負載100兩端，若將負載100兩端短路，其等同將第一直流電源200直接加於第一半導體14的集極C與射極E兩端，此時第一半導體11 的集極C與射極E兩端電壓降上升，當第二半導體15的閘極G與源極S達到導通電壓時，第二半導體15的汲極D與源極S導通，第一半導體14的閘極G與射極E兩端電壓低，於是第一半導體14的集極C與射極E開路，第一直流電源200不供電於負載100，而達到短路保護第一直流電源200的目的。 As shown in FIG. 3, when the second DC power supply 300 is connected to the first end 30 and the first DC power supply 200 is connected to the second end 40, the first DC power supply 200 supplies power to both ends of the load 100. The two ends are short-circuited, which is equivalent to directly applying the first DC power source 200 to both ends of the collector C and the emitter E of the first semiconductor 14. At this time, the first semiconductor 11 The voltage drop across the collector C and the emitter E rises. When the gate G and the source S of the second semiconductor 15 reach the turn-on voltage, the drain D and the source S of the second semiconductor 15 are turned on, and the first semiconductor 14 The voltage across the gate G and the emitter E is low, so the collector C and the emitter E of the first semiconductor 14 are open, the first DC power supply 200 does not supply power to the load 100, and the short circuit protection of the first DC power supply 200 is achieved. the goal of.

由上述可知，當第一端30接有第二直流電源300，第二端40接有第一直流電源200時，第一直流電源200供電於負載100兩端，當負載100兩端發生短路，其第一直流電源200受到保護，若將負載100兩端短路的原因去除，將第二開關70轉向開路，再轉向導通，此時延時產生器10的正電壓輸出端VO輸出一延時正電壓使第三半導體16的汲極D與源極S導通，第二半導體15的閘極G與源極S兩端電壓低，第二半導體15的汲極D與源極S開路，於是第一半導體14的集極C與射極E導通，亦就是第一直流電源200重新供電於負載100，若將第二開關70轉向開路，第一半導體14的集極C與射極E開路，亦就是第一直流電源200不供電於負載100，而第一端30能達成具有第一半導體14的集極C與射極E導通與開路的功能。 It can be seen from the above that when the first terminal 30 is connected to the second DC power source 300 and the second terminal 40 is connected to the first DC power source 200, the first DC power source 200 supplies power to both ends of the load 100. Short-circuit, the first DC power supply 200 is protected. If the cause of the short-circuit at both ends of the load 100 is removed, the second switch 70 is turned to open, and then turned on. At this time, the positive voltage output terminal VO of the delay generator 10 outputs a delay The positive voltage causes the drain D and the source S of the third semiconductor 16 to be turned on. The voltage across the gate G and the source S of the second semiconductor 15 is low, and the drain D and the source S of the second semiconductor 15 are open. The collector C and the emitter E of a semiconductor 14 are turned on, that is, the first DC power supply 200 is re-powered to the load 100. If the second switch 70 is turned to open, the collector C and the emitter E of the first semiconductor 14 are open. That is, the first DC power source 200 does not supply power to the load 100, and the first terminal 30 can achieve the function of conducting and opening the collector C and the emitter E of the first semiconductor 14.

如圖3所示，當第一端30接有第二直流電源300，第二端40接有第一直流電源200時，第一直流電源200供電於負載100兩端，若將負載100加大亦就是增大負載100的電流量，此時若第一半導體14的集極C與射極E之電壓降值大於第二半導體15的閘源極導通電壓時，第二半導體15的汲極D與源極S導通，第一半導體14的閘極G與射極E兩 端電壓低，於是第一半導體14的集極C與射極E開路，第一直流電源200不供電於負載100，而達到過電流保護第一直流電源200的目的。 As shown in FIG. 3, when the second DC power supply 300 is connected to the first end 30 and the first DC power supply 200 is connected to the second end 40, the first DC power supply 200 supplies power to both ends of the load 100. Increasing means increasing the current of the load 100. At this time, if the voltage drop between the collector C and the emitter E of the first semiconductor 14 is greater than the gate-source turn-on voltage of the second semiconductor 15, the drain of the second semiconductor 15 The electrode D is connected to the source electrode S, and the gate electrode G and the emitter electrode E of the first semiconductor 14 are two The terminal voltage is low, so the collector C and the emitter E of the first semiconductor 14 are open, and the first DC power source 200 does not supply power to the load 100, and the purpose of protecting the first DC power source 200 from overcurrent is achieved.

由上述可知，當第二開關70轉向導通與開路來回切換時，就如同第一端30接上正電壓脈波與零電壓斷續，因此第一端30如同半導體的閘極或基極，而第二端40連接負載100如同半導體的汲極或集極，第三端50連接第一直流電源200與第二直流電源300的負電端如同半導體的源極或射極。 It can be seen from the above that when the second switch 70 is turned on and switched back and forth, it is as if the first terminal 30 is connected with a positive voltage pulse and the zero voltage is interrupted. Therefore, the first terminal 30 is like the gate or base of a semiconductor, and The second terminal 40 is connected to the load 100 as the drain or collector of a semiconductor, and the third terminal 50 is connected to the negative terminals of the first DC power source 200 and the second DC power source 300 as the source or emitter of the semiconductor.

由上述可知，圖2與圖3之動作原理與功能皆為相同，如圖2之第一半導體11為N通道金屬氧化半導體場效電晶體，圖3之第一半導體14為絕緣閘極雙極電晶體，兩者之差異僅在應用於不同之負載100，如N通道金屬氧化半導體場效電晶體之應用特性為低電壓高電流，適用於低電壓高電流之負載100，而絕緣閘極雙極電晶體之應用特性為高電壓高電流，適用於高電壓高電流之負載100，由此可知其隨負載100之需求選用，因此其第一半導體11與第一半導體14是可互相替代，而不予自限。 It can be seen from the above that the operating principles and functions of FIGS. 2 and 3 are the same. The first semiconductor 11 in FIG. 2 is an N-channel metal oxide semiconductor field effect transistor, and the first semiconductor 14 in FIG. 3 is an insulated gate bipolar transistor. Transistor, the difference between the two is only applied to different loads 100. For example, the application characteristics of N-channel metal oxide semiconductor field effect transistors are low voltage and high current, which is suitable for low voltage and high current loads. The application characteristic of the polar transistor is high voltage and high current, suitable for the load 100 of high voltage and high current. It can be known that it can be selected according to the demand of the load 100. Therefore, the first semiconductor 11 and the first semiconductor 14 can be replaced with each other. No self-limitation.

由上述可知，圖2與圖3之動作原理與功能皆為相同，如圖2之第二半導體12為N型電晶體，圖3之第二半導體15為N通道金屬氧化半導體場效電晶體，可知其隨負載100之需求選用，因此其第二半導體12與第二半導體15是可互相替代，而不予自限。 It can be seen from the above that the operating principles and functions of FIGS. 2 and 3 are the same. The second semiconductor 12 in FIG. 2 is an N-type transistor, and the second semiconductor 15 in FIG. 3 is an N-channel metal oxide semiconductor field effect transistor. It can be seen that it can be selected according to the demand of the load 100, so the second semiconductor 12 and the second semiconductor 15 can be replaced with each other, and are not self-limiting.

由上述可知，圖2與圖3之動作原理與功能皆為相同，如圖2之第三半導體13為N型電晶體，圖3之第三半導體16為N通道金屬氧化半導體場效電晶體，可知其隨第三半導體13、第三半導體16及 時延產生器10之需求選用，因此其第三半導體13與第三半導體16是可互相替代，而不予自限。 It can be seen from the above that the operating principles and functions of FIGS. 2 and 3 are the same. The third semiconductor 13 in FIG. 2 is an N-type transistor, and the third semiconductor 16 in FIG. 3 is an N-channel metal oxide semiconductor field effect transistor. It can be seen that it follows the third semiconductor 13, the third semiconductor 16 and The time delay generator 10 needs to be selected, so the third semiconductor 13 and the third semiconductor 16 can be replaced with each other without self-limiting.

以上所述實施例僅是為充分說明本發明所舉的較佳的實施例，本發明的保護範圍不限於此，包括本技術領域的技術人員，在本發明基礎上所作的等同替代或變換，皆在本發明的保護範圍內。本發明的保護範圍以申請專利範圍書為准。 The above-mentioned embodiments are only preferred embodiments for fully explaining the present invention. The protection scope of the present invention is not limited to this, including equivalent substitutions or transformations made by those skilled in the art on the basis of the present invention. All are within the protection scope of the present invention. The scope of protection of the present invention is subject to the scope of the patent application.

10‧‧‧延時產生器 10‧‧‧Delay generator

11‧‧‧第一半導體 11‧‧‧First Semiconductor

12‧‧‧第二半導體 12‧‧‧Second Semiconductor

13‧‧‧第三半導體 13‧‧‧The Third Semiconductor

21‧‧‧第一電阻器 21‧‧‧First resistor

22‧‧‧第二電阻器 22‧‧‧Second resistor

23‧‧‧第三電阻器 23‧‧‧Third resistor

30‧‧‧第一端 30‧‧‧First end

40‧‧‧第二端 40‧‧‧Second end

50‧‧‧第三端 50‧‧‧Third end

60‧‧‧第一開關 60‧‧‧First switch

70‧‧‧第二開關 70‧‧‧Second switch

100‧‧‧負載 100‧‧‧Load

200‧‧‧第一直流電源 200‧‧‧The first DC power supply

300‧‧‧第二直流電源 300‧‧‧Second DC power supply

Claims (12)

一種半導體保護裝置，其應用於直流電路，當該直流電路的負載發生過載或短路時，其功能為使第一直流電源得到保護，其包括有：一第一半導體，具有一汲極、一源極及一閘極；一第二半導體，具有一集極、一射極及一基極，該第二半導體的集極連接該第一半導體的閘極，該第二半導體的射極連接該第一半導體的源極；一第三半導體，具有一集極、一射極及一基極，該第三半導體的射極連接該第二半導體的射極，該第三半導體的集極連接該第二半導體的基極；一第一電阻器，具有二個連接端，該第一電阻器的一端連接該第一半導體的閘極及該第二半導體的集極；一第二電阻器，具有二個連接端，該第二電阻器的一端連接該第一半導體的汲極成為第二端，該第二端具有提供連接該負載的另一端之功能，該負載的一端連接該第一直流電源的正電端，該第二電阻器的另一端連接該第二半導體的基極及該第三半導體的集極；一第三電阻器，具有二個連接端，該第三電阻器的一端連接該第三半導體的基極；及一延時產生器，具有啟動第一半導體由開路轉為導通的功能，並且具有正電壓端、正電壓輸出端及接地端，該正電壓端連接該第一電阻器的另一端成為第一端，該第一端具有提供連接第二直流電源的正電端之功能，該正電壓輸出端連接該第三電阻器的另一端，該接地端連接該第三半導體的射極、該第二半導體的射極及該第一半導體的源極成為第三端，該第三 端具有提供連接該第一直流電源與該第二直流電源的負電端之功能。 A semiconductor protection device is applied to a DC circuit. When the load of the DC circuit is overloaded or short-circuited, its function is to protect the first DC power supply. It includes: a first semiconductor with a drain and a A source and a gate; a second semiconductor having a collector, an emitter and a base, the collector of the second semiconductor is connected to the gate of the first semiconductor, and the emitter of the second semiconductor is connected to the The source of the first semiconductor; a third semiconductor having a collector, an emitter and a base, the emitter of the third semiconductor is connected to the emitter of the second semiconductor, and the collector of the third semiconductor is connected to the The base of the second semiconductor; a first resistor with two connecting ends, one end of the first resistor is connected with the gate of the first semiconductor and the collector of the second semiconductor; a second resistor with Two connecting ends, one end of the second resistor is connected to the drain of the first semiconductor to become a second end, the second end has the function of providing the other end of the load, and one end of the load is connected to the first DC The positive terminal of the power supply, the other end of the second resistor is connected to the base of the second semiconductor and the collector of the third semiconductor; a third resistor has two connecting ends, one end of the third resistor Connected to the base of the third semiconductor; and a delay generator, which has the function of starting the first semiconductor to turn from open circuit to conduction, and has a positive voltage terminal, a positive voltage output terminal and a ground terminal, and the positive voltage terminal is connected to the first The other end of the resistor becomes the first end. The first end has the function of providing a positive terminal connected to the second DC power source. The positive voltage output end is connected to the other end of the third resistor, and the ground end is connected to the third end. The emitter of the semiconductor, the emitter of the second semiconductor, and the source of the first semiconductor become the third end, and the third The terminal has the function of providing a negative terminal connecting the first DC power source and the second DC power source. 如申請專利範圍第1項所述的半導體保護裝置，其中該第一半導體為N通道金屬氧化半導體場效電晶體或N型絕緣閘極雙極電晶體。 According to the semiconductor protection device described in claim 1, wherein the first semiconductor is an N-channel metal oxide semiconductor field-effect transistor or an N-type insulated gate bipolar transistor. 如申請專利範圍第1項所述的半導體保護裝置，其中該第二半導體為N型電晶體或N通道金屬氧化半導體場效電晶體。 According to the semiconductor protection device described in claim 1, wherein the second semiconductor is an N-type transistor or an N-channel metal oxide semiconductor field effect transistor. 如申請專利範圍第1項所述的半導體保護裝置，其中該第三半導體為N型電晶體或N通道金屬氧化半導體場效電晶體。 According to the semiconductor protection device described in claim 1, wherein the third semiconductor is an N-type transistor or an N-channel metal oxide semiconductor field effect transistor. 如申請專利範圍第1項所述的半導體保護裝置，其中該第一直流電源的正電端連接該負載的一端，該負載的另一端連接該第二端，該第一直流電源的負電端連接該第三端；該第二直流電源的正電端連接該第一端，該第二直流電源的負電端連接該第三端。 The semiconductor protection device according to the first item of the scope of patent application, wherein the positive terminal of the first DC power supply is connected to one end of the load, the other end of the load is connected to the second terminal, and the negative terminal of the first DC power supply is The terminal is connected to the third terminal; the positive terminal of the second DC power source is connected to the first terminal, and the negative terminal of the second DC power source is connected to the third terminal. 如申請專利範圍第5項所述的半導體保護裝置，還包括第一開關與第二開關，該第一開關位於該第一直流電源與該負載之間；該第二開關位於該第二直流電源與該第一端之間。 The semiconductor protection device according to item 5 of the scope of patent application further includes a first switch and a second switch, the first switch is located between the first DC power supply and the load; the second switch is located at the second DC Between the power supply and the first end. 一種半導體保護裝置，其應用於直流電路，當該直流電路的負載發生過載或短路時，其功能為使第一直流電源得到保護，其包括有：一第一半導體，具有一集極、一射極及一閘極；一第二半導體，具有一汲極、一源極及一閘極，該第二半導體的汲極連接該第一半導體的閘極，該第二半導體的源極連接該第一半導體的射極；一第三半導體，具有一汲極、一源極及一閘極，該第三半導體的源極連接該第二半導體的源極，該第 三半導體的汲極連接該第二半導體的閘極；一第一電阻器，具有二個連接端，該第一電阻器的一端連接該第一半導體的閘極及該第二半導體的汲極；一第二電阻器，具有二個連接端，該第二電阻器的一端連接該第一半導體的集極成為第二端，該第二端具有提供該連接負載的另一端之功能，該負載的一端連接該第一直流電源的正電端，該第二電阻器的另一端連接該第二半導體的閘極及該第三半導體的汲極；一第三電阻器，具有二個連接端，該第三電阻器的一端連接該第三半導體的閘極；及一延時產生器，具有啟動第一半導體由開路轉為導通的功能，並且具有正電壓端、正電壓輸出端及接地端，該正電壓端連接該第一電阻器的另一端成為第一端，該第一端具有提供連接第二直流電源的正電端之功能，該正電壓輸出端連接該第三電阻器的另一端，該接地端連接該第三半導體的源極、該第二半導體的源極及該第一半導體的射極成為第三端，該第三端具有提供連接該第一直流電源與該第二直流電源的負電端之功能。 A semiconductor protection device, which is applied to a DC circuit. When the load of the DC circuit is overloaded or short-circuited, its function is to protect the first DC power supply. It includes: a first semiconductor with a collector, a An emitter and a gate; a second semiconductor having a drain, a source and a gate, the drain of the second semiconductor is connected to the gate of the first semiconductor, and the source of the second semiconductor is connected to the The emitter of the first semiconductor; a third semiconductor having a drain, a source and a gate, the source of the third semiconductor is connected to the source of the second semiconductor, the first The drain of three semiconductors is connected to the gate of the second semiconductor; a first resistor has two connecting ends, one end of the first resistor is connected to the gate of the first semiconductor and the drain of the second semiconductor; A second resistor has two connecting ends. One end of the second resistor is connected to the collector of the first semiconductor to become a second end. The second end has the function of providing the other end of the connected load. One end is connected to the positive terminal of the first DC power source, the other end of the second resistor is connected to the gate of the second semiconductor and the drain of the third semiconductor; a third resistor has two connecting ends, One end of the third resistor is connected to the gate of the third semiconductor; and a delay generator has the function of starting the first semiconductor to turn from open circuit to conduction, and has a positive voltage terminal, a positive voltage output terminal and a ground terminal. The positive voltage terminal is connected to the other end of the first resistor to become the first terminal. The first terminal has the function of providing a positive terminal connected to the second DC power supply. The positive voltage output terminal is connected to the other end of the third resistor, The ground terminal is connected to the source of the third semiconductor, the source of the second semiconductor, and the emitter of the first semiconductor to become a third terminal. The third terminal is provided to connect the first direct current power source and the second direct current source. The function of the negative terminal of the power supply. 如申請專利範圍第7項所述的半導體保護裝置，其中該第一半導體為N型絕緣閘極雙極電晶體或N通道金屬氧化半導體場效電晶體。 According to the semiconductor protection device described in item 7 of the scope of patent application, the first semiconductor is an N-type insulated gate bipolar transistor or an N-channel metal oxide semiconductor field effect transistor. 如申請專利範圍第7項所述的半導體保護裝置，其中該第二半導體為N通道金屬氧化半導體場效電晶體或N型電晶體。 According to the semiconductor protection device described in item 7 of the scope of patent application, the second semiconductor is an N-channel metal oxide semiconductor field-effect transistor or an N-type transistor. 如申請專利範圍第7項所述的半導體保護裝置，其中該第三半導體為N通道金屬氧化半導體場效電晶體 或N型電晶體。 The semiconductor protection device according to item 7 of the scope of patent application, wherein the third semiconductor is an N-channel metal oxide semiconductor field effect transistor Or N-type transistor. 如申請專利範圍第7項所述的半導體保護裝置，其中該第一直流電源的正電端連接該負載的一端，該負載的另一端連接該第二端，該第一直流電源的負電端連接該第三端；該第二直流電源的正電端連接該第一端，該第二直流電源的負電端連接該第三端。 The semiconductor protection device according to item 7 of the scope of patent application, wherein the positive terminal of the first DC power supply is connected to one end of the load, the other end of the load is connected to the second terminal, and the negative terminal of the first DC power supply is The terminal is connected to the third terminal; the positive terminal of the second DC power source is connected to the first terminal, and the negative terminal of the second DC power source is connected to the third terminal. 如申請專利範圍第11項所述的半導體保護裝置，還包括第一開關與第二開關，該第一開關位於該第一直流電源與該負載之間；該第二開關位於該第二直流電源與該第一端之間。 The semiconductor protection device described in item 11 of the scope of the patent application further includes a first switch and a second switch, the first switch is located between the first DC power source and the load; the second switch is located at the second DC Between the power supply and the first end.
TW109101132A 2019-05-10 2020-01-14 Semiconductor protection device TWI728650B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910389113.8 2019-05-10
CN201910389113.8A CN111917095B (en) 2019-05-10 2019-05-10 Semiconductor protection device

Publications (2)

Publication Number Publication Date
TW202042467A TW202042467A (en) 2020-11-16
TWI728650B true TWI728650B (en) 2021-05-21

Family

ID=73241892

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109101132A TWI728650B (en) 2019-05-10 2020-01-14 Semiconductor protection device

Country Status (2)

Country Link
CN (1) CN111917095B (en)
TW (1) TWI728650B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719531A (en) * 1985-05-15 1988-01-12 Kabushiki Kaisha Toshiba Overcurrent protective circuit for modulated-conductivity type MOSFET
CN101542877A (en) * 2007-03-30 2009-09-23 卢浩义 Circuit protection and control system and protection control method applying same
TW201208222A (en) * 2010-08-12 2012-02-16 Hon Hai Prec Ind Co Ltd Power protection circuit
TW201530954A (en) * 2013-12-11 2015-08-01 Monolithic Power Systems Inc Short protection circuit for power switch and associated protection method
US9478978B1 (en) * 2013-03-14 2016-10-25 Iml International Short circuits and power limit protection circuits
CN207339248U (en) * 2017-07-05 2018-05-08 上海一旻成峰电子科技有限公司 A kind of general protective circuit, comprehensive protector and Plastic packaging apparatus

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5319515A (en) * 1990-10-12 1994-06-07 Raychem Limited Circuit protection arrangement
CN100490265C (en) * 2006-04-24 2009-05-20 宇泉能源科技股份有限公司 Electric current driving electronic broken circuit protecting equipment
JP4621231B2 (en) * 2007-06-29 2011-01-26 富士通テン株式会社 Power supply protection device and electronic control device
CN201466667U (en) * 2009-07-31 2010-05-12 北京七星华创电子股份有限公司 Protective device of direct current (DC) power supply and load
CN102790374B (en) * 2011-12-19 2015-01-28 洛阳理工学院 Short circuit protection circuit
JP6294061B2 (en) * 2013-11-29 2018-03-14 ローム株式会社 Short circuit protection circuit
TWI548184B (en) * 2014-09-05 2016-09-01 緯創資通股份有限公司 Protection device and method for electronic device
CN105514932B (en) * 2015-12-08 2018-07-03 深圳天珑无线科技有限公司 The short-circuit protection circuit of power supply
CN109245053A (en) * 2018-08-30 2019-01-18 广州金升阳科技有限公司 A kind of overload protecting circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719531A (en) * 1985-05-15 1988-01-12 Kabushiki Kaisha Toshiba Overcurrent protective circuit for modulated-conductivity type MOSFET
CN101542877A (en) * 2007-03-30 2009-09-23 卢浩义 Circuit protection and control system and protection control method applying same
TW201208222A (en) * 2010-08-12 2012-02-16 Hon Hai Prec Ind Co Ltd Power protection circuit
US9478978B1 (en) * 2013-03-14 2016-10-25 Iml International Short circuits and power limit protection circuits
TW201530954A (en) * 2013-12-11 2015-08-01 Monolithic Power Systems Inc Short protection circuit for power switch and associated protection method
CN207339248U (en) * 2017-07-05 2018-05-08 上海一旻成峰电子科技有限公司 A kind of general protective circuit, comprehensive protector and Plastic packaging apparatus

Also Published As

Publication number Publication date
CN111917095A (en) 2020-11-10
TW202042467A (en) 2020-11-16
CN111917095B (en) 2022-06-17

Similar Documents

Publication Publication Date Title
US10283957B2 (en) Supplying load having inrush-current behaviour
US7816898B2 (en) Switching regulator
TWI548184B (en) Protection device and method for electronic device
US8730624B2 (en) Electrostatic discharge power clamp with a JFET based RC trigger circuit
TWI728650B (en) Semiconductor protection device
TW202042469A (en) Semiconductor circuit device
TWI779519B (en) Semiconductor device
TW202040900A (en) Semiconductor device
TW202230923A (en) Semiconductor circuits device
WO2020035712A1 (en) Switching circuit
TW202425469A (en) Electric circuit protection device
TWI760188B (en) Electronic circuit protector
TW202213892A (en) Semiconductor device
TW202215758A (en) Semiconductor circuits device
TW202324869A (en) Electronic circuit protection device
TW202215737A (en) Semiconductor protection device
TW201933712A (en) Semiconductor devices
TW202320440A (en) Electronic circuit protection device
TWI583089B (en) Cell discharge protection device
TW202213891A (en) Dc short circuits protection device
TW202329575A (en) Electric circuit protection device
TW202205770A (en) Dc short circuits protection device
TW202404218A (en) Semiconductor protector
TW202339386A (en) Semiconductor protector
TW202416618A (en) Semiconductor protection circuit