TW201104839A - Integrated circuit memory devices having vertical transistor arrays therein and methods of forming same - Google Patents

Abstract

An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.

Description

201104839 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device method. [Prior Art] In order to satisfy the excellent performance and low cost required by a person, it is necessary to make a semiconductor. The integration of the device is increased. In the case of a memory semiconductor device, the degree of integration is an important factor in the price of the shirt product, and thus it is particularly necessary to increase the degree of integration. In the case of the previous two-dimensional or planar memory semiconductor device, the degree of integration mainly depends on the area occupied by the unit memory cell, and thus the level of the fine pattern forming technology is greatly affected. However, in order to miniaturize the pattern, a high price is required, and thus the integration of the two-dimensional memory semiconductor device is increasing, but there are still limitations. SUMMARY OF THE INVENTION [Problems to be Solved by the Invention] The present invention has been developed in view of the above problems, and it is an object of the invention to provide a memory semiconductor device having an increased degree of integration.

Another object of the present invention is to provide a method of fabricating a memory semiconductor device having increased integration. X Another object of the present invention is to provide a method of operating a memory semiconductor device having increased integration. <Technical means for solving the problem] In order to achieve the above object, a memory semiconductor device according to an aspect of the present invention includes: a plurality of semiconductor patterns having a long axis ' perpendicular to the upper surface of the substrate 145224.doc 201104839 and And a plurality of word lines having a long axis traversing the plurality of semiconductor patterns and arranged in three dimensions between the semiconductor patterns. According to an embodiment, an information storage film pattern (e.g., a charge storage film) interposed between the semiconductor pattern and the sub-line may be further included. According to one embodiment, the word line is configured to control the potential of the semiconductor pattern adjacent thereto. Alternatively, the arrangement of the word lines arranged in the same layer is substantially the same as the arrangement of the word lines arranged in the other layers. According to one embodiment, the memory semiconductor device may further include: a common source electrode electrically connecting a plurality of lower regions of the semiconductor pattern; and a bit line traversing the word line The direction is electrically connected to a plurality of upper regions of the semiconductor pattern. According to one embodiment, the substrate may be a semiconductor substrate including an impurity diffusion region. In this case, the impurity diffusion region may be used as a common source electrode for electrically connecting a plurality of lower ends of the semiconductor pattern. According to one embodiment, a conductive film serving as a common source electrode can be formed between the substrate and the word line. According to one embodiment, a conductive pattern parallel to the word line can be formed between the plurality of word lines as a common source electrode. According to an embodiment of the present invention, the substrate may include a cell array region and a core region formed around the cell array region. In the case of a dome shape, the upper surface of the substrate may be lower in the cell array region than in the core region. According to one embodiment, each of the word lines includes a wiring section parallel to the upper surface of the substrate, 145224.doc 201104839, and a contact section inclined to the upper surface of the substrate. In this case, the contact section may be formed in the above The cell array region is adjacent to the region of the core region. Further, the word line is formed such that the wiring interval is further apart from the upper surface of the substrate, and the contact region is formed apart from the core region. In a form, the upper surface of the contact section of the word line can be formed to have substantially the same height. In order to achieve the above technical problem, the memory semiconductor device of the present invention may include: a lower wiring; at least one upper wiring; Arranging on the lower wiring; at least one intermediate wiring structure including a plurality of intermediate wirings sequentially stacked and disposed between the lower wiring and the upper wiring; at least one semiconductor pattern disposed on the a side surface of the intermediate wiring structure for connecting the lower wiring and the upper wiring And at least one information storage pattern disposed between the semiconductor pattern and the intermediate wiring structure. According to an embodiment, each of the intermediate wirings may be a linear pattern intersecting the upper wiring. In one embodiment, the semiconductor pattern may include an impurity region connected to an upper portion of the upper wiring and a channel region disposed on a sidewall of the intermediate wiring structure to connect the upper impurity region and the lower wiring. The region may have a different conductivity type from the upper impurity region or be in an undoped state. According to the consistent form, the voltage applied to the upper wiring and the lower wiring to the channel region may be transmitted to the upper portion. In addition, in order to achieve the above-described technical problem, the method for manufacturing the memory semiconductor device of the present invention includes forming a layered layer in sequence and repeatedly in order to achieve the above-described technical problem. Insulation film pattern, and A stage including at least one intermediate structure of the intermediate wiring. Specifically, the method may include the steps of: forming the intermediate wiring structure on the substrate, and forming at least one sidewall covering at least the intermediate wiring structure; After the information storage film pattern and at least the semiconductor pattern, at least one bit line connected to the semiconductor pattern and crossing the intermediate wiring is formed. Further, in order to achieve the above-mentioned technical problem, the memory of the present invention is driven A method of operating a semiconductor device includes: a semiconductor pattern having a long axis perpendicular to an upper surface of the substrate, and having a two-dimensional row and a word line having a long axis crossing the semiconductor pattern, and in the semiconductor pattern Between the three dimensions. Specifically, the memory semiconductor device may further include: a common source electrode electrically connecting a plurality of lower regions of the semiconductor pattern; and a bit line traversing the word line The direction electrically connects the plurality of upper regions of the semiconductor pattern; the operation method may include the following steps: controlling the potential of the semiconductor pattern by using a voltage applied to the word line, thereby controlling the semiconductor pattern and the common source electrode or Electrical connection between bit lines. [Effects of the Invention] The plurality of character lines arranged in three dimensions according to the embodiment of the present invention are disposed between a plurality of semiconductor patterns having two axes perpendicular to the vertical axis. Since the plurality of character lines are arranged in three dimensions, the present invention has not only increased integration, but also individual memory cells 145224.doc 201104839 can be independently controlled. On the other hand, a part of the method has been proposed in which a three-dimensional memory cell is realized by sequentially stacking a plurality of memory cells arranged in two dimensions. However, such a method is based on the repetition of the step-by-step process, so that the manufacturing cost is increased. However, according to the present invention, the plurality of word lines and the plurality of semiconductor patterns serving as the channel regions can actually pass through the step of form. According to the present invention, a memory element in a three-dimensional arrangement can be produced without a significant increase in manufacturing cost due to an increase in the number of steps. [Embodiment] The above-described objects, features, and advantages of the present invention are readily understood by the accompanying drawings and the preferred embodiments below. However, the present invention is not limited to the embodiment described herein, but may be embodied in other forms. It is to be understood that the embodiments described herein are intended to be thorough and complete, and are intended to convey the teachings of the invention. In the present specification, when § and a film are on different films or substrates, it means that they can be formed directly on different films or substrates, or a third film can be inserted between them. Further, in the drawings, the thickness of the film and the region are exaggerated in order to effectively explain the technical contents. Further, in the various embodiments of the present specification, the use of the i, 帛2, 帛3, etc. is used to describe various regions, films, and the like, but the regions and films are not limited by the above terms. These terms are only used to distinguish a particular region or film from other regions or films. Therefore, the film quality of the first film of a certain embodiment may be referred to as the second film quality in the other palladium form. Each of the embodiments described and illustrated herein is also exemplified by a detailed supplementary embodiment. Fig. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention. Referring to Fig. 1, an intermediate wiring structure 200 is disposed on a substrate 10. The intermediate wiring structure 200 includes a plurality of insulating film patterns 131, 132, 133, 134, and 135 and a plurality of intermediate wirings 141, 142, 143, and 144 which are laminated in this order. At least one semiconductor pattern 65' is disposed on the side wall of the intermediate wiring structure 2'', and an information storage pattern 55 is disposed between the semiconductor pattern 65 and the intermediate wiring structure 200. A plurality of lower regions of the semiconductor pattern 65 may be connected to the lower portion wiring 20 between the semiconductor pattern 65 and the substrate 10, and the plurality of semiconductor patterns 65 may be disposed on the upper portion of the intermediate wiring structure 2? Connecting the upper portion wiring The substrate 10 may include at least one of a semiconductor, a conductive material, and an insulating material. According to one embodiment, the substrate 1A is a tantalum film having a single crystal structure, and the lower wiring 20 may be an impurity diffusion region formed in the substrate 1A. In this case, the substrate 1G and the impurity diffusion region serving as the lower wiring 20 may have mutually different conductivity types.

Semiconductor, the essence of semiconductors). Crystal semiconductor. In the case of this diffusion region, the above-described half wiring 20 and the diode are of a type. According to one embodiment, the semiconductor in the upper state (intrinsic I45224.doc 201104839, on the other hand, will be described later with reference to FIG. 2A and FIG. 21, the lower wiring 20 may be formed of a conductive material, and in this case, in order to achieve the above In the diode-like rectifying element, the semiconductor pattern 65 includes at least two portions having mutually different conductivity patterns. For example, a portion of the semiconductor pattern 65 disposed around the plurality of intermediate wirings 141 to 144 (hereinafter, The main body portion B may be different from the other region (source region) of the semiconductor pattern 65 that is in contact with the lower wiring 20 in terms of a conductive type, and may be a part of the upper portion of the semiconductor pattern 65 (hereinafter, The drain region D can be formed to have a different conductivity type from the main body portion B. The semiconductor pattern 65 can be extended from one side surface of the intermediate wiring structure 200 and disposed in the middle as shown in the drawing. The other semiconductor patterns 65 on the other side of the wiring structure are connected. In this case, the semiconductor pattern 65 is also The upper wiring 75 is placed on the upper surface of the intermediate wiring structure 200, and the upper wiring 75 is connected to the semiconductor pattern 65 formed on the upper surface of the intermediate wiring structure 200 via a specific plug 70. The wirings 141 to 144 may be at least one of a plurality of conductive materials. For example, the plurality of intermediate wirings 141 to 144 may include a doped semiconductor, a plurality of metals, a plurality of metal nitrides, and a metal halide. At this time, the intermediate wirings 141 to 144 may be formed in a direction crossing the upper wiring 75. According to an aspect of the present invention, the plurality of intermediate wirings 141 to 144 may be controlled by the semiconductor pattern 65. The electrical connection between the upper wiring 145224.doc 201104839 75 and the lower wiring 20 is controlled by the potential '. More specifically, the semiconductor pattern 65 can be capacitively coupled to the intermediate wirings 141 144 144. And constitute M〇s (Metal screening 6

Semiconductor, metal oxide semiconductor) capacitors. In this case, the voltage applied to the intermediate wirings 141 to 144 can variably control the potential of the semiconductor pattern 65 adjacent thereto, and the energy band of the semiconductor pattern 65 can be applied to the intermediate wirings 141 to 144. The applied voltage is inverted. Therefore, the electrical connection between the upper wiring 75 and the lower wiring 20 can be controlled by the voltage applied to the plurality of intermediate wirings 14144 constituting the intermediate wiring structure 200. On the other hand, such an electrical connection can be realized when a plurality of regions which are reversed on the respective sides of the plurality of intermediate wirings 141 to 144 overlap each other. The insulating film patterns 132 to 134 between the plurality of intermediate wirings 141 to 144 may be formed to have a thickness smaller than twice the maximum width of the inverted region so that the plurality of inverted regions may overlap. The insulating film patterns 131 to 135 may be at least one of a plurality of insulating materials, and may include at least one of a hafnium oxide film, a tantalum nitride film, and a hafnium oxynitride film. However, the uppermost insulating film pattern 1 35 can be used as a mask for the subsequent patterning step, and thus can be formed with a thicker thickness than the other plurality of insulating film patterns 1 3 1 to 1 34. Further, according to the embodiment of the present invention of the flash memory device, a high voltage for causing an insulation breakdown phenomenon with the substrate 1 or the lower wiring 2 can be applied to the lowermost intermediate wiring 141. Therefore, the lowermost insulating film pattern 131 can have a thicker thickness than the plurality of insulating film patterns 131 to 134 inserted between the plurality of intermediate wirings 145224.doc -10- 201104839 141 to 144 as shown in the drawing. form. According to another aspect of the present invention, the intermediate wirings 141 to 144 may be used in conjunction with the semiconductor pattern 65 to change the information stored in the information storage pattern 55. According to an aspect of the present invention, when the voltage applied to each of the plurality of intermediate wirings 141 to 144 is independently adjusted, the semiconductor pattern 65 of the side of the specific intermediate wiring can be selectively connected to the upper wiring. 75 or one of the lower wirings 20 described above. That is, a partial region of the semiconductor pattern 65 opposed to the specific intermediate wiring (for example, 142) may be combined with the upper wiring 75 or the lower wiring 20 according to a voltage applied to the other plurality of intermediate wirings 141, 143, and 144. At the same potential. Therefore, when a voltage different from the upper wiring 75 or the lower wiring 20 is applied to the selected intermediate wiring 142, a potential difference that can be used to change the information can be generated at both ends of the information storage pattern 55. According to an aspect of the present invention, the information storage pattern 55, the semiconductor pattern 65, and the intermediate wirings 141 to 144 can be used as a capacitor dielectric film constituting an M 〇 electric crystal. Therefore, the information storage pattern 55 includes at least one of insulating materials. According to another aspect of the present invention, the information storage pattern 55 may be combined with the semiconductor pattern 65 and the intermediate wirings 141 to 144 to constitute an M 〇 electric crystal. In this case, the semiconductor pattern 65 is used as a channel region, the intermediate wiring is used as a gate electrode, and the information storage pattern "uses as a gate insulating film. At this time, a portion of the semiconductor pattern 65 on the side of the insulating film pattern 55 is used. The region is reversed by applying electric dust of 145224.doc 201104839 to the intermediate wirings 14i to i44. Therefore, it can be used as the source/dot electrode of the electric (four). The semiconductor pattern 65 is disposed in the middle of the plurality of strips. The side walls of the wirings 141 to 144, so that the current direction of the m〇s transistor used as the channel region is perpendicular to the upper surface of the substrate 1〇. The information storage pattern 55 includes an insulating material and may include a hafnium oxide film and nitrogen. At least (10) of the fossil film, the oxynitride film, and the high dielectric film. The high dielectric film refers to a plurality of insulating materials having a higher dielectric constant than the oxidized film. Contains oxidized (tetra), titanium oxide film, oxidized film, oxidized film, oxidized lanthanum, oxidized _, oxidized sharp film, oxidized diced film, indium oxide film, yttrium oxide film 'Xiajia 丨 (10) gamma' tiU Nate, lithium titanate ruthenium film and pzT (Lead, lead bismuth titanate) film. Fig. 2 is a cross-sectional view showing the information storage pattern of the _眚10/3 heart yoke form of the present invention. The information storage pattern 55 may include a tunnel insulating film 55a adjacent to the semiconductor pattern 65, an agglomerated insulating film "o, adjacent to the intermediate wiring structure 2", and a charge storage film inserted in the above Between the tunnel insulating film 55a and the above-mentioned agglomerated insulating film Me. In this case, the agglomerated insulating film 55c may include at least one of a hafnium oxide film, a tantalum nitride film, a nitrous oxide film, and a high dielectric film, and may be a multilayer film including two dielectric films according to an embodiment. . The tunnel insulating film 55a may be formed of a substance having a lower dielectric constant than the agglomerating insulating film 55c. The charge storage port 55b may be an insulating film of a charge trap trap (for example, tantalum nitride). Membrane), or an insulating film comprising a plurality of conductive particles 145224.doc 12 201104839. According to one embodiment, the tunnel insulating film 55a may be a hafnium oxide film, the charge storage film 55b may be a tantalum nitride film, and the agglomerate insulating film 55c may be an insulating film including an aluminum oxide film. In this case, the above intermediate wirings 141 to 144 may include a tantalum nitride film. Fig. 3 is a circuit diagram for explaining a cell array structure of a memory semiconductor device according to an embodiment of the present invention. Referring to Fig. 3, the memory semiconductor device of the present embodiment includes a plurality of bit lines BL, a common source electrode CSL, and a plurality of semiconductor patterns 65.

The plurality of bit lines BL are connected to the common source electrode CSL; and the plurality of intermediate lines 140 are opposite to the plurality of semiconductor patterns 65 and traverse the plurality of bit lines BL. A rectifying element may be disposed between the semiconductor pattern 65, the bit line BL, or the common source electrode CSL. An information storage body can be disposed between the inter-command wiring 14A and the semiconductor pattern 65. According to an embodiment, the above-described poor memory storage body may include a film for charge storage as described with reference to Fig. 2 . The unit memory cell uc of the memory semiconductor device of the present embodiment includes the semiconductor pattern 65, an intermediate wiring layer 4 〇 opposite thereto, and an information storage body interposed therebetween. At this time, a plurality of intermediate wirings 14A opposed to one semiconductor pattern 65 are sequentially disposed between the bit line muscle and the common source electrode CSL. Therefore, a plurality of unit memory cells uc sharing a semiconductor pattern 65 are connected in series with the above-described common source electrode CSL. The cell string STR of the memory semiconductor device of the present embodiment includes the above-mentioned bit 4bL, the common source electrode 145224.doc 201104839 pole CSL, and the above-mentioned plurality of unit cells UC connected in series therebetween. According to an embodiment, the intermediate wiring most adjacent to the bit line BL can be used as the upper selection line USL for controlling the electrical connection between the cell string STR and the bit line BL. Further, the intermediate wiring which is most adjacent to the common source electrode CSL can be used as an electrical connection lower selection line LSL between the cell string STR and the common source electrode CSL. The plurality of intermediate wirings 140 between the upper and lower selection lines USL and LSL can be used as a plurality of word line lines WL for changing the information of the unit memory cells UC. To simplify the description, there are two word lines illustrated in the drawing, but the above cell string STR may contain a greater number of word lines. The plurality of word line lines WL may be connected to a plurality of global word lines GWL. At this time, each of the word lines WL constituting one unit string STR is connected to the mutually different global word line GWL. According to one embodiment, as shown in the figure, the global word line GWL is disposed in a direction parallel to the bit line BL for electrically connecting the word line WL. On the other hand, when the above-described global word line GWL is parallel to the bit line BL, the upper selection line USL and the lower selection line LSL may be formed in a direction crossing the bit line BL, so that The above unit memory cell UC can be selected. Fig. 4 is a perspective view showing a part of a cell array of a memory semiconductor device according to an embodiment of the present invention. The memory semiconductor device of this embodiment has the technical features of the present invention described with reference to the above-described embodiments of Figs. 1 and 2 . Therefore, in order to simplify the description, the description of the repeated technical features 145224.doc -14-201104839 can be omitted. Referring to Fig. 4', the memory semiconductor device of the present embodiment includes a plurality of intermediate wiring structures 2 disposed on the substrate 10. The plurality of intermediate wiring structures 200 may be arranged in parallel with each other, and each of them may include a plurality of insulating film patterns 1 3 1 to 13 5 sequentially stacked and repeatedly stacked, and a plurality of intermediate wirings 141 to 144. A plurality of semiconductor patterns 65 traversing the plurality of intermediate wiring structures 200 may be disposed on both side faces of the plurality of intermediate wiring structures 200. According to one embodiment, the semiconductor pattern 65 may be connected to each other on the upper surface of the plurality of intermediate wiring structures 200 and the bottom surface therebetween. In this case, as shown in the figure, the semiconductor pattern 65 can be formed by a linear pattern that traverses the plurality of intermediate wiring structures 2'' and covers the side faces of the plurality of intermediate wiring structures 200. An information storage pattern 55 can be disposed between the semiconductor pattern 65 and the intermediate wiring structure 2A. According to the embodiment, the information storage pattern 55 may include a charge storage film as described with reference to FIG. 2, and the information stored in the information storage pattern 55 may be utilized between the semiconductor pattern 65 and the intermediate wirings 141 to 144. The FN tunneling (Fowler-Nordheim turnneling) caused by the voltage difference is changed. A lower wiring 20 (or a lower impurity region) may be formed in the substrate 1A below the plurality of intermediate wiring structures 2''. The lower impurity region 2 is formed not only under the plurality of intermediate wiring structures 200 but also in the substrate 1 between the plurality of intermediate wiring structures 200, so that the plurality of semiconductor patterns 65 can be electrically connected. On the upper portion of the intermediate wiring structure 200, 145224.doc •15-201104839, a plurality of upper wirings 75 connected to the semiconductor pattern 65 or across the plurality of intermediate wirings 141 to 144 may be disposed. According to the present embodiment, the lower impurity region 20 can be used as a common source electrode (CSL of FIG. 3), and the upper wiring 75 can be used as a plurality of bit lines (BL of FIG. 3), and the plurality of bit lines A write voltage for changing information stored in the information storage pattern 55 or a read voltage for reading the stored information is applied. On the other hand, according to an embodiment of the present invention, in addition to the contact section for connection of the upper wiring described below, the arrangement structure of a plurality of intermediate wirings (for example, 141) arranged in a specific layer may be plural to those arranged in other layers. The arrangement structure of the strip intermediate wirings (for example, 142 to 144) is substantially the same. Fig. 5 to Fig. 1 are perspective views for explaining a method of manufacturing a memory semiconductor device according to an embodiment of the present invention. Referring to Fig. 5, a substrate 1 having a cell array region (CeU Array Region) and a core region (Core Region) is prepared. * The upper surface of the cell array region is formed lower than the upper surface of the core region. According to an embodiment, such a configuration can be formed via a patterning stage in which the substrate 1 is formed into a groove in the cell array region. According to another embodiment, the configuration may be formed by forming a specific film having a thickness corresponding to the step difference between the two regions on the substrate 1A after the unit array region The above film is etched. Thereafter, as shown in the figure, a plurality of insulating films 31, 32, 33, 34, 35 and a plurality of conductive films 41, 42, 43, 44 are vapor-deposited sequentially and repeatedly on the substrate 1''. At this time, the plurality of insulating films 31 to 35 and the plurality of conductive layers 145224.doc -16 - 201104839 are formed conformally on the substrate 1 . The total thickness of the plurality of insulating films 3 1 to 3 5 and the plurality of conductive films 41 to 44 may be smaller than the step Η between the cell array region and the core region. The plurality of insulating films 31 to 35 may be a hafnium oxide, a tantalum nitride film, or a hafnium oxynitride film. On the other hand, the thickness of the plurality of insulating films 32 to 34 interposed between the plurality of conductive films 41 to 44 may be such that the inverted regions illustrated in Fig. i overlap (〇vedap Qf inversi〇n regi ( The technical characteristics of the ms) are all within the range of the selection. However, the uppermost insulating film 35 can be used as a pattern in the subsequent patterning, (4) reading (4) reading other plural, 彖 film 31~34 thicker The lowermost insulating film is formed to have a thicker thickness than the plurality of insulating films 32 34 interposed between the plurality of conductive films 41 to 44 to prevent the lowermost portion. Insulation breakdown between the intermediate wiring (141 of FIG. 3) and the substrate 1G or the lower impurity region 2 () The plurality of conductive films 41 to 44 may include doped semiconductors, metals, metal nitrides, and metals. At least one of the tellurides. As shown in FIG. 1, the memory cell of the embodiment of the present invention has a vertical channel, and the thickness of the plurality of conductive films 41 to 44 is the memory cell crystal. In such a situation, the above plurality of conductive The thickness of the films 41 to 44 can be selected within a range that satisfies the technical length of the channel length of the memory cell: (for example, preventing the short channel effect). According to an embodiment, the plurality of insulating films are formed. Before the plurality of conductive films 41 to 44 and the plurality of conductive films 41 to 44, the lower impurity region 20 may be formed in the cell array region of the substrate 1 . The lower impurity region 2 may be formed as 145224.doc • 17-201104839 having the substrate 1 〇 different conductivity types, in this case, can be used as the common source electrode CSL described with reference to Fig. 3. Referring to Fig. 6, the plurality of insulating films 3 1 to 35 and the plurality of conductive films 41 to 44 is patterned to form an intermediate wiring structure 200 defining a plurality of trenches for exposing the upper surface of the substrate 10. The intermediate wiring structure 200 may include a plurality of insulating film patterns 13, 132, 133, and 134. 135' is formed by patterning the plurality of insulating films 31 to 35 and the plurality of conductive films 41 to 44, and a plurality of intermediate wirings 141, 142, 143, and 144. The plurality of intermediate wirings 141 to 144 and the side surfaces of the plurality of insulating film patterns 131 to 135 are exposed to define the trench Τ. The plurality of intermediate wiring structures 2 can be formed by photolithography and etching steps. After the uppermost insulating film 135 is patterned, it is formed by using the patterned uppermost insulating film 丨35 as a patterning step of the hard mask. According to the modified embodiment, the plurality of intermediate wirings may be formed. Before the structure 200, further comprising a step of forming another mask film for etching the mask in order to reduce the difficulty in patterning caused by the step difference between the cell array region and the core region The resultant is planarized and etched after the front side of the substrate. According to another embodiment of the present invention, the plurality of intermediate wiring structures 200 can be formed through a plurality of patterning stages. For example, the plurality of insulating films 31 to 35 and the plurality of conductive films 41 to 44 may be independently patterned in the core region and the cell array region. Specifically, the patterning stage may include the following steps: first, patterning the film of the above-mentioned core region to form a mask film covering the patterned core region, The above cell array regions are patterned. Referring to Fig. 7, after the information storage film pattern 55 covering the side surface of the intermediate wiring structure 2 is formed, a semiconductor film 6 is formed on the resultant. The above-mentioned asset A storage film pattern 55 is extended from the side surface of the intermediate wiring structure 2 to cover the upper surface of the intermediate wiring structure 2 . According to the present embodiment, the information storage film pattern 55 can be formed such that the upper surface of the substrate 10 is exposed at the bottom of the trench T. Therefore, the step of removing the information storage film pattern 5 at the bottom of the trench T can be further carried out. ☆ According to the embodiment of the deformation, in order to prevent the information storage film pattern 55 from being damaged, the above-described step can be carried out in a state where the information storage film pattern 55 is covered with a specific protective film. For example, the above semiconductor may be formed by two or more steps, and the earliest vaporized transfer film may be used as the above protective film. The information storage film pattern Μ may include a charge storage film according to the shape of the ruthenium. For example, the information storage film pattern 55 may include an agglomerated insulating film 55e sequentially stacked as shown in FIG. 2, a charge storage film, and a tunnel insulating film. The above-mentioned agglomerated insulating film may include an oxygen cut film or a nitrogen cut film. At least one of a nitrous oxide film and a high dielectric film, the ruthenium comprising a plurality of films. In this case, the above-mentioned high dielectric film means an insulating material having a higher dielectric constant than the above oxygen film, and may include an oxide film, a titanium oxide film, an oxide film, a zirconium oxide film, an aluminum oxide film, and oxidation. Antimony film, hafnium oxide film, oxidized film, indium oxide film, silver oxide film, brittle film, and ρζτ film. The above-mentioned accompanying channel 145224.doc -19·201104839*, a may have a lower dielectric constant than the above-mentioned agglomerating insulating film... The above-mentioned charge storage film 55b may be an insulating (four) film rich in charge trapping traps ( For example, a nitrogen film), or a plurality of conductive tweezers, a .g edge J. phase. According to the embodiment, the above-mentioned track insulating film may be an oxide film. The charge storage film 55b may be a nitride film, and the agglomerate film 55c may be an insulating film containing an oxide film. The feeding conductor film 60 may be a single crystal semiconductor or a polycrystalline semiconductor, and may be formed by a vapor phase evaporation technique or an epitaxial technique. The semiconductor film 6A may be formed in a conformal thickness as shown in the figure, or may be formed to substantially fill a remaining space of the trench τ in which the information storage film pattern 55 is formed. According to an embodiment, the semiconductor 臈6 〇 may have a different conductivity type from the lower impurity region 2 , to constitute the lower impurity region 2 二 and the diode. Referring to Fig. 8 (4), the result of the semiconductor film 6 is described as being planarized and etched to expose the upper surface of the substrate 10. On the other hand, as described above, the total thickness t of the plurality of insulating films 31 to 35 and the plurality of conductive films 4 to 44 may be smaller than the step Η between the cell array region and the core region. In the case of such an embodiment, the plurality of intermediate wirings 141 to 144 and the plurality of insulating film patterns 131 to 135 are disposed inside the unit array region so as to be limited by the flattening. On the other hand, each of the plurality of intermediate wirings 141 to 144 limited to the inside of the unit array region may have a wiring section parallel to the upper surface of the substrate 1 and an extension of one or both ends of the wiring section. Contact interval. At this time, the contact section of the plurality of intermediate wirings 141 to 144 is disposed at a boundary between the unit array region and the core region 145224.doc • 20·201104839 near as a result of the flattening characterization, the upper surface It can be formed at the same height as the upper surface of the substrate ίο exposed. According to an embodiment, the planarization etching may be further formed

The buried insulating film 88 in which the result of the above-described semiconductor film 60 is formed and the trench T is filled is covered. In this case, the upper surface of the contact section of the plurality of intermediate wirings 14i to 144 is exposed between the substrate 1A and the buried insulating film. Referring to Fig. 9, the semiconductor film 6 is patterned to form a plurality of semiconductor patterns 65 which traverse the intermediate wiring structure 2A. The step of forming the semiconductor pattern 65 may include a step of patterning the buried insulating film 88 to form a buried insulating film pattern 99 defining an opening portion 99a for exposing the semiconductor film 60, and etching the exposed portion The semiconductor film 60. At this time, the opening portion 99a may be formed in a direction H across the intermediate structure (four), and the semiconductor (four) 65 may be formed in a direction crossing the intermediate wiring structure 2'. The step of etching the buried insulating film can be carried out by a method of anisotropic (4) for the above-mentioned semiconductor film, and the stage of the semiconductor film 60 can be utilized for the above-mentioned buried insulating film. The method of narration is implemented. The step of engraving the semiconductor film 6 can be carried out by means of isotropic etching so that the semiconductor film 60 can be separated on the side surface of the intermediate wiring structure. However, the last stage of the above-described semiconductor film 60 can be carried out by the anisotropic meal engraving method and the isotropic etching method, or a combination thereof. According to the embodiment, after the semiconductor pattern & is formed, the information storage film pattern 55 can be further etched so that the intermediate wiring structure 200 is exposed as shown in the drawing of I45224.doc - 21 - 201104839. Referring to Fig. 10', after forming an insulating film (not shown) in which the opening portion 99a is filled in the result of forming the semiconductor pattern 65, the semiconductor pattern 65 and the plurality of intermediate wirings 14A to 44 are formed. The upper wiring 75. The upper wiring 75 connected to the semiconductor pattern 65 and the plurality of intermediate wirings 141 to 144 is used as a plurality of bit lines BL and a global intermediate wiring gw1 described with reference to Fig. 3 . Further, after the upper wiring 75 is formed, the upper selection line USL and the lower selection line LSL are connected to the uppermost intermediate wiring 144 and the lowermost intermediate wiring 141, respectively. The upper and lower selection lines are formed in a direction crossing the bit line BL as shown in the figure. Figs. 11 and 12 are circuit diagrams and perspective views for explaining a cell array structure of a memory semiconductor device according to another embodiment of the present invention. In order to simplify the description, the description of the technical features repeated with the embodiment described with reference to Figs. 3 and 4 above will be omitted. Referring to Fig. 11 and Fig. 12, according to the present embodiment, the lower selection line LSL can connect the cell strings _ in a direction parallel to the bit line BL. However, in the same manner as the embodiment described with reference to Fig. 3, the upper selection line USL is connected to the cell string STR which is directed across the bit line BL. In this case, the - cell string can be selected by the above bit line BL and the above upper selection line USL. FIG. 13 is a circuit diagram showing a structure of a cell array of a memory semiconductor device according to another embodiment of the present invention. FIG. 13 is a circuit diagram for explaining a semiconductor device of the embodiment of 145224.doc. 22-201104839. A perspective view of the manufacturing method. For the sake of simplification of the description, the description of the technical features overlapping with the embodiments described with reference to Figs. 3 and 4 will be omitted. According to the present embodiment, as shown in Fig. 14, a plurality of localized semiconductor patterns 65a and 65b can be disposed on both side faces of one of the intermediate wiring structures 200. Unlike the above-described embodiment, the semiconductor patterns 65a and 65b of the present embodiment are not extended to the side opposite to the intermediate wiring structure 2, but are cut at the upper portion thereof. At this time, the semiconductor pattern 65a disposed on one side surface of the intermediate wiring structure 200 may be disposed between the plurality of semiconductor patterns 65b. The plurality of semiconductor patterns 65b are disposed on the other of the intermediate wiring structures 2 side. In other words, the semiconductor patterns 65a and 65b are alternately arranged on the both sides 6 along the intermediate wiring structure 2, and the openings 99a of the buried insulating film pattern 99 can be formed to be different from each other. The intermediate wiring structure 200 is slanted across the two directions. That is, the opening portion 99a can be formed by a mesh structure. As shown in Fig. 15, the semiconductor pattern 65a disposed on one side surface of the intermediate wiring structure 2 and the adjacent semiconductor pattern 65b disposed on the other side surface are connected to a plurality of bit lines different from each other. In this case, as shown in FIG. 13, each of the localized semiconductor patterns 65a and 6515 constitutes an independently controllable cell string STR, so that the number is increased as compared with the embodiment described above with reference to FIG. The memory cells can be formed in a single 7C array region of the same area. Fig. 16 and Fig. 17 are perspective views for explaining the electrical connection structure of the intermediate wiring 145224.doc • 23-201104839 according to the embodiment of the present invention. As described with reference to Fig. 5, the plurality of conductive films 41 to 44 can be conformally formed. In this case, an angle between a contact section of the plurality of intermediate wirings 141 to 144 and an upper surface of the substrate 1 可 may be a boundary surface between the unit array region and the core region and an upper surface of the substrate 1 The angles formed are essentially the same. For example, as shown in FIG. 6, when the boundary surface between the cell array region and the core region is perpendicular to the upper surface of the substrate, the contact interval of the plurality of intermediate wires 141 to 144 is still adjacent to the substrate 1 The upper surface is formed vertically. On the other hand, according to another embodiment of the present invention, as shown in Fig. 17, the boundary surface between the cell array region and the core region forms an angle 小于 of less than 90 degrees with respect to the upper surface of the substrate 10. In this case, the area of the upper surface of the plurality of intermediate wirings 141 to 144 exposed by the planarization etching is increased as compared with the above embodiment. Specifically, if the thickness and width of the intermediate wiring are & and b, respectively, the exposed area of such intermediate wiring is ab in the case of the above embodiment, and ab/sine in the case of the present embodiment. Therefore, as the angle is decreased, the exposed area of the plurality of intermediate wirings 141 to 144 is increased. According to an embodiment, the above angle may be between 3 degrees and 90 degrees. Fig. 18 to Fig. 2 are perspective views each showing an electrical connection structure of a lower wiring of an embodiment of a modification of the present invention. Referring to Fig. 18, according to the present embodiment, the lower impurity region 2 can be formed by the ion implantation step using the intermediate wiring structure 200 as an ion mask after the intermediate wiring structure 2 is formed. Here, the lower impurity region 2〇 may be partially formed between the plurality of intermediate wiring structures 200 (i.e., in the substrate 10 of the trench). On the other hand, in order to make the above-mentioned lower impurity region 20 usable as the common source electrode CSL as described above, these may be electrically connected to each other. For example, as shown in Fig. 19, the lower impurity region 20 may be extended from the cell array region to the sidewalls and the upper surface of the core region. In this case, the electrical connection to the lower impurity region 2A serving as the common source electrode CSL becomes easy. That is, as shown in Fig. 19, the extended lower impurity region may be connected to the source line SL of the transfer source voltage. According to an embodiment of the present invention, the common source electrode CSL can be formed of a conductive material by the lower wiring 20. For example, as shown in FIG. 20, the conductive line 2〇a formed under the trench τ can be used as the common source electrode CSLe in this case, and can be formed below the semiconductor pattern to form a diode. The source impurity region S having a conductivity type different from that of the body portion B is formed in a bulk manner. The source impurity region s needs to be formed lower than the lowermost intermediate wiring 141 so that the above-mentioned conductive line 2〇a The lowermost insulating film pattern 131 can be formed to have a thickness thicker than the thickness of the semiconductor film and the conductive line 20a. The embodiment according to another modification is as shown in the figure. 21, the semiconductor pattern 65 may be connected to the upper surface of the specific conductive plate 20b serving as the common source electrode cs1. In this case, the conductive plate bird can be limited to:: array area In other respects, according to such a poor form, the substrate 1 does not need to be limited to a semiconductor material. This embodiment can be applied to 145224.doc -25-201104839 After the unit array structure is formed on the insulating substrate, the method of connecting to the peripheral circuit by a wafer bonding technique or the like is used. However, when the substrate 10 is a semiconductor or a conductive material, the substrate 10 and the conductive plate 20b are formed. The insulating film 12 can be further inserted between them. Fig. 22 and Fig. 23 are respectively a perspective view and a circuit diagram for explaining a cell array structure of a memory semiconductor device according to another embodiment of the present invention. 2 to 23, there is provided a ground selection region GSR, a string selection region SSR, and a memory region MMR disposed between the two. The substrate 10 has at least one word line structure and at least one semiconductor pattern 65 disposed on the memory region MMR of the substrate 10. The word line structure includes a plurality of word lines WL of the two sequential layers, The semiconductor pattern 65 faces the word line structure and traverses the word line WL. The word line structure and the half The information storage pattern 55 can be inserted between the body patterns 65. The above-mentioned Bayesian memory pattern 55 can be the same as that described with reference to FIG. 7. The ground selection area GSR of the earth plate is configured to use the ground selection line GSL as a gate. a plurality of ground selection transistors (10) of the electrode electrodes are arranged on the φ selection region SSR of the earth plate 0. The string selection transistor SST for using the string selection line as the idle electrode is disposed. The ground selection line GSL and the string selection line The SSL can be formed to have a long axis parallel to the above-described word line WL. Root 145224.doc -26· 201104839

According to one embodiment, the ground selection transistor GST and the string selection electric BB body SST may be a metal-oxide-transistor (Metal-Oxide-Semiconductor «Field-Effect-Transistor) using the substrate 1〇 as a channel region. Semiconductor field effect transistor). An impurity region 25 serving as a source and a drain electrode of the ground selection transistor GST may be formed in the substrate 10 on both sides of the ground selection line GSL and in the substrate 10 on both sides of the string selection transistor SST . According to an embodiment, the semiconductor pattern 65 may be formed to have a different conductivity type β than the impurity region 25, and the source electrode of the ground selection transistor GST is commonly connected to a common source parallel to the word line WL. Each of the drain electrodes of the ground selection transistor GST may be connected to one of the ends of the semiconductor pattern 65. Therefore, the semiconductor pattern 65 can be extended from the memory region MMR to the ground selection region GSR. The drain electrode of the above-mentioned selective transistor sst may be connected to a plurality of bit lines BL having a long axis crossing the direction of the word line wL, and the source electrode of the string selection transistor SST may be connected to the semiconductor pattern The other end of 65. Therefore, the semiconductor pattern 65 can be elongated from the memory region MMRs to the string selection region SSR. According to one embodiment, the lower insulating film 12 can be disposed under the word line structure. The lower insulating germanium 12 may be an element isolation film that defines an active region, such as a shallow trench isolation insulating layer (STI). The semiconductor pattern 65 on the memory region MMR may be from the substrate 1 The 〇 is formed by separation. The above-mentioned semiconductor pattern 65 may be a ruthenium or a gas containing hydrogen therein, and the thickness of the plurality of solar cells 145224.doc -27 201104839 may be 5 (10) to _ (10). According to an embodiment, the thickness of the semiconductor pattern 65 may be approximately 15 (10) to 25 nm. The semiconductor pattern 65 can be used as an electrical path connecting the ground selection transistor gst and the string selection transistor SST or the common source line cs1 and the bit line BL. The electrical path may be such that the voltage applied by the word line i adjacent to the semiconductor pattern 65 is applied to the 兀琛WL and the information storage pattern 65 adjacent to the word line WL. The potential (electric P -) is selectively performed, and the potential of the information storage pattern "may be different according to the information stored in the information storage pattern 55. As a result, the constituent elements of the semiconductor pattern 65 are not shown in FIG. Fig. 24 and Fig. 25 are a perspective view and a plan view showing a cell array structure of a memory semiconductor device according to another embodiment of the present invention, in order to simplify the NANDarray. The description may omit the description of the technical features overlapping with the embodiments described with reference to FIGS. 1 to 23. Referring to FIG. 24 and FIG. 25, a plurality of intermediate wiring structures and bodies 200 _L are arranged. The intermediate wiring structure body may include at least one character line structure WLS that is spaced apart from each other, the ground selection structure Gss and the string selection structure, and between the three temples. In this case, each of the plurality of inter-wiring wiring structures may include a plurality of intermediate wirings sequentially stacked, and the ground selection structure gss includes a plurality of intermediate wirings which are used as the ground selection line GSL. The string selection structure SSS packet 3 is used as a plurality of laminated intermediate wirings of the string selection line SSL, 145224.doc -28- 201104839 The above word line structure WLS may include a plurality of laminated layers used as the word line WL. According to one embodiment, the ground selection structure GSS, the string selection structure sss, and the word line structure wls may each be formed of the same structure. The two sides of the intermediate wiring structure 200 are formed. A plurality of semiconductor patterns 65 traversing the intermediate wiring structure 200 may be disposed. According to one embodiment, the semiconductor patterns 65 may be connected to each other on the upper surface of the intermediate wiring structure 2 and the bottom surface therebetween. In this case, as shown in FIG. 24, the semiconductor pattern 65 can traverse the plurality of intermediate wiring structures 200 and cover the intermediate wiring. The information storage pattern 55 is disposed between the semiconductor pattern 65 and the intermediate wiring structure 200. According to the embodiment, the information storage pattern 55 is as described with reference to FIG. Generally, the charge storage film may be included, and the information of the information storage pattern 55 may be changed by the FN tunneling caused by the voltage difference between the feeding conductor pattern 65 and the intermediate wirings 141 to 144. The selected structure sss and a partial region 65d of the semiconductor pattern 65 adjacent to the ground selection structure GW may be formed to have a different conductivity type from the other regions 65b. For example, the portion (four) 65d of the semiconductor pattern 65 disposed on the upper portion of the string selection structure SSS and the ground selection structure Gss may be formed to have the semiconductor pattern adjacent to the sidewall of the word line structure WLS. The other regions of 65 are different in conductivity type 65b. According to another embodiment, as shown in FIG. 25 145224.doc -29-201104839, the upper portion of the plurality of intermediate wiring structures 2 与 and the plurality of intermediate wiring structures 2 可 can be formed and utilized. The impurity region 65d doped with impurities of different conductivity types of the main body portion 65b of the side wall of the intermediate wiring structure 200 is covered. The impurity region 65d can be formed by using an ion implantation step in which the spacer Sp covering the side wall of the intermediate wiring structure 2 is used as an ion implantation mask. The distance between the impurity region 65 (1) and the intermediate wiring structure 200 may be smaller than the maximum width of the inversion region generated by the voltage applied to the intermediate wiring. The plurality of intermediate wiring structures 2 The upper plurality of bit lines BL are disposed across the upper portion, and the plurality of bit lines b1 are connected to the impurity regions 65d adjacent to the string selection structure sss via the bit line plugs BL_PLG. A common source line cs1 electrically connected to the impurity region 65d adjacent to the ground selection structure 〇ss may be disposed above the plurality of intermediate wiring structures 2A. The description will be made with reference to FIGS. 24 and 25. According to the embodiment, as described above, the ground selection structure GSS, the string selection structure sss, and the word line structure WLS may each have substantially the same structure. Therefore, the structure is formed by structures different from each other. Compared with the case of the case, the manufacturing method can be simplified. Compared with the embodiment described with reference to FIGS. 22 and 23, the ground selection electro-crystal can be reduced according to the present embodiment. And selecting the area for the transistor 'and the technical difficulty in the manufacturing step caused by the difference in southness between the ground selection line and the word line of the layer. Moreover, in the result of the construction, In the case of a semiconductor device of 24, the aa chip area can be increased without increasing the complexity of the manufacturing steps, and the composition is increased by a unit 145224.doc -30· 201104839

Select the number of transistors and also the string. Such an increase in the number of selected transistors can effectively suppress leakage current, and thus the inverse flash memory device of the present embodiment has improved electrical characteristics. Figure 26 is a block diagram schematically showing an embodiment of a memory card 1200 including the flash memory device of the present invention. Referring to Fig. 26, in order to support high-capacity data storage capability, the flash memory device 1210 of the present invention is installed in the memory card 1200. The tree memory card 120 includes a memory controller 122 that controls various data conversions between the host Host and the flash memory device 1210. An SRAM (static rand 〇 access mem ryry) 1221 is used as the operational memory of the processing unit 1222. The host interface coffee includes a data conversion protocol of the host connected to the memory card U00. The error correction block 1224 detects and corrects errors contained in the data read from the multi-bit flash memory device ΐ2ι〇. The memory interface 1225 is interfaced with the flash memory device 1210 of the present invention. The processing unit is configured to perform various control operations for data conversion by the memory controller 122. Although not shown in the drawings, it is known to those of ordinary skill in the art that the memory card 1200 of the present invention can further provide R〇M (read-〇nlymemory, read-only memory) for storing the data associated with the interface of the host. Body) (not shown), etc. According to the above flash memory device and memory card or memory system of the present invention, it is possible to pass the memory device of the fast memory device mo« which has improved the deletion characteristics of the dummy cells. The inter-memory memory device of the present invention can be provided, in particular, by a recently developed semiconductor disk device (Solid State Disk): the following memory system. 'After blocking the read errors generated by the self-deficient 145224.doc • 31 · 201104839 unit, the reliability is both dry and sorrowful. Figure 27 is a simplified representation of the installation of the invention. The block diagram of the information processing system 1300 of the body system 13 10. Referring to _, the present invention is installed on the information processing system like a desktop computer, and the flash memory is integrated 1310. The information processing system of the present invention ” w I 3 flashing 糸 13 10, with each system bus J 36 〇 electrical, 丨 connected modem 1320, central processing unit 1330, RAM (random access me 々揞 Ηζ, Ηζιλχζ Mem〇ry, random memory H) m〇 and user interface 135. The flash memory system can be constructed substantially the same as the above described memory system or flash memory system. In the flash memory system 13 attached, stored The data processed by the medium wheat processing device 1330 or the data input from the outside. Here, the flash memory system (10) may include the semiconductor magnetic disk device ss 2, and in this case, the information processing system 13 The large-capacity data is stably stored in the flash memory system 1310. And as the reliability increases, the flash memory system 131 can save resources required for erroneous correction, and thus the information processing system 13〇〇 A high speed data conversion function can be provided. Although not shown to those skilled in the art, an application chip set can be further provided in the communication processing system 1300 of the present invention.

ChiPSet), Camera lmage Sensor (CIS), input and output devices, etc. This & clear flash memory device or memory system can be packaged and packaged in various forms. For example, the flash memory device or memory system of the present invention can be packaged and installed in the following manner: P〇P (Package on

Package, go to peak belly m, J 哒 )), Ball grid arrays (BGAs, spherical grid array 145224.doc -32- 201104839 column), Chip scale packages (CSPs, wafer size package), plastic Leaded Chip Carrier (PLCC' Plastic die-loaded package), piastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form , Chip On Board (COB, substrate flip chip bonding), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP, plastic metric quad flat package) ' Thin Quad Flat Pack (TQFP, thin quad flat package), Small Out line (SOIC, small outline package), shrink Small Out line Package (SS0P, reduced form factor package), TMn line (TSOP, thin small package), Thin Quad Flat pack (TQFp, thin quad flat package), System In Package (SIP, system-in-package), Multi Chip Package (MCP, multi-chip package), WafeMevel Fabricated PaCkage (WFP, wafer-level package) , Wafer_

Level Processed Stack package (wsp, wafer level stack package) and so on. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention; FIG. 2 is a cross-sectional view showing a step of explaining an information storage pattern according to an embodiment of the present invention; Figure 4 is a circuit diagram showing a cell array structure of a memory semiconductor device according to an embodiment of the present invention; and Figure 4 is a perspective view showing a portion of a cell array of a memory semiconductor device according to an embodiment of the present invention; 145224.doc • 33-201104839; FIG. 6 is a perspective view for explaining a method of manufacturing a memory semiconductor device according to an embodiment of the present invention; FIG. 7 is a perspective view for explaining a method of manufacturing a memory semiconductor device according to an embodiment of the present invention; FIG. 8 is a perspective view for explaining a method of manufacturing a memory semiconductor device according to an embodiment of the present invention; FIG. 9 is a view for explaining an implementation of the present invention; A perspective view of a method of manufacturing a memory semiconductor device of the form; FIG. 1 is a view for explaining the present invention FIG. 11 is a circuit diagram for explaining a cell array structure of a memory semiconductor device according to another embodiment of the present invention; FIG. 12 is a view for explaining another structure of the present invention; FIG. 14 is a circuit diagram for explaining a cell array structure of a memory semiconductor device according to another embodiment of the present invention; FIG. 14 is a view for explaining another embodiment of the present invention; Fig. 5 is a perspective view for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention; and Fig. 16 is a view for explaining a plurality of intermediate portions of an embodiment of the present invention FIG. 17 is a perspective view for explaining an electrical connection structure of a plurality of intermediate wirings according to an embodiment of the present invention; FIG. 18 is a perspective view for explaining the implementation of the present invention. FIG. 19 is a perspective view showing the electrical connection structure of a plurality of lower wirings of the form; FIG. FIG. 20 is a perspective view for explaining an electrical connection structure of a plurality of lower wirings according to an embodiment of the present invention; FIG. 21 is a perspective view for explaining an embodiment of the present invention. FIG. 22 is a perspective view showing a cell array structure of a memory semiconductor device according to another embodiment of the present invention; FIG. 23 is a view for explaining another embodiment of the present invention. Figure 24 is a perspective view showing a cell array structure of a memory semiconductor device according to another embodiment of the present invention; and Figure 25 is a view for explaining another embodiment of the present invention. FIG. 26 is a block diagram schematically showing an embodiment of a memory card including the flash memory device of the present invention; and FIG. 27 is a simplified representation of the present invention. A block diagram of one embodiment of a memory card of a flash memory device. [Main component symbol description] I45224.doc •35· 201104839 10 Substrate 20 lower wiring. 55 Information storage pattern 65 Semiconductor pattern 75 Upper wiring 131, 132, 133, 134, 135 Insulation film patterns 141, 142, 143, 144 Intermediate wiring 200 intermediate wiring structure 145224.doc •36

Claims (1)

201104839 VII. Patent application scope: 1 . A memory semiconductor device comprising: a ground selection structure and a string selection structure, which are arranged apart from each other; 'at least one memory structure including sequential layers And a plurality of word lines disposed between the ground and string selection structures; and at least one semiconductor pattern covering the upper surface and the sidewall of the memory structure, crossing the plurality of word lines, and It is connected to the grounding and string selection structure described above. 2. The memory semiconductor device of claim 1, further comprising: an information storage film 3 interposed between the semiconductor pattern and the memory structure; the memory semiconductor device of claim 2, wherein the information is stored The film pattern contains a charge storage film. 4. The memory semiconductor device according to claim 1, further comprising: the ground and string selection structure; and a substrate disposed under the word line structure, wherein the ground and string selection structure includes the substrate A plurality of MOS-FETs serving as a channel, wherein the memory structure includes a plurality of MOS-FETs using the semiconductor pattern as a sequential layer of channels. 5. The memory semiconductor device of claim 4, wherein the plurality of ground and string selection structures comprise parallel to the plurality of words, and the ground selection line and the string selection line are respectively used as a closed-pole power I45224.doc 201104839 The plurality of MOS-FETs include a plurality of MOS-FETs using the plurality of word lines sequentially stacked as a gate electrode. 6. The memory semiconductor device according to claim 5, wherein the ground selection structure includes a first impurity region and a second impurity region formed in the substrate on both sides of the ground selection line, and the plurality of first and second regions The impurity region is connected to each of the semiconductor patterns and to a common source line parallel to the ground selection line, and the string selection structure includes a third impurity region and a fourth impurity region formed in the substrate on both sides of the string selection line In the impurity region, the plurality of third and fourth impurity regions are connected to each of the semiconductor patterns and the bit line crossing the string selection line. 7. The memory semiconductor device according to claim 1, wherein the semiconductor pattern is extended from a periphery of the memory structure, and covers an upper surface and a sidewall of the ground and string selection structure, and each of the ground and string selection structures The plurality of MOS-FETs are formed by using a plurality of conductive wires sequentially stacked as a gate electrode, using the semiconductor pattern as a channel, and sequentially stacking the layers. 8. The domain semiconductor device of claim 7, wherein the plurality of conductive lines of the grounding and serial selection 2 are in a plurality of lines of material f, film thickness, and layer-to-number, and the memory structure The character lines are consistent in quality. 9. The memory semiconductor device of claim 7, wherein 匕3 is a common source line parallel to said plurality of word lines, and 145224.doc 201104839 traverses said plurality of word lines to Μ 位 位The line, the common source line is connected to a portion of the semiconductor pattern extending toward an upper portion of the ground selection structure, and the bit line is connected to another portion of the semiconductor pattern extending toward an upper portion of the string selection structure. 11. The memory semiconductor device of claim 1, wherein the semiconductor pattern comprises a body portion adjacent to a sidewall of the plurality of word lines, and a surface adjacent to an upper surface of the ground and string selection structure The plurality of impurity regions have a different conductivity type from the impurity region. The memory semiconductor device according to claim 10, further comprising: the ground and string selection structure; and a substrate disposed under the word line structure, wherein the plurality of impurity regions are further formed on the memory structure a memory structure between the memory structure adjacent to the substrate, the memory structure adjacent to the substrate, and the ground selection structure, and the memory structure and the string selection structure adjacent to the substrate At least 1 position between. The memory semiconductor device of claim 10, further comprising the ground and string selection structure, and a plurality of spacers disposed on a side of the word line structure to cover the semiconductor pattern. 145224.doc