200930199 •九、發明說明： •【發明所屬之技術領域】 本發明涉及電路板技術領域，尤其涉及一種電路板製 作方法。 【先前技術】 隨著電子產品往小型化、高速化方向發展，電路板亦 從單面電路板往雙面電路板甚至多層電路板方向發展。雙 面電路板係指雙面均分佈有導電線路之電路板。多層電路 ❹板係指由複數個單面電路板或雙面電路板積層而成之具有 三層以上導電線路之電路板。由於雙面電路板與多層電路 板具有較多佈線面積而得到廣泛應用，請參見Takahashi，A. 等人於 1992 年發表於 IEEE Trans, on Components， Packaging，and Manufacturing Technology 之文獻 “High density multilayer printed circuit board for HITAC M-880” 。 雙面電路板製作方法通常包括下料、鑽孔、孔金屬化、 & 製作導電線路、貼阻焊膜、檢驗、包裝等製程。下料係指 將雙面覆銅板原料裁切成便於生產之適當尺寸。鑽孔係指 以雷射、機械、電漿等方法於雙面覆銅板上形成過孔。’孔 金屬化係指於過孔孔壁形成鍍銅層從而導通雙面銅箔之過 程。孔金屬化後即可將雙面銅箔製成設計之導電線路，並 於導電線路表面貼覆阻焊膜。最後進行電性導通、阻抗測 試及熱衝擊耐受性等試驗，檢驗合格後即可將產品包裝出 貨。 製作多層電路板時，可先將複數單面電路板或雙面電 ❹ ❹ 200930199 路板進行壓合，形成已製作内層導電線路、尚未製作外層 導電線路之多層基板，然後再同樣進行鑽孔、孔金屬化、 製作外層導電線路、貼阻焊膜、檢驗、包裝等製程，從而 完成多層電路板之製作。 雙面電路板與多層電路板之製程中，孔金屬化均為使 各層銅落或導電線路實現導通之重要工序。孔金屬化包括 化學沈銅工序與電鑛銅工序。化學沈銅係指利用自催化氧 化還原反應機理於基體表面沈積化學銅層之技術。電鑛銅 係指利用外界直流電仙’於溶液巾進行電解反應從而使 導電體表面沈積上銅層之過程。電路板製程中，為降低生 產成本，通f先以化學沈純躲過孔㈣沈積上極薄化 學鑛銅層’然後相電賴技術純學軸層上沈積較厚 電鍍銅層’從而以較低成本獲得需要厚度之孔壁銅層。然 而’當以化學沈銅技術於過孔孔壁沈積上化學鍛銅層時”，、 不可避免地亦會於雙面覆銅板表面或多層基板表面沈積上 化干鑛銅^ ϋ且，於其後之電鑛銅卫序時亦同樣於雙面 覆銅板表面或夕層基板表面之化學鐘銅層上沈積上電錢銅 層’使得雙面覆銅板表面或多層基板表面之銅箱厚度增 加，從而使得雙面覆銅板或多層基板經過後續導電線路製 2無法形成較細密輕薄之導電線路，從而無法製作出高 雄、度、細線路之電路板。 有鑑於此’有必要提供—錄雷牧4c也』 你制从古—由 種電路板製作方法，其可方 便製作间毯、度、細線路之電路板。 200930199 【發明内容】 以下將以實施例說明一種電路板製作方法。 :種電路板製作方法’包括以下步驟：提供—覆銅基 一八至）包括第一外部銅層、第二外部銅層及一位於第 U銅層與第二外部銅層間之樹脂層；於所述覆銅基材 上升/成至V過孔，於過孔孔壁、第一外部銅層及第二外 部銅層上形成鍍銅層；遮蔽過孔孔壁之鍵銅層，去除第一 ❺外相層上與第二外部銅層上之錢銅層；將第一外部銅層 與第二外部銅層均製成導電圖形。 本技術方案之電路板製作方法具有如下優點：首先， 其包括去除第-外部銅層、第二外部銅層上之鍵銅層之步 驟，使得第-外部銅層與第二外部銅層之厚度均較小，從 而可製成高密度、細線路之電路板；其次，減輕第一外部 銅層與第二外部銅層之重量’使得製成之電路板較為輕 薄’再次，對於柔性電路板來說，還可使得製成之電路板 ❹具有較好之撓性。 【實施方式】 下面將結合附圖及實施例，對本技術方案雷 板製作方法作進一步之詳細說明。 〃'、 本技術方案實施方式提供之電路板製作方法包括以下 步驟： 第一步，提供一覆銅基材，其包括至少二外部銅層及 至少一樹脂層。 所述覆銅基材可為雙面覆銅基板，亦可為已完成内部 200930199 線路製作、尚未進行外部表面線路製作之三層及三層以 之多層基板。請參閱圖1，本實施例中，覆銅基材 面覆銅基板’其包括第一外部銅層11、第二外部銅層 位於苐一外部銅層11與第二外部銅層12間之樹脂層1) -'-Ο 〇 所述第一外部銅層11、第二外部銅層12可為壓延鋼n亦了 為電解銅箔，優選為具有較好可撓性之壓延銅箔。所迷樹 脂層13可為硬性樹脂層，如環氧樹脂、玻纖布等，亦可索 性樹脂層’如聚酿亞胺（Polyimide, ΡΙ)、聚乙烯對苯二甲 ❹酸乙二醇醋（Polyethylene Terephtalate, PET)、聚四氧乙婦 (Teflon)、聚硫胺（p〇iyaniide)、聚曱基丙烯酸甲酯（p〇iy_ methylmethacrylate)、聚碳酸 g旨（Polycarbonate)或聚醯亞胺_ 聚乙烯-對苯二曱g旨共聚物（Polyamide Polyethylene-terephthalate Copolymer)等。 另外，第一外部銅層11、第二外部銅層12與樹脂層 13之間還可具有黏膠層，以使得第一外部銅層11、第二外 ❹部銅層12與樹脂層13之間具有較好黏結性能。 優選地，為便於製作較輕薄之細線路電路板，所述第 一外部銅層11、第二外部銅層12之厚度可小於12微米。 第二步，鑽孔以於所述覆銅基材10上形成至少一過孔 101 ° 所述覆銅基材10可以具有一個或複數個過孔1〇1，所 述過孔101係指至少貫穿二銅層與一樹脂層之通孔或盲 孔。過孔101之形狀、位置視電路板之設計需求而定。本 實施例中，覆銅基材10具有一過孔101，其為貫穿第一外 200930199 部銅層11、樹脂層13及第二外部銅層12之圓形通孔。 第二步’於過孔101孔壁、第一外部銅層11及第二外 部銅層12上形成鍍銅層20。 電路板製作中，通常將為導通各銅層而於過孔孔壁形 成鍍銅層之工序稱為孔金屬化製程。孔金屬化製程至少包 括化學鍍銅工序，依具體鍍銅層厚度需要，還可包括電鍍 銅工序。 ❹ 化學鍍銅工序通常包括清洗、粗化、預浸、活化及沈 銅等步驟。具體地，首先以鹼液清洗覆銅基材1Q ,去除覆 銅基材10表面之油污及灰塵。其次，以過氧水-硫酸體系粗 化覆銅基材ίο之第一外部銅層η、第二外部銅層12以及 過孔ιοί之孔壁。再次，將覆銅基材1〇置於預浸液或敏化 液中，以預防覆銅基材10帶入雜質，並潤濕過孔1〇1之孔 壁預/5：後進行活化，使貴金屬催化劑均勻吸附於第一外 4銅層11、第一外部銅層12以及過孔ιοί之孔壁，形成化 ❾子沈銅所需之活化中心。最後即可將覆銅基材放置於化 學鍍銅液中，使得化學鍍銅液中之金屬銅鹽與還原劑於具 有催化/舌性之苐一外部銅層11、第二外部銅層1 2以及過孔 〇 1之孔壁上進行自催化氧化還原反應’並於第一外部銅層 11、第二外部銅層12表面以及過孔101之孔壁上形成具有 一疋厚度之化學鍍銅層21，如圖3所示。 化學鑛銅層21通常較薄，其厚度一般為0.1〜3微米之 門工業上為確保孔壁銅層之連續性與可靠性，於化學鑛 ’s灸還了進行電鑛銅工序。即，將覆銅基材10放置於電鑛 200930199 槽令以覆銅基材1G為陰極，以銅棒或銅板做陽極，以含 有銅鹽之電解質溶液作為電鍵液，接通直流電源即可 艘液中發生電解反應，從而於覆銅基材1G之導電表面沈積 上電鑛銅層22,即，於孔壁之化學鐘銅層21上鑛上_ 度之電鑛銅層22,如圖4所示。電鑛銅層22之厚度可依且 體電路板之設計需求而定，_般可為5〜3()微米之間。… 優選地為減少電鑛液耗量，可以光阻覆蓋第一外部 銅層11貞第二外部銅層12，使得電錢銅時不於第一外部銅 層11、第二外部銅I 12之化學鏡銅層21上沈積電鍍銅層 22而僅於孔壁之化學鐘銅層21上沈積電鍛銅層η。 經過如上所述製程，即可於過孔101之孔壁上形成包 括化學鏡銅層21與電鑛銅層22之鑛銅層20，鐘銅層2〇 可導通第-外部銅層1：L與第二外部銅層12。 第四步，遮蔽過孔1〇1孔壁之鍍銅層2〇，去除第一外 部銅層1/、第二外部銅層12上之鑛銅層2〇。 ❽_遮蔽過孔1〇1孔壁之錢銅層20後，以銅钱刻液钕刻覆 銅基材1〇時，過孔101孔壁之鍵銅層20即可受到保護而 不被侵姓，第一外部銅層u、第二外部銅層12上之錢銅層 2〇則可被蝕刻去除。從而，可除去第一外部銅層u上與第 二外部銅層12上之錢銅層2〇，使得後續以第一外部銅層 lj第一外部銅層12製作出之導電圖形厚度較小、密度較 南、線路較細。 化所述銅蝕刻液可為硫酸-雙氧水、過硫酸銨-硫酸、過硫 I鈉/硫馱及過硫酸鉀/硫酸、氣化銅-硫酸等混合微蝕體 11 200930199 系’亦可為酸性氣化鋼蝕刻液或鹼性氯化銅蝕刻液等蝕刻 體系。所述銅触刻液餘刻鍍銅層2〇之速度跟銅蝕刻液之成 分、濃度、餘刻溫度、處理方法以及鍍銅層2〇之厚度均密 切相關。適當控制覆銅基材1〇之蝕刻速度以及蝕刻時間即 可恰好除去第-外部銅層u、第二外部銅層12上之鐘銅層 20。舉例來說’以會霧式處理法將硫酸_雙氧水系韻液於 38攝氏度ί哀境下以l3kg/m2之喷壓喷淋至走板速度為 2.lm/min之電路板表面時，微蝕速度約為，若第 外4銅層11、第—外部銅層12上之鍍銅層之厚度為 5以m，則大約蝕刻5分鐘即可除去第一外部銅層u、 外部銅層12上之鍍銅層2〇。 遮蔽過子L 101孔壁之鍍銅層2〇之方法可為以液態光阻 ^過孔1G1，亦可為直接於過孔皿孔周貼覆乾膜，並使 ^膜封閉過孔逝；亦可藉由圖像轉移法使得乾膜僅 T過孔搬孔周並封閉過孔如；當然，亦可藉由其他方法 ©遮蔽過孔101孔壁之鍍銅層20。 20之以以圖像轉移法為例，說明遮蔽孔壁之鍍銅層 々 種方法。f先，請參閱圖5，於第一外部銅居、 第二外部銅層12表面分別貼覆第一 、曰 所诚坌一护时。 乾膜31、第二乾膜32〇 光ί 二乾膜％可為正型光阻，亦可為負型 光阻為^ 中’僅以第—麵31、第二乾臈32為負型 先阻為例，說明其後之曝光顯 、孓 圖6,分別藉由第一#星41 / 序其:欠，請參閱 刀乃J猎由第一先罩41、第二光罩42對第— —乾膜32進行曝光。所述第— 、 ^ 弟一先罩42分 12 200930199 別具有第一開口 411、第二開口 421，所述第一開口 411、 第二開口 421之形狀、位置均與過孔101對應。並且，第 一開口 411、第二開口 4n之直徑D1為過孔ι〇ι之直徑d2 之2〜5倍’即’ ( 2〜5 ) D2。優選地，Dl= ( 3〜4) D2。 所述過孔101之直徑D2係指過孔1〇1之孔壁形成鍍銅層 20後之孔徑，而非為形成鍍銅層2〇前之孔徑。曝光時，與 第開口 411、第二開口 421對應之乾膜受到光線照射，發 生聚合反應，而未受光線照射之乾膜則 β以顯影液嘴淋第-乾膜31、第二乾膜32，發生聚合^應之 乾膜於顯影液中具有低溶解度，不被顯影液溶解；而未發 生刀解反應之乾膜則於顯影液中具有高溶解度，可被顯影 液溶解。因此，經過顯影工序後，請參閱圖7，第一乾膜 31於與第-開口 411對應區域之乾膜不被溶解，第二乾膜 7於與第二開口 421對應區域之乾膜亦不被溶解，從而使 侍該。卩为乾膜封閉過孔1〇1，並遮蔽過孔1〇1孔周之部分銅 ❹層。並且，該部分乾膜之直徑D3亦為過孔ι〇ι之直徑D2 之2〜5倍，該部分乾膜之中心軸與過孔ι〇ι之中心軸重合。 同叶其餘部分之乾膜均被溶解，即，裸露出第—外部銅 層11、第二外部銅層12上之鐘銅層20。從而，將覆銅基 材1〇浸置於遍m切純刻时淋覆銅基材1〇以姓 刻覆銅基材10時，第一外部銅層U、第二外部銅層12上 之鏡銅層2G可被*刻去除’而過孔1Q1孔壁 則不被蝕刻，如圖8所示。 ㈣覆銅基材1G | ’可將分別殘留於第—外部銅層 13 200930199 2、第二外部銅層12上之第一乾膜31、第二乾膜32除去， 圖9所不。當然，該些殘留之乾膜亦可暫時留置，直至 ^第外銅層u、第二外部銅層12製成導電圖形後再 去0 另外，如果第一外部銅層u、第二外部銅層Η之厚产 t於12微米’於除去第—外部銅層11、第二外部銅層Γ2 =之:又銅層20後’還可進一步以銅關液將第一外部銅層 ❹ ❹ 剪作! 銅層12之厚度_至12微WF，以使得 I作士之電路板之導電圖形具有較小厚度。 電圖^五步’將第-外部銅層U、第二外部銅層12製成導200930199 • Nine, invention description: • Technical field of the invention The present invention relates to the field of circuit board technology, and in particular to a method of manufacturing a circuit board. [Prior Art] With the development of electronic products in the direction of miniaturization and high speed, circuit boards have also evolved from single-sided boards to double-sided boards and even multilayer boards. A double-sided circuit board is a circuit board in which conductive lines are distributed on both sides. Multilayer Circuit A slab is a circuit board having three or more layers of conductive lines laminated by a plurality of single-sided boards or double-sided boards. Since the double-sided circuit board and the multi-layer circuit board have a large number of wiring areas and are widely used, please refer to the article "High Density Layer printed" by Takahashi, A. et al., IEEE Trans, on Components, Packaging, and Manufacturing Technology, 1992. Circuit board for HITAC M-880”. Double-sided circuit board manufacturing methods usually include blanking, drilling, hole metallization, & fabrication of conductive traces, solder mask, inspection, packaging and other processes. Unloading means cutting the double-sided copper clad material into appropriate sizes for easy production. Drilling refers to the formation of vias on double-sided copper clad laminates by laser, mechanical, plasma, etc. The term "hole metallization" refers to the process of forming a copper plating layer on the wall of the via hole to conduct the double-sided copper foil. After the hole is metallized, the double-sided copper foil can be made into a designed conductive line, and the solder resist film is attached to the surface of the conductive line. Finally, electrical conduction, impedance test and thermal shock resistance test are carried out. After passing the test, the product can be packaged for delivery. When making a multi-layer circuit board, a plurality of single-sided circuit boards or double-sided electric ❹ ❹ 200930199 board can be pressed together to form a multi-layer substrate on which an inner conductive line has been fabricated, and an outer conductive line has not been formed, and then drilled, The metallization of the hole, the production of the outer conductive circuit, the solder resist film, the inspection, the packaging, and the like, thereby completing the fabrication of the multilayer circuit board. In the process of double-sided circuit board and multi-layer circuit board, hole metallization is an important process to make each layer of copper or conductive lines conductive. Hole metallization includes a chemical copper sinking process and an electric copper ore process. Electroless copper is a technique for depositing a chemical copper layer on the surface of a substrate by an autocatalytic oxidation reduction mechanism. Electro-mineral copper refers to the process of depositing a copper layer on the surface of an electric conductor by utilizing an external DC electric current to perform an electrolytic reaction on a solution towel. In the process of circuit board, in order to reduce the production cost, the first layer of chemically pure copper layer is deposited by chemical deposition, and the thick copper plating layer is deposited on the purely axial layer. Low cost copper layers of the desired thickness are obtained. However, when the chemical forging copper layer is deposited on the via hole wall by the chemical copper sinking technique, it is inevitable that the surface of the double-sided copper clad laminate or the surface of the multi-layer substrate is deposited with a dry copper ore. In the latter case, the electric copper layer is also deposited on the surface of the double-sided copper clad plate or the chemical clock copper layer on the surface of the matte substrate, so that the thickness of the copper box on the surface of the double-sided clad laminate or the surface of the multi-layer substrate is increased. Therefore, the double-sided copper clad laminate or the multi-layer substrate can not form a thin and light conductive line through the subsequent conductive circuit 2, so that the circuit board of the Kaohsiung, the degree, and the thin line cannot be produced. In view of this, it is necessary to provide the recording of the Leimu 4c. Also, you have made a circuit board manufacturing method, which can easily produce a circuit board of a blanket, a degree, and a thin line. 200930199 [Summary of the Invention] Hereinafter, a circuit board manufacturing method will be described by way of an embodiment. The manufacturing method includes the following steps: providing a copper-clad substrate VIII to include a first outer copper layer, a second outer copper layer, and a resin layer between the U-th copper layer and the second outer copper layer; The copper substrate is raised/formed into a V via, and a copper plating layer is formed on the via hole wall, the first outer copper layer and the second outer copper layer; the key copper layer of the via hole is shielded to remove the first layer a copper layer on the outer layer and the second outer copper layer; the first outer copper layer and the second outer copper layer are both made into a conductive pattern. The circuit board manufacturing method of the technical solution has the following advantages: First, it includes removing a step of bonding the copper layer on the first outer copper layer and the second outer copper layer such that the thickness of the first outer copper layer and the second outer copper layer are both small, so that a high density, thin circuit circuit board can be formed; Secondly, the weight of the first outer copper layer and the second outer copper layer is reduced to make the fabricated circuit board lighter and thinner. Again, for the flexible circuit board, the manufactured circuit board can be made to have better flexibility. [Embodiment] Hereinafter, a method for manufacturing a lightning plate of the present technical solution will be further described in detail with reference to the accompanying drawings and embodiments. The method for manufacturing a circuit board provided by the embodiment of the present technical solution includes the following steps: Copper-clad The material comprises at least two outer copper layers and at least one resin layer. The copper-clad substrate may be a double-sided copper-clad substrate, or may be three layers and three layers that have been fabricated in the inner 200930199 circuit and have not been subjected to external surface wiring. The multilayer substrate is layered. Referring to FIG. 1 , in this embodiment, the copper-clad substrate surface-clad copper substrate includes a first outer copper layer 11 and a second outer copper layer on the outer copper layer 11 and the second outer layer. The resin layer 1) between the copper layers 12) - '- Ο 〇 the first outer copper layer 11 and the second outer copper layer 12 may be rolled steel n or electrolytic copper foil, preferably having good flexibility. The resin layer 13 may be a hard resin layer such as an epoxy resin, a fiberglass cloth, or the like, or a resin layer such as polyimide (polyimide) or polyethylene terephthalic acid. Polyethylene Terephtalate (PET), Teflon, p〇iyaniide, p〇iy_methylmethacrylate, Polycarbonate or Polyimine _ polyethylene-p-benzoquinone g-copolymer (Polyamide Polyethylene-t Erephthalate Copolymer). In addition, an adhesive layer may be further disposed between the first outer copper layer 11 and the second outer copper layer 12 and the resin layer 13 such that the first outer copper layer 11, the second outer copper layer 12 and the resin layer 13 It has good bonding properties. Preferably, the thickness of the first outer copper layer 11 and the second outer copper layer 12 may be less than 12 micrometers in order to facilitate the fabrication of a thinner and thinner circuit board. In the second step, the hole is formed on the copper-clad substrate 10 to form at least one via 101°. The copper-clad substrate 10 may have one or more vias 1〇1, and the via 101 means at least A through hole or a blind hole penetrating the two copper layers and a resin layer. The shape and position of the via 101 depends on the design requirements of the board. In the present embodiment, the copper clad base material 10 has a through hole 101 which is a circular through hole penetrating through the first outer layer 200930199, the copper layer 11, the resin layer 13, and the second outer copper layer 12. In the second step, a copper plating layer 20 is formed on the via 101 wall, the first outer copper layer 11, and the second outer copper layer 12. In the fabrication of a circuit board, a process of forming a copper plating layer on the walls of the via holes by conducting a copper layer is generally referred to as a hole metallization process. The hole metallization process includes at least an electroless copper plating process, and may include a copper plating process depending on the thickness of the specific copper plating layer. ❹ The electroless copper plating process usually includes steps such as cleaning, roughening, prepreg, activation, and copper plating. Specifically, the copper-clad substrate 1Q is first washed with an alkali solution to remove oil stains and dust on the surface of the copper-clad substrate 10. Next, the first outer copper layer η, the second outer copper layer 12, and the via walls of the via ιοί are roughened by a peroxyhydrate-sulfuric acid system. Again, the copper-clad substrate 1〇 is placed in the pre-dip solution or the sensitizing solution to prevent the copper-clad substrate 10 from being contaminated, and the pore wall of the via hole 1〇1 is wetted for a predetermined period of 5: The precious metal catalyst is uniformly adsorbed on the first outer copper layer 11, the first outer copper layer 12, and the pore walls of the via ιοί to form an activation center required for the scorpion to sink copper. Finally, the copper-clad substrate can be placed in the electroless copper plating solution, so that the metal copper salt and the reducing agent in the electroless copper plating solution have an external copper layer 11 and a second outer copper layer 12 having catalytic/tongue properties. And performing an autocatalytic redox reaction on the wall of the via hole 1 and forming an electroless copper plating layer 21 having a thickness on the first outer copper layer 11, the surface of the second outer copper layer 12, and the hole wall of the via 101. ,As shown in Figure 3. The chemical ore layer 21 is generally thin, and its thickness is generally 0.1 to 3 μm. In order to ensure the continuity and reliability of the copper layer of the hole wall, the chemical ore is also subjected to the electro-mineralization process. That is, the copper-clad substrate 10 is placed in the electric ore 200930199 groove so that the copper-clad substrate 1G is used as the cathode, the copper rod or the copper plate is used as the anode, and the electrolyte solution containing the copper salt is used as the electric-key liquid, and the DC power source can be connected. An electrolytic reaction occurs in the liquid to deposit a copper ore layer 22 on the conductive surface of the copper-clad substrate 1G, that is, an electro-copper layer 22 on the chemical clock copper layer 21 of the pore wall, as shown in FIG. Shown. The thickness of the electrowinning copper layer 22 may depend on the design requirements of the bulk circuit board, and may be between 5 and 3 (micrometers). Preferably, in order to reduce the consumption of the electro-mineral liquid, the first outer copper layer 11 and the second outer copper layer 12 may be covered by the photoresist so that the electric copper is not in the first outer copper layer 11 and the second outer copper layer 12 An electroplated copper layer 22 is deposited on the chemical mirror copper layer 21 and an electrically forged copper layer η is deposited only on the chemical clock copper layer 21 of the pore walls. After the process as described above, a copper ore layer 20 including a chemical mirror copper layer 21 and an electric ore copper layer 22 can be formed on the wall of the via 101, and the copper layer 2 can conduct the first-outer copper layer 1: L And a second outer copper layer 12. In the fourth step, the copper plating layer 2 of the via hole 1 〇 1 hole is shielded, and the first outer copper layer 1/ and the second outer copper layer 12 are removed. ❽ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The last name, the first outer copper layer u, and the second copper layer 2 on the second outer copper layer 12 can be removed by etching. Therefore, the copper layer 2 on the first outer copper layer u and the second outer copper layer 12 can be removed, so that the conductive pattern formed by the first outer copper layer 12 of the first outer copper layer 1j is small, The density is souther and the line is thinner. The copper etching solution may be a mixed micro-etched body such as sulfuric acid-hydrogen peroxide, ammonium persulfate-sulfuric acid, sodium persulfate/sulfurium, potassium persulfate/sulfuric acid, vaporized copper-sulfuric acid, etc. 200930199 An etching system such as a vaporized steel etching solution or an alkaline copper chloride etching solution. The speed of the copper-plated copper layer 2 〇 is closely related to the composition, concentration, residual temperature, treatment method, and thickness of the copper plating layer 2 of the copper etching solution. The copper layer 20 on the first outer copper layer u and the second outer copper layer 12 can be removed just by appropriately controlling the etching rate and etching time of the copper clad substrate. For example, when the spray of sulfuric acid-hydrogen peroxide solution is sprayed at a pressure of l3kg/m2 at a temperature of 38 degrees Celsius to a surface of a board with a running speed of 2.lm/min. The etching rate is about 5. If the thickness of the copper plating layer on the outer 4th copper layer 11 and the first outer copper layer 12 is 5 m, the first outer copper layer u and the outer copper layer 12 can be removed by etching for about 5 minutes. The copper plating layer on the 2 〇. The method of shielding the copper plating layer 2 of the hole of the hole L 101 may be a liquid photoresist 1G1, or a dry film may be applied directly to the hole of the via hole, and the film may be closed; The image transfer method can also be used to make the dry film only pass through the hole and close the via hole. For example, the copper plating layer 20 of the hole wall of the via hole 101 can be shielded by other methods. 20 is to take the image transfer method as an example to illustrate the method of shielding the copper plating layer of the hole wall. f First, please refer to Figure 5, when the first outer copper and the second outer copper layer 12 are respectively attached to the surface of the first and second sides. Dry film 31, second dry film 32 ί ί 二 干 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 % % % % % % % % % % % % % % % % The resistance is taken as an example to illustrate the subsequent exposure display, Figure 6, respectively, by the first #星41 / preface: owe, please refer to the knife is the first hood 41, the second mask 42 pairs - - Dry film 32 is exposed. The first opening and the second opening 421 have a first opening 411 and a second opening 421. The shapes and positions of the first opening 411 and the second opening 421 correspond to the through holes 101. Further, the diameter D1 of the first opening 411 and the second opening 4n is 2 to 5 times of the diameter d2 of the via ι ’, i.e., '(2 to 5) D2. Preferably, Dl = (3~4) D2. The diameter D2 of the via 101 refers to the aperture formed by the hole wall of the via hole 1〇1 to form the copper plating layer 20, not the aperture before the copper plating layer 2 is formed. During exposure, the dry film corresponding to the first opening 411 and the second opening 421 is irradiated with light to cause a polymerization reaction, and the dry film not irradiated with the light is then sprayed onto the first dry film 31 and the second dry film 32 by the developing liquid nozzle. The dry film which is polymerized has a low solubility in the developer and is not dissolved by the developer; and the dry film which does not undergo the knife solution has high solubility in the developer and can be dissolved by the developer. Therefore, after the development process, referring to FIG. 7, the dry film of the first dry film 31 in the region corresponding to the first opening 411 is not dissolved, and the dry film of the second dry film 7 in the region corresponding to the second opening 421 is not It is dissolved so that it can be served.卩The dry film closes the via 1〇1 and shields the copper layer of the via of the 1〇1 hole. Moreover, the diameter D3 of the portion of the dry film is also 2 to 5 times the diameter D2 of the via ι〇ι, and the central axis of the portion of the dry film coincides with the central axis of the via ι〇ι. The dry film of the rest of the same leaf is dissolved, i.e., the copper layer 20 on the first outer copper layer 11 and the second outer copper layer 12 is exposed. Therefore, when the copper-clad substrate 1 is immersed in the copper substrate 1 when the copper substrate is pasted, the first outer copper layer U and the second outer copper layer 12 are The mirror copper layer 2G can be removed* and the via 1Q1 hole walls are not etched, as shown in FIG. (4) The copper-clad substrate 1G | ' can be removed from the first outer film 31 and the second dry film 32 remaining on the first outer copper layer 13 200930199 2, the second outer copper layer 12, as shown in Fig. 9. Of course, the residual dry film may be temporarily left until the outer copper layer u and the second outer copper layer 12 are made into a conductive pattern and then go to 0. In addition, if the first outer copper layer u and the second outer copper layer The thicker t of the crucible is at 12 micron 'after removing the first outer copper layer 11, the second outer copper layer Γ2 =: after the copper layer 20', the first outer copper layer ❹ can be further cut with a copper liquid The thickness of the copper layer 12 is _ to 12 micro WF, so that the conductive pattern of the circuit board of the Ishishi has a small thickness. Electrogram ^ five steps 'conducting the first outer copper layer U and the second outer copper layer 12
-般地，先藉由圖像轉移法於第一外部銅層U 二上成相應光阻圖案，再經由化學藥液儀刻或 :=法將第-外部銅層-第二外部銅層峨Generally, the first external copper layer U is first formed into a corresponding photoresist pattern by image transfer method, and then the first outer copper layer and the second outer copper layer are etched by chemical liquid etching or := method.
请參閱圖10’首先，於第一外部銅層η 層12表面分別形成第一 ^ J 中’所述第-_ 51、第：光二光Γ/2 °本實施例 亦可為負型光阻。其次，枝灸間.、’、正^光阻’當然’其 6!、第四光罩62對第一光;:=二？藉由第三光^ 經過光線照射之触發生 —1且52進订曝光’ 則不發生反應。所述第三=應，未經光線照射之光阻 之導電圖形相對應之圖宰，f 2 =罩62具有與設計 光阻Μ上亦具有相應之圖Π光後將第；^二51、第二 m 丹次’將覆銅基材10浸置 14 200930199 於顯影液中時，路&八c & , 之部八第-L 光阻被溶解，裸露出並下 第外邛銅層11與部分之第二外部銅層12， 生^應之綠心被轉，絲著於第 而1 5==12之表面，如圖12所示。即，二層第= "阻52形成與設計導電圖形相同之圖案。再、 ❹ ❹ 罐除，而其餘部分之==銅:刻::= 2則被光_護而不麵如圖13所示：:π 第二霧雪^ 圖形lla，將第二外部銅層12製成 仙^ 最後’請參關14,將殘留於第一外 部銅層！1、第二外部銅層12 、第外 去，即可得到已—占道發 未發生反應之光阻除 厚产之雜而堂々Γ 製作之具有較細線路、較薄 厚度之雙面電路基板10a。 权碑 將覆銅基材1〇製成雙面電路基板施 檢驗、包裝等工序，從而製作出一= 電路AΜ字Μ又面電路基板10a與其他雙面 電路基板或早面覆銅板等麼合 ΓΤ路板時，同樣可運用本===:密 度、細線路之多層電路板。 山 盆之電路板製作方法具有如下優點：首先， 驟，使得ί一外IS銅層：第二外部銅層上之鐘銅層之步 可製成古广♦ °層、第二外部銅層之厚度較小，從而 翁度、細線路之電路板；其次，減輕第-外部銅 15 200930199 蟪 層、第二外部銅層之重量，使得製成之電路板較為輕薄； '再次，對於柔性電路板來說，還可使得製成之電路板具有 較好撓性。 綜上所述，本發明確已符合發明專利之要件，遂依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限制本案之申請專利範圍。舉凡熟悉本案 技藝之人士援依本發明之精神所作之等效修飾或變化，皆 應涵蓋於以下申請專利範圍内。 ❹【圖式簡單說明】 圖1係本技術方案實施方式提供之覆銅基材之示意圖。 圖2係本技術方案實施方式提供之於覆銅基材上形成 過孔之示意圖。 圖3係本技術方案實施方式提供之覆銅基材上沈積化 學艘銅層之示意圖。 圖4係本技術方案實施方式提供之於覆銅基材之化學 0銅層上沈積電鍍銅層之示意圖。 圖5係本技術方案實施方式提供之覆銅基材之銅箱表 面貼覆乾膜之示意圖。 圖6係本技術方案實施方式提供之覆銅基材之銅箔表 面貼覆乾膜後曝光之示意圖。 圖7係本技術方案實施方式提供之覆銅基材之銅箔表 面貼覆乾膜、曝光、顯影後之示意圖。 圖8係本技術方案實施方式提供之去除覆銅基材銅箔 表面之嫂銅層後之示意圖。 16 200930199 圖9係本技術方案實施方式提供之去除覆銅基材乾膜 後之示意圖。 圖10係本技術方案實施方式提供之於覆銅基材銅箱表 面形成光阻之示意圖。 圖11係本技術方案實施方式提供之於覆銅基材銅箔表 面形成光阻後曝光之示意圖。 圖12係本技術方案實施方式提供之於覆銅基材銅镇表 面形成光阻、曝光、顯影後之示意圖。 ® 圖13係本技術方案實施方式提供之將覆銅基材銅箔蝕 刻成導電圖形後之示意圖。 圖14係本技術方案實施方式提供之去除覆銅基材之光 阻後之示意圖。 【主要元件符號說明】 覆銅基材 10 第一外部銅層 11 第二外部銅層 12 樹脂層 13 過孔 101 鐘銅層 20 化學锻銅層 21 電鍍銅層 22 第一乾膜 31 第二乾膜 32 第一光罩 41 第二光罩 42 第一開口 411 第二開口 421 第一光阻 51 第二光阻 52 第三光罩 61 第四光罩 62 第一導電圖形 11a 第二導電圖形 12a 雙面電路基板l〇a 17Referring to FIG. 10', first, the first - _ 51, the second light /2 / 2 is formed on the surface of the first outer copper layer η layer 12, and the embodiment may also be a negative photoresist. . Secondly, between the moxibustion, the ', the positive ^ photoresist' of course, its 6!, the fourth mask 62 to the first light;: = two? No reaction occurs when the third light passes through the touch of the light -1 and 52 sets the exposure. The third=should, the conductive pattern corresponding to the light-resistance of the light-resistance is corresponding to the figure, and f2=the cover 62 has a corresponding pattern on the design of the photoresist Π, and then the first; When the second m-dan is immersed in the copper-clad substrate 10 for 14 200930199 in the developing solution, the road & eight c &, the eighth-l-resistance is dissolved, and the outer outer copper layer is exposed. 11 and a portion of the second outer copper layer 12, the green core of the raw material is turned, and the surface is on the surface of the first 15 == 12, as shown in FIG. That is, the second layer = " resistance 52 forms the same pattern as the design conductive pattern. Then, ❹ 罐 can be removed, and the rest of the == copper: engraved::= 2 is protected by light _ no face as shown in Figure 13:: π second fog snow ^ graphic lla, the second outer copper layer 12 made into a fairy ^ Finally 'please participate in the 14th, will remain in the first outer copper layer! 1. The second outer copper layer 12 and the outer layer can be obtained, and the double-sided circuit substrate having the thinner line and the thinner thickness can be obtained. 10a. The company will manufacture a double-sided circuit board for inspection and packaging, and produce a circuit A. The circuit board 10a is combined with other double-sided circuit boards or early copper-clad boards. When using the circuit board, you can also use this ===: multilayer circuit board with density and fine lines. The manufacturing method of the circuit board of the mountain basin has the following advantages: firstly, the outer copper layer of the IS: the copper layer on the second outer copper layer can be made into the ancient layer ♦ ° layer and the second outer copper layer The board has a small thickness, so that the length and the thin circuit board; secondly, the weight of the first outer copper 15 200930199 layer and the second outer copper layer is lightened, so that the manufactured circuit board is light and thin; 'again, for the flexible circuit board In this case, the fabricated circuit board can also be made to have better flexibility. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the present invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a copper-clad substrate provided by an embodiment of the present technical solution. 2 is a schematic view showing a via hole formed on a copper-clad substrate according to an embodiment of the present technical solution. 3 is a schematic view showing the deposition of a chemical copper layer on a copper-clad substrate provided by an embodiment of the present technical solution. 4 is a schematic view showing deposition of an electroplated copper layer on a chemical 0 copper layer of a copper-clad substrate provided by an embodiment of the present technical solution. Fig. 5 is a schematic view showing the surface of a copper case of a copper-clad substrate provided by an embodiment of the present invention. Fig. 6 is a schematic view showing the exposure of the copper foil surface of the copper-clad substrate provided by the embodiment of the present invention to the dry film after exposure. Fig. 7 is a schematic view showing the surface of the copper foil of the copper-clad substrate provided by the embodiment of the present invention after the dry film is attached, exposed, and developed. Fig. 8 is a schematic view showing the copper layer on the surface of the copper foil of the copper-clad substrate removed by the embodiment of the present invention. 16 200930199 FIG. 9 is a schematic view showing the removal of a dry film of a copper-clad substrate provided by an embodiment of the present technical solution. Fig. 10 is a schematic view showing the formation of photoresist on the surface of a copper-clad substrate copper case provided by an embodiment of the present invention. Fig. 11 is a schematic view showing the exposure of the surface of the copper-clad substrate copper foil after the photoresist is formed by the embodiment of the present invention. Fig. 12 is a schematic view showing the formation of photoresist, exposure and development of the copper-coated surface of the copper-clad substrate provided by the embodiment of the present invention. ® Figure 13 is a schematic illustration of a copper-clad substrate copper foil etched into a conductive pattern provided by an embodiment of the present technical solution. Fig. 14 is a schematic view showing the photoresist removal of the copper-clad substrate provided by the embodiment of the present invention. [Description of main components] Copper-clad substrate 10 First outer copper layer 11 Second outer copper layer 12 Resin layer 13 Via 101 Bell copper layer 20 Chemical forged copper layer 21 Electroplated copper layer 22 First dry film 31 Second dry Film 32 first mask 41 second mask 42 first opening 411 second opening 421 first photoresist 51 second photoresist 52 third mask 61 fourth mask 62 first conductive pattern 11a second conductive pattern 12a Double-sided circuit board l〇a 17