SU1594687A1 - A-d converter - Google Patents

Abstract

The invention relates to computing and can be used to convert analog values to digital, as well as digital signal processing and, in addition, to obtain digital information about the location of an object in a two-dimensional coordinate system. The invention makes it possible to extend the functionality by converting an analog signal into a code with a base √2 and controlling the accuracy of the conversion. This is achieved by introducing scaling operational amplifiers 1, 2, 3, analog-to-digital converter 5, switches 7, 8, register 9, block 6 of code comparison in the device containing the source 10 of the reference voltage, analog-digital converter 4. 1 il.

Description

ate

with

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O5 00

The invention relates to computing and can be used to convert analog values to digital, as well as to digital signal processing, in addition, to obtain digital information about the location of an object in a two-dimensional coordinate system.

The purpose of the invention is to enhance the functionality by converting an analog signal into a code with a base 2 and monitoring the conversion correctness.

The drawing shows a block diagram of the device.

The device contains scalable operational amplifiers 1-3, analog-to-digital converters (ADC) 4 and 5 parallel conversions, block 6 comparison of codes, switches 7 and 8.

register 9, source 10 reference eg

input busses 1–13, 14 tat pulse bus, control buses 15 and 16, control bus 17.

Scaling amplifiers 1-3 have two transmission coefficients, depending on the mode of operation of the device. To convert the input signal and in. binary code each of the three scaled 1x op-amps has a gain of one, In the case of converting the input signal U VK to a digital signal

with base 42, scaling amplifier 1 has a gain

G „

 the second is - and transform1 + l121 +

input voltage ADC 4 - .. 1. ,, d „П 3 - D ..-- C.Ma stacking amplifier 3 has a coefficient (}) of transfer 2 and converts the reference voltage U for the second ADC 5 into U.

Block 6 monitors the correctness of the conversion. The occurrence of a single signal at the output of block 6 indicates the occurrence of errors in the conversion.

Switches 7 and 8 allow, depending on the conversion mode, to generate digital signals to the register 9. In the case of converting the input signal to the binary code, the switch 7 provides connection of the generated ADC 4 code to the first

Yu

five

20

25

thirty

40

ds

five

from 1 to p input register bits, and switch 8 are the codes generated by ADC 5 to the second from n + to 2p register bits.

In the input-to-code-to-code conversion mode, the switch 7 connects the A / D converter 4 to the even bits of register 9, and the switch 8 connects the A / D converter 5 to the odd bits of it.

The device can operate in two modes: in the mode of converting an analog value into a code with an irrational base 4 and in the mode of simultaneous conversion of two independent (including one) analog values into two binary codes, respectively.

The device in the first mode works as follows.

The conversion is preceded by the initial state setting, in which the input inputs of the scaling amplifiers 1 and 2 are supplied with the input voltage U, and their second inputs are connected to the common point of the device circuit, the transfer ratio of the scaled amplifiers has the values:

the first is pr, the second is

1 + 42 + {1

and the third is nfi, single signals are sent to the control buses 15 and 16 of the switches 7 and 8, the register 9 is reset.

On the first pulse, which arrives on the bus 14 clock pulses in the ADC 4, the comparison is the same Ufcx

neither --- with reference voltage U I + s2o

and simultaneous comparison

- | 2 ADC 5 voltage UB, -.- from .g 1 H2 by pin Uo 2.

In the second cycle, the decoders of the first 4 and second 5 ADCs convert the words obtained at the outputs of the comparison circuits into even and odd bits of a code with -h2, respectively, which are then written into the output registers of each ADC in the third clock cycle. Thus, at the output of the first ADC 4, even bits of the code are formed, and at the output of ADC 5, odd bits. The final formation of a single 2-bit code with an irrational base -Jz is carried out by

ten

zero signal to bus 15 of switches 7 and 8, which organize the connection of even and odd n-bits of code 2 from the A / D converters to the corresponding inputs of register 9 with subsequent recording.

Block 6 monitors the accuracy of the conversion — a unit at the output of the circuit signals an error in the conversion.

The second mode of operation of the device for analogue-1F conversion is characterized in that in the initial state, the first inputs of the first I and second 2 scaling amplifiers are connected to a common point of the circuit, and the second inputs are supplied with independent input voltages, respectively U.

cvl

and the transmission coefficients of each of the three scaling amplifiers are one; a zero signal is applied to the control bus 15.

By the first clock pulse input-, ..., „..,.„

stresses Ug ,, and Ug. 25 scaling operational amplitudes are compared, y, l. „ monitors.

Claims (1)

5 claims An analog-to-digital conversion device comprising a first analog-to-digital converter and a source of reference voltage, the output of which is connected to the first input of the first analog-digital conversion of bodies, the second input of which is a clock pulse bus, characterized in that possibilities by creating an additional possibility of converting the analogue value into a code with an irrational basis / 2 and controlling the correctness of the transformation, a code comparison block, register mp, two switches, a second analog-to-digital converter, the first, second and third 15 20 with voltage "U" in the comparison circuits, respectively, of the first 4 and second 5 ADC. During the second clock cycle, in each ADC, the word obtained at the outputs of the comparison circuits is deciphered, and then the third clock writes to the output registers of the ADC N1- and N2 n-bit binary codes: in the first ADC 4-code, appropriately the first input voltage Ug, in the second ADC 5 - the code corresponding to the voltage Ug,. Due to the application of a zero signal to the busbar 15, using switches 7 and 8, the output code N1 is recorded in the lower ones from one to n bits, and the code V 2 in the older ones from n + 1 to 2p bits of the register 9 for analog-digital transform. Compared with the known, the proposed device has wider functionality due to the fact that the device is capable of converting the voltage into a digital value represented by a PCK binary n-bit code, as well as a 2n-bit code with a V2 base, as well as convert simultaneously two voltage Ug, and 8xz two N1 and N2 n-bit binary codes, in addition, has the ability to detect an error of 35 40 Respectively to the third input of the first analog-digital converter, jc to the first and second inputs of the second analog-digital converter, the third input of which is a clock bus, the outputs of the first analog-digital converter are connected to the corresponding first information inputs of the first and second switches and code comparison unit, the outputs of the second analog-to-digital converter are connected to the corresponding second information inputs of the first and second switches and the comparison unit code c, and the first and second control inputs of the first and second switches, respectively, are combined and are, respectively, the first and second control buses, 5, the outputs of the first and second switches are connected respectively to the first and second register inputs, and the first inputs of the first and second scaling operational amplifiers are combined and are the first input bus, the second inputs are the second and third input buses respectively, the input of the third scaling operational amplifier is connected to the output 50 55 the reference voltage source, the outputs of the code comparison unit are the control bus, the register outputs are the output bus. 1594687 0 , ..., „..,.„ 5 scaling operational amplifiers — jjjj OUTPUTS of which are connected in the process of device operation, i.e. monitors. 5 claims An A / D conversion device comprising a first A / D converter and a source of reference voltage, the output of which is connected to the first input of the first A / D converter, the second input of which is a clock pulse bus, characterized in that by creating an additional possibility of converting an analog value into a code with an irrational basis / 2 and controlling the accuracy of the conversion, a code comparison block, p Trunk, two switches, a second analog-to-digital converter, the first, second and third five 0 35 0 correspondingly to the third input of the first analog to digital converter, jc to the first and second inputs of the second analog to digital converter, the third input of which is a clock bus, the outputs of the first analog to digital converter are connected to the corresponding first information inputs of the first and second switches and code comparison unit, the outputs of the second analog-digital converter are connected to the corresponding second information inputs of the first and second switches and the comparison unit o, and the first and second control inputs of the first and second switches, respectively, are combined and are respectively the 5 first and second control buses; the outputs of the first and second switches are connected respectively to the first and second inputs of the register, the first inputs of the first and second scaling operational amplifiers are combined and are the first input bus, the second inputs are the second and third input buses respectively, the input of the third scaling operational amplifier is connected to the output 0 five the reference voltage source, the outputs of the code comparison unit are the control bus, the register outputs are the output bus.