KR960016813B1 - Multi-channel digital/analog converter - Google Patents

Abstract

a single channel digital/analog converter(10) converting a digital signal inputted through a data bus into an analog signal; a sample/hold means(20) including several sample/hold parts(21-2n) to sample and to hold the analog signal from the single channel digital/analog converter(10); and an address decoder part(30) comprising several address decoders(31,32-3n) controlling each of the sample/hold means(20) to select the output of the sample/hold means(20).

Description

Multichannel Digital / Analog Converter

1 is a configuration diagram in which a sample / hold means is connected to a single channel digital / analog converter of the present invention.

2 is a block diagram of an analog demultiplexer and a sample / hold means connected to a single channel digital / analog converter of the present invention.

3 is a block diagram of a conventional embedded multi-channel digital to analog converter.

4 is an exemplary diagram of a circuit in which the 16-channel digital / analog converter of the present invention is designed using a sample / hold unit.

* Explanation of symbols on main parts of the drawings

10: single channel digital / analog converter 20: multichannel sample / hold means

30: address decoder section 40: analog demultiplexer section

50: single channel sample / hold means

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multichannel digital / analog converter, and does not use a conventional built-in multichannel digital / analog converter and uses a single channel digital / analog converter and a sample / hold means that are commonly used. It is intended to provide a low resolution multichannel digital / analog converter.

In general, multichannel digital-to-analog converters are electronic components widely used in digital automatic control using microprocessors, audio, TV, video, and digital signal processing (DSP) applications.

Conventional multichannel digital / analog converters that have been used up to now include a built-in multichannel / analog converter 60 in which several digital / analog circuits are packaged into one chip as shown in FIG. come.

Therefore, it is limited by the integration density of the semiconductor and the number of channels, and has a disadvantage of being expensive.

The currently available built-in multi-channel digital-to-analog converters range from 2 to 36 channels, with low resolutions of 8, 10, and 12 bits predominantly available, and high resolutions of 14 and 16 bits. There are very few digital / analog converters.

The present invention is to solve the conventional problems, it characterized in that it is possible to implement a multi-channel using a low-cost single-channel digital / analog converter and a sample / hold means.

That is, the present invention allows the analog output of a single channel digital / analog converter to obtain a multichannel analog signal by using a sample / hold means, wherein a single channel digital / analog converter and a plurality of sample / holds are obtained. The combination of these features allows existing single-channel digital / analog converters to achieve high-resolution and low-resolution multichannel digital / analog converters at low cost without limiting the number of channels.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing an embodiment of the present invention, which includes a single channel digital / analog converter 10 for converting a digital signal input through a data bus into an analog signal, and the single channel digital / analog. Specify the channel of the multichannel sample / hold means 20 for sampling and holding the analog signal output of the converter 10 and the information received through the address bus; An address decoder section 30 for controlling each of the multichannel sample / hold sections 21, 22, ..., 2n of the multichannel sample / hold section 20, wherein the CPU transfers an address to the address bus. Is omitted.

2 is a block diagram illustrating another embodiment of the present invention, in which a single channel digital / analog converter 10 and a plurality of common inputs received from the single channel digital / analog converter 10 are selected. An analog demultiplexer section 40 for outputting to an output terminal, an address decoder section 30 for designating an output line of the analog demultiplexer section 40 as an address transmitted via an address bus, and the analog demultiplexer section And sample / hold means (50) consisting of a plurality of sample / hold portions (51, 52, ..., 5n) for sampling and holding the output value of (40), wherein the CPU for transferring an address to the address bus is omitted. It was.

The analog demultiplexer 40 and the single channel sample / hold means 50 constitute a multi-channel sample / hold means 20.

4 is a specific embodiment of the present invention, the digital-to-analog converter 61 converts a 16-bit digital input into an analog signal, and R ₁ , R ₂ , R ₃ , R ₄ and C ₁ are resistors and capacitors for adjusting the applied voltage (+12 V), and the analog signal, which is the output of the digital / analog converter 61, has four samples / four having four channels. It is input to the holding part 62 in common.

The address decoder 63, which receives information from the 4-bit address bus and has an enable line, has a function of specifying a channel of the sample / hold unit 62 and a function of controlling the sample / hold unit. have. Since the address decoder 63 is designed as a chip that is active low, 16 inverters I 1 to I 16 are disposed corresponding to each output line of the chip. The operation of FIG. 4 is the same as that of FIG. When the inverters I 1 to I 16 are designed to be active high, it will be appreciated that the inverters are omitted. The single channel digital / analog converter 61 may be implemented with AD DA C71-COB-V, the address decoder 63 may be implemented with 74LS 154, and the sample / hold part 62 is configured with AD 684JQ. Can be implemented.

The following describes the overall operation and effects of the present invention.

As shown in FIG. 1, in order to output an analog signal to a desired channel, first input a digital value corresponding to an analog value to be output to the data bus of the digital / analog converter 10, the single channel. The analog signal, which is the output of the digital / analog converter 10, is commonly input to each of the multichannel sample / hold sections 21, 22, ..., 2n. At this time, each of the address decoders 31, 32, ..., 3n of the address decoder unit 30 sends out a signal only to the output line designated by the address transferred to the address bus, thereby providing the multi-channel sample / hold units 21, 22, ..., ... One channel of 2n) is specified, and each multichannel sample / hold section 21, 22, ..., 2n is controlled. That is, each of the address decoders 31, 32, ..., 3n not only designates one channel from the information received through the n-bit address bus, but also the multi-channel sample / hold units 21, 22, ..., 2n By controlling to sample and maintain the analog signal input from the single channel digital / analog converter 10, an analog value can be output to a desired channel.

On the other hand, as shown in FIG. 2, in order to output an analog signal to a desired channel, a digital value corresponding to an analog value desired for output of the data bus of the digital / analog converter 10 is input. The analog signal, which is an output of the digital / analog converter 10, is input to each of the demultiplexers 41, 42, ..., 4n of the analog demultiplexer section 40, and receives the information by the address bus 30. Decoders 31, 32,..., And 3n of N U) designate output lines of the respective analog demultiplexers 41, 42,..., 4 n. At this time, if the sample / hold signal is sent, the analog value is output to the desired channel. The S / H control lines of the single-channel sample / holders 51, 52, ..., 5n, if the input value is 1, sample the analog signal values of the analog demultiplexer sections 41, 42, ..., 4n and input the input values. If 0, it has a control function to maintain the sampling value.

As described in detail above, the present invention can expand the number of channels at a low cost by using a single channel digital / analog converter and a sample / hold device which are generally used, and not only a low resolution multichannel digital / analog converter There is an effect to realize a high resolution multichannel digital to analog converter.

Especially in the field of digital automatic control, a single channel digital / analog converter is used to drive several actuators, or when using instead of semi-fixed or variable resistors in products with many adjustment points such as VTR and TV. The density can be increased.

In addition, high-resolution embedded digital-to-analog converters, which require high precision, are not yet commercially available, making it easy to realize high-resolution multichannel digital-to-analog converters.

Claims (2)

A single channel digital / analog converter 10 for converting a digital signal input through a data bus into an analog signal and an analog signal which is an output of the single channel digital / analog converter 10 are simultaneously received and sampled. And a sample / hold means 20 including a plurality of sample / hold parts 21 to 2n for holding and parallel connection with an address bus, respectively, and the sample / hold means 20 from information via an address bus. It consists of an address decoder section 30 composed of a plurality of address decoders 31, 32, ..., 3n respectively controlling corresponding to each sample / hold section of the sample / hold means 20 to select an output channel of Featuring multichannel digital / analog converters. A single channel digital / analog converter 10 for converting a digital signal input through a data bus into an analog signal; Analog Demultiplexer consisting of Analog Demultiplexers 41, 42, ..., 4n to which output lines are assigned corresponding to each Address Decoder 31, 32, ..., 3n of each Address Decoder of the Address Decoder 30. 40 and a plurality of single channel sample / hold sections 51 controlled by the S / H control line (Sample Hold Control) and receiving and sampling and holding the outputs of the respective demultiplexers 41, 42, ..., 4n. A multichannel sample / hold means 20 composed of a single channel sample / hold means 10 composed of 52, ..., 5n); And an address decoder section (30) consisting of said analog demultiplexers (41, 42, ..., 4n) from information via an address bus.