KR20130120821A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display device according to an embodiment of the present invention includes a display panel with a plurality of liquid crystal cells. The liquid crystal cells share the same data line. Two liquid crystal cells which are adjacently arranged between a first gate line and a second gate line make a first pair. Two liquid crystal cells which make the first pair include a first liquid cell connected to the data line through a first TFT and a second liquid crystal cell connected to the data line through a second TFT and a third TFT. The first TFT and the second TFT are turned on when a first gate line is activated by a scan signal. The third TFT is turned on when a second gate line is activated by the scan signal.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device capable of increasing the aperture ratio.

The liquid crystal display displays an image by controlling the light transmittance of the liquid crystal layer through an electric field applied to the liquid crystal layer in accordance with a video signal. Such a liquid crystal display device is a flat panel display device having advantages of small size, thinness and low power consumption, and is used as a portable computer such as a notebook PC, office automation equipment, audio / video equipment and the like. Particularly, an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell is capable of actively controlling a switching element, which is advantageous for a moving image. As a switching element used in the liquid crystal display device, a thin film transistor (hereinafter referred to as "TFT") is mainly used.

The liquid crystal display includes a plurality of liquid crystal cells for image realization and signal lines for driving each of the liquid crystal cells. The signal lines include data lines to which a data voltage is applied and gate lines to which a scan signal is applied. As the resolution of the LCD increases, the number of data lines and gate lines increases. When the area where an image is displayed on the display panel of the liquid crystal display device is defined as the opening area, the ratio of the opening area to the opening area is the percentage of the entire area of the display panel. Since image display is impossible in the area where the signal lines are formed, the opening ratio decreases as the number of data lines and gate lines increases. In addition, at high resolution, as the number of data lines and gate lines is increased, a configuration of a driving circuit unit for driving the data lines and gate lines becomes complicated.

When m (m is a natural number of two or more) liquid crystal cells for each horizontal cell line, a commonly known normal liquid crystal display device requires one gate line and m data lines to drive m liquid crystal cells. Shall be. On the contrary, the DRD driving liquid crystal display proposed to simplify the configuration of the data driving circuit includes two gate lines and m / 2 for each horizontal cell line to drive m liquid crystal cells. Data lines are required. The DRD driving method can reduce the number of output channels of the data driving circuit by reducing the number of data lines by half compared to a normal liquid crystal display at the same resolution. However, in the DRD driving method, since the number of gate lines is doubled in comparison with the normal liquid crystal display at the same resolution, the total number of signal lines is rather increased. In the case of the DRD driving method, it is difficult to improve the aperture ratio of the display panel at high resolution.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of increasing the aperture ratio of a display panel while simplifying the configuration of a driving circuit unit for driving signal lines of the display panel.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention is a liquid crystal display device having a display panel formed with a plurality of liquid crystal cells, the liquid crystal cells share the same data line and the first gate line and the first gate line; Forming a first pair in units of two liquid crystal cells disposed adjacent to each other between two gate lines; The two liquid crystal cells forming the first pair include a first liquid crystal cell connected to the data line through a first TFT, and a second liquid crystal cell connected to the data line through a second TFT and a third TFT. and; The first TFT and the second TFT are turned on when the first gate line is activated by the scan signal, and the third TFT is turned on when the second gate line is activated by the scan signal.

According to the present invention, the number of gate lines is approximately equal to the number of liquid crystal cells in the vertical direction, and the number of data lines is reduced to about half of the number of liquid crystal cells in the horizontal direction, or the number of data lines is equal to the number of liquid crystal cells in the horizontal direction. Since the number of gate lines can be reduced by almost half compared to the number of liquid crystal cells in the vertical direction, the configuration of the driving circuit can be simplified, and the aperture ratio can be greatly increased.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.
2 shows a cell array according to one embodiment of the invention.
3 is an equivalent circuit diagram showing a part of FIG. 2.
4 is a diagram illustrating a scan signal applied to the gate line of FIG. 3 and a data signal synchronized with the scan signal;
5 illustrates a cell array according to another embodiment of the present invention.
FIG. 6 is an equivalent circuit diagram of a portion of FIG. 5. FIG.
FIG. 7 is a diagram illustrating a scan signal applied to a gate line of FIG. 6 and a data signal synchronized with the same;

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 1 to 7.

1 shows a liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a display panel 10, a timing controller 11, a data driving circuit 12, and a gate driving circuit 13.

The display panel 10 includes two glass substrates and a liquid crystal layer formed therebetween. In the display panel 10, a plurality of liquid crystal cells Clc are arranged in a matrix form for each pixel area provided in a cross structure of the data lines DL and the gate lines GL.

The lower glass substrate of the display panel 10 includes a plurality of data lines DL, a plurality of gate lines GL, TFTs, pixel electrodes 1 of liquid crystal cells Clc connected to TFTs, and pixels. The common electrode 2 and the storage capacitor Cst, etc., which face the electrodes 1, are formed. A black matrix, a color filter, and the like are formed on the upper glass substrate of the display panel 10. The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system. A polarizing plate having an optical axis orthogonal to each other is attached to each of the upper and lower glass substrates of the display panel 10, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on an inner surface thereof in contact with the liquid crystal.

In the display panel 10, a cell array having an intersection structure between the data lines DL and the gate lines GL is formed. The cell array includes a plurality of liquid crystal cells Clc. The liquid crystal cells Clc are paired in units of two liquid crystal cells disposed adjacent to each other. Since two liquid crystal cells in a pair share the same data line, they charge a data voltage having the same polarity.

The present invention has a cell array configuration as shown in Figs. In addition, the present invention has a cell array configuration as shown in FIGS. 5 to 7 in order to reduce the number of data lines almost without increasing the number of gate lines to about half of the number required for the corresponding resolution.

In each of these configurations, two paired liquid crystal cells include a first liquid crystal cell connected to a data line through a first TFT, and a second liquid crystal cell connected to a data line through a second TFT and a third TFT. The two liquid crystal cells in pairs are allocated with a first gate line and a second gate line disposed adjacent to each other. Further, in each of these configurations, the first TFT and the second TFT are turned on when the first gate line is activated by the scan signal, and the third TFT is turned on when the second gate line is activated by the scan signal. do.

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a dot clock signal DCLK, and the like, and the data driving circuit 12 and the gate driving circuit. The control signals DDC and GDC for controlling the operation timing of the furnace 13 are generated.

The data control signal DDC for controlling the operation timing of the data driving circuit 12 is source sampling to control the latching operation of data in the data driving circuit 12 based on a rising or falling edge. The polarity of the clock (Source Sampling Clock: SSC), the source output enable signal SOE for controlling the output of the data driving circuit 12, and the data voltages to be supplied to the liquid crystal cells Clc of the display panel 10. And a polarity control signal POL for controlling.

The gate control signal GDC for controlling the operation timing of the gate driving circuit 13 may include a gate start pulse (GSP) indicating a start horizontal line at which scanning starts in one vertical period in which one screen is displayed; A gate shift clock signal (Gate Shift) generated at a pulse width corresponding to an ON period of a TFT as a timing control signal input to a shift register in the gate driving circuit 13 to sequentially shift the gate start pulse GSP. Clock (GSC), and a gate output enable signal (GOE) for controlling the output of the gate driving circuit 13 and the like.

The timing controller 11 aligns the input digital video data RGB with the resolution of the display panel 10 and supplies the digital video data RGB to the data driving circuit 12.

The data driver circuit 12 includes a plurality of data drive ICs. Each of the data drive ICs includes a shift register, a latch, a digital to analog converter (DAC), an output buffer, and the like.

The data driving circuit 12 latches the digital video data RGB according to the data control signal DDC and converts the latched data into a positive data voltage or a negative data voltage with reference to the polarity control signal. The data driving circuit 12 inverts the polarities of the data voltages supplied to the data lines DL in units of data lines and inverts them in units of frames. The data voltage whose polarity is inverted by the data driving circuit 12 is sequentially supplied to the data lines DL in synchronization with the scan signal.

The gate drive circuit 13 includes a plurality of gate drive ICs. Each of the gate drive ICs includes a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for TFT driving of a liquid crystal cell, an output buffer, and the like. The gate driving circuit 13 generates a scan signal including two consecutive pulses according to the gate control signal GDC, and supplies the horizontal line to the gate lines GL in a line sequential manner to apply a data voltage. Choose. The gate driving circuit 13 may be directly formed on the lower glass substrate together with the cell array by a gate driver in panel (GIP) process.

2 shows a cell array according to an embodiment of the present invention. 3 shows an equivalent circuit for a portion of FIG. 2. 4 illustrates a scan signal applied to the gate line of FIG. 3 and a data signal synchronized with the scan signal.

2 and 3, two liquid crystal cells paired in a cell array according to an embodiment of the present invention are adjacent to each other first and second liquid crystal cells LC1 and horizontally along an extension direction of a gate line. The liquid crystal cell LC2 is included. Since the first liquid crystal cell LC1 and the second liquid crystal cell LC2 are horizontally adjacent to each other and are connected to the same data line, one data line is allocated to every two vertical cell lines CL so that the number of data lines is horizontal. It is reduced by almost half of the number of liquid crystal cells. Since the gate lines are commonly connected to a part of the liquid crystal cell of the odd-numbered horizontal cell line RL and a part of the liquid crystal cell of the even-numbered horizontal cell line RL, the number thereof is almost similar to the number of liquid crystal cells in the vertical direction.

That is, according to an exemplary embodiment of the present invention, K (K is a positive even number) liquid crystal cells are formed in each horizontal cell line RL along the extending direction of the gate line, and data is formed for each vertical cell line CL. When J (J is a positive even number) liquid crystal cells are formed along the extension direction of the line, the display panel includes (K / 2 + 1) data lines and (J + 1) gate lines. For example, when 16 liquid crystal cells are formed in each horizontal cell line RL and three liquid crystal cells are formed in each vertical cell line CL in FIG. 2, nine data lines Dm are formed in the display panel. -1 to Dm + 7 and four gate lines Gn to Gn + 3.

Referring to FIG. 3, the liquid crystal cells form a first pair in units of two liquid crystal cells disposed adjacent to each other between the first gate line Gn and the second gate line Gn + 1, and also the second gate. A second pair is formed in units of two liquid crystal cells between the line Gn + 1 and the third gate line Gn + 2.

The first liquid crystal cell LC1 is connected to the data line Dm through the first TFT TR1, and the second liquid crystal cell LC2 is connected to the data line through the second TFT TR2 and the third TFT TR3. It is connected to (Dm). A first gate line Gn and a second gate line Gn + 1 are allocated to upper and lower sides of the first and second liquid crystal cells LC1 and LC2, respectively.

The first TFT TR1 includes a gate electrode connected to the first gate line Gn, a drain electrode connected to the data line Dm, and a source electrode connected to the first liquid crystal cell LC1. The first TFT TR1 is turned on when the first gate line Gn is activated by the scan signal so that the data voltage charged in the data line Dm is applied to the first liquid crystal cell LC1.

The second TFT TR2 includes a gate electrode connected to the first gate line Gn, a drain electrode connected to the data line Dm, and a source electrode connected to the drain electrode of the third TFT TR3. The third TFT TR3 includes a gate electrode connected to the second gate line Gn, a drain electrode connected to the source electrode of the second TFT TR2, and a source electrode connected to the second liquid crystal cell LC2. It includes. The second and third TFTs TR2 and TR3 are turned on when the first and second gate lines Gn and Gn + 1 are simultaneously activated by the scan signal, and the data voltages charged in the data line Dm are zero. 2 is applied to the liquid crystal cell LC2.

The third liquid crystal cell LC3 is connected to the data line Dm through the fourth TFT TR4, and the fourth liquid crystal cell LC4 is connected to the data line through the fifth TFT TR5 and the sixth TFT TR6. It is connected to (Dm). The second gate line Gn + 1 and the third gate line Gn + 2 are allocated to the upper side and the lower side of the third and fourth liquid crystal cells LC3 and LC4, respectively.

The fourth TFT TR4 includes a gate electrode connected to the second gate line Gn + 1, a drain electrode connected to the data line Dm, and a source electrode connected to the third liquid crystal cell LC3. The fourth TFT TR4 is turned on when the second gate line Gn + 1 is activated by the scan signal so that the data voltage charged in the data line Dm is applied to the third liquid crystal cell LC3.

The fifth TFT TR5 includes a gate electrode connected to the second gate line Gn + 1, a drain electrode connected to the data line Dm, and a source electrode connected to the drain electrode of the sixth TFT TR6. do. The sixth TFT TR6 is connected to the gate electrode connected to the third gate line Gn + 2, the drain electrode connected to the source electrode of the fifth TFT TR5, and the fourth liquid crystal cell LC4. It includes a source electrode. The fifth and sixth TFTs TR5 and TR6 are turned on when the second and third gate lines Gn + 1 and Gn + 2 are simultaneously activated by the scan signal to charge the data voltages charged in the data line Dm. The fourth liquid crystal cell LC4 is applied to the fourth liquid crystal cell LC4.

The scan signal SP applied to each gate line Gn, Gn + 1, and Gn + 2 includes two pulses as shown in FIG. The scan signal SP is a first pulse P1 having a first width A and a second pulse B1 generated after the first pulse P1 and having a second width B wider than the first width A. Pulse P2.

As shown in FIG. 4, the scan signal SPn of the second pulse P2 applied to the first gate line Gn is the scan signal SPn of the first pulse P1 applied to the second gate line Gn + 1. Overlap with +1). In other words, the scan signal SPn of the second pulse P2 applied to the first gate line Gn and the scan signal SPn + of the first pulse P1 applied to the second gate line Gn + 1. 1) overlaps by the first width A. The rising edge of the second pulse P2 of the scan signal SPn and the rising edge of the first pulse P1 of the scan signal SPn + 1 may be synchronized with each other. The falling edge of the second pulse P2 of the scan signal SPn and the rising edge of the second pulse P2 of the scan signal SPn + 1 may be synchronized with each other.

In addition, as illustrated in FIG. 4, the scan signal SPn + 1 of the second pulse P2 applied to the second gate line Gn + 1 is applied to the first pulse P1 applied to the third gate line Gn + 2. Superimposed on the scan signal SPn + 2. In other words, the scan signal SPn + 1 of the second pulse P2 applied to the second gate line Gn + 1 and the scan of the first pulse P1 applied to the third gate line Gn + 2 are scanned. The signals SPn + 2 overlap by the first width A. The rising edge of the second pulse P2 of the scan signal SPn + 1 and the rising edge of the first pulse P1 of the scan signal SPn + 2 may be synchronized with each other. The falling edge of the second pulse P2 of the scan signal SPn + 1 and the rising edge of the second pulse P2 of the scan signal SPn + 2 may be synchronized with each other.

In FIG. 4, the data voltage DLC2 is applied to the second liquid crystal cell LC2 in the period T1 where the scan signal SPn of the second pulse P2 and the scan signal SPn + 1 of the first pulse P1 overlap. ) Is charged. In the overlap period T1, the first liquid crystal cell LC1 and the third liquid crystal cell LC3 are precharged with the data voltage DL2. The first liquid crystal cell LC1 has a data voltage DL1 in a period T2 in which the scan signal SPn of the second pulse P2 is not overlapped with the scan signal SPn + 1 of the first pulse P1. ) Is charged.

In FIG. 4, the data voltage is applied to the fourth liquid crystal cell LC4 in the period T3 where the scan signal SPn + 1 of the second pulse P2 and the scan signal SPn + 2 of the first pulse P1 overlap. (DLC4) is charged. In this overlap period T3, the third liquid crystal cell LC3 is precharged with the data voltage DL4. The third liquid crystal cell LC3 has a data voltage in a period T4 in which the scan signal SPn + 1 of the second pulse P2 does not overlap with the scan signal SPn + 2 of the first pulse P1. Filled with (DLC3).

The liquid crystal cells LC2 and LC4 charging the data voltage through the two TFTs have a longer charging path than the liquid crystal cells LC1 and LC3 charging the data voltage through the one TFT, so that the charging power is relatively high. Falls. In order to compensate for the difference in charging power between the liquid crystal cells, the charging time for the second and fourth liquid crystal cells LC2 and LC4 should be increased compared to the first and third liquid crystal cells LC1 and LC3. To this end, the width A of the first pulse P1 corresponding to the overlap period T1 is set to be wider than 1/2 of the width B of the second pulse P2.

In order to reduce power consumption of the data driving circuit, paired liquid crystal cells are zigzag connected to the data lines along the vertical direction as shown in FIG. 2. In other words, each of the two liquid crystal cells constituting the first pair in the odd-numbered horizontal cell line RL is connected to a data line disposed on either of their left or right sides, and in the even-numbered horizontal cell line RL. Each of the two liquid crystal cells forming the second pair is connected to a data line disposed on the other side of the left side or the right side thereof.

As a result, the liquid crystal cells connected to the data line through one TFT and the liquid crystal cells connected to the data line through two TFTs are arranged in a check board type with each other to mitigate the perceived luminance deviation between the liquid crystal cells. .

As described above, according to an exemplary embodiment of the present invention, the number of gate lines is approximately equal to the number of liquid crystal cells in the vertical direction, and the number of data lines can be reduced by almost half compared to the number of liquid crystal cells in the horizontal direction. Not only can it be simplified, but it can also greatly increase the aperture ratio.

 5 shows a cell array according to another embodiment of the present invention. 6 shows an equivalent circuit for a portion of FIG. 5. 7 illustrates a scan signal applied to the gate line of FIG. 6 and a data signal synchronized with the scan signal.

5 and 6, two liquid crystal cells paired in a cell array according to another embodiment of the present invention may be formed of the first liquid crystal cell LC1 ′ and the first liquid crystal cell LC1 ′ adjacent to each other vertically along an extension direction of the data line. 2 liquid crystal cell LC2 '. Since the first liquid crystal cell LC1 'and the second liquid crystal cell LC2' are vertically adjacent to each other and are connected to the same data line, one gate line is allocated to each of the two horizontal cell lines RL so that the number of gate lines is increased. It is reduced by almost half compared to the number of liquid crystal cells in the vertical direction. Each of the gate lines is commonly connected to a portion of the liquid crystal cell of the odd-numbered horizontal cell line RL and a portion of the liquid crystal cell of the even-numbered horizontal cell line RL.

That is, according to another exemplary embodiment of the present invention, K (K is a positive even number) liquid crystal cells are formed in each horizontal cell line RL along the extending direction of the gate line, and data is formed in each vertical cell line CL. When J (J is a positive even number) liquid crystal cells are formed along the extension direction of the line, the display panel includes (K + 1) data lines and (J / 2 + 1) gate lines. For example, when eight liquid crystal cells are formed in each horizontal cell line RL and four liquid crystal cells are formed in each vertical cell line CL in FIG. 5, nine data lines Dm are formed in the display panel. -1 to Dm + 7 and three gate lines Gn to Gn + 2.

Referring to FIG. 6, the liquid crystal cells form a first pair in units of two liquid crystal cells disposed adjacent to each other between the first gate line Gn and the second gate line Gn + 1 and further include a second gate. A second pair is formed in units of two liquid crystal cells between the line Gn + 1 and the third gate line Gn + 2.

The first liquid crystal cell LC1 'is connected to the data line Dm through the first TFT TR1', and the second liquid crystal cell LC2 'is connected to the second TFT TR2' and the third TFT TR3 '. Is connected to the data line Dm. The first gate line Gn and the second gate line Gn + 1 are allocated to the upper side and the lower side of the first and second liquid crystal cells LC1 ′ and LC2 ′, respectively.

The first TFT TR1 'includes a gate electrode connected to the first gate line Gn, a drain electrode connected to the data line Dm, and a source electrode connected to the first liquid crystal cell LC1'. The first TFT TR1 'is turned on when the first gate line Gn is activated by the scan signal so that the data voltage charged in the data line Dm is applied to the first liquid crystal cell LC1'.

The second TFT TR2 'includes a gate electrode connected to the first gate line Gn, a drain electrode connected to the data line Dm, and a source electrode connected to the drain electrode of the third TFT TR3'. do. The third TFT TR3 'is connected to the gate electrode connected to the second gate line Gn, the drain electrode connected to the source electrode of the second TFT TR2', and the second liquid crystal cell LC2 '. And a source electrode. The second and third TFTs TR2 'and TR3' are turned on when the first and second gate lines Gn and Gn + 1 are simultaneously activated by a scan signal and are charged in the data line Dm. The second liquid crystal cell LC2 'is applied to the second liquid crystal cell LC2'.

The third liquid crystal cell LC3 'is connected to the data line Dm through the fourth TFT TR4', and the fourth liquid crystal cell LC4 'is connected to the fifth TFT TR5' and the sixth TFT TR6 '. Is connected to the data line Dm. The second gate line Gn + 1 and the third gate line Gn + 2 are allocated to the upper side and the lower side of the third and fourth liquid crystal cells LC3 'and LC4', respectively.

The fourth TFT TR4 'includes a gate electrode connected to the second gate line Gn + 1, a drain electrode connected to the data line Dm, and a source electrode connected to the third liquid crystal cell LC3'. do. The fourth TFT TR4 'is turned on when the second gate line Gn + 1 is activated by the scan signal so that the data voltage charged in the data line Dm is applied to the third liquid crystal cell LC3'. do.

The fifth TFT TR5 'includes a gate electrode connected to the second gate line Gn + 1, a drain electrode connected to the data line Dm, and a source electrode connected to the drain electrode of the sixth TFT TR6'. It includes. The sixth TFT TR6 'includes a gate electrode connected to the third gate line Gn + 2, a drain electrode connected to the source electrode of the fifth TFT TR5', and a fourth liquid crystal cell LC4 '. And a source electrode connected to it. The fifth and sixth TFTs TR5 'and TR6' are turned on when the second and third gate lines Gn + 1 and Gn + 2 are simultaneously activated by the scan signal, and are charged in the data line Dm. The data voltage is applied to the fourth liquid crystal cell LC4 '.

The scan signal SP applied to each gate line Gn, Gn + 1, and Gn + 2 includes two pulses as shown in FIG. The scan signal SP is a first pulse P1 having a first width A and a second pulse B1 generated after the first pulse P1 and having a second width B wider than the first width A. Pulse P2.

As illustrated in FIG. 7, the scan signal SPn of the second pulse P2 applied to the first gate line Gn is the scan signal SPn of the first pulse P1 applied to the second gate line Gn + 1. Overlap with +1). In other words, the scan signal SPn of the second pulse P2 applied to the first gate line Gn and the scan signal SPn + of the first pulse P1 applied to the second gate line Gn + 1. 1) overlaps by the first width A. The rising edge of the second pulse P2 of the scan signal SPn and the rising edge of the first pulse P1 of the scan signal SPn + 1 may be synchronized with each other. The falling edge of the second pulse P2 of the scan signal SPn and the rising edge of the second pulse P2 of the scan signal SPn + 1 may be synchronized with each other.

In addition, as illustrated in FIG. 7, the scan signal SPn + 1 of the second pulse P2 applied to the second gate line Gn + 1 is applied to the first pulse P1 applied to the third gate line Gn + 2. Superimposed on the scan signal SPn + 2. In other words, the scan signal SPn + 1 of the second pulse P2 applied to the second gate line Gn + 1 and the scan of the first pulse P1 applied to the third gate line Gn + 2 are scanned. The signals SPn + 2 overlap by the first width A. The rising edge of the second pulse P2 of the scan signal SPn + 1 and the rising edge of the first pulse P1 of the scan signal SPn + 2 may be synchronized with each other. The falling edge of the second pulse P2 of the scan signal SPn + 1 and the rising edge of the second pulse P2 of the scan signal SPn + 2 may be synchronized with each other.

In FIG. 7, in the period T1 where the scan signal SPn of the second pulse P2 and the scan signal SPn + 1 of the first pulse P1 overlap each other, the data voltage (2) is applied to the second liquid crystal cell LC2 '. DLC2 ') is charged. In the overlap period T1, the first liquid crystal cell LC1 ′ and the third liquid crystal cell LC3 ′ are precharged with the data voltage DLC2 ′. In addition, the first liquid crystal cell LC1 ′ has a data voltage in the period T2 when the scan signal SPn of the second pulse P2 is not overlapped with the scan signal SPn + 1 of the first pulse P1. DLC1 ').

In FIG. 7, data is stored in the fourth liquid crystal cell LC4 ′ in a period T3 where the scan signal SPn + 1 of the second pulse P2 and the scan signal SPn + 2 of the first pulse P1 overlap. The voltage DLC4 'is charged. In this overlap period T3, the third liquid crystal cell LC3 ′ is precharged with the data voltage DLC4 ′. The third liquid crystal cell LC3 ′ has data in a period T4 in which the scan signal SPn + 1 of the second pulse P2 does not overlap with the scan signal SPn + 2 of the first pulse P1. Charged to voltage DLC3 '.

The liquid crystal cells LC2 'and LC4' that charge the data voltage through two TFTs have a longer charging path than the liquid crystal cells LC1 'and LC3' that charge the data voltage through one TFT. As the charge falls. In order to compensate for the difference in charging power between the liquid crystal cells, the charging time for the second and fourth liquid crystal cells LC2 'and LC4' should be increased compared to the first and third liquid crystal cells LC1 'and LC3'. To this end, the width A of the first pulse P1 corresponding to the overlap period T1 is set to be wider than 1/2 of the width B of the second pulse P2.

In order to reduce power consumption of the data driving circuit, paired liquid crystal cells are zigzag connected to the data lines along the vertical direction as shown in FIG. 5. In other words, when a horizontal cell line pair is formed for two vertically neighboring horizontal cell lines, each of the two liquid crystal cells constituting the first pair in the odd-numbered horizontal cell line pair is on either side of their left or right side. Each of the two liquid crystal cells making up the second pair in the even-numbered horizontal cell line pair is connected to the data line arranged on the other side of their left or right side.

As a result, the liquid crystal cells connected to the data line through one TFT and the liquid crystal cells connected to the data line through two TFTs are each arranged in a stripe type.

As described above, according to another exemplary embodiment of the present invention, the number of gate lines can be reduced to about half of the number of liquid crystal cells in the vertical direction while the number of data lines is approximately equal to the number of liquid crystal cells in the horizontal direction. Not only can it be simplified, but it can also greatly increase the aperture ratio.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit

Claims (14)

A liquid crystal display device having a display panel in which a plurality of liquid crystal cells are formed,
The liquid crystal cells form a first pair in units of two liquid crystal cells that share the same data line and are disposed adjacent to each other between a first gate line and a second gate line;
The two liquid crystal cells forming the first pair,
A first liquid crystal cell connected to the data line through a first TFT, and a second liquid crystal cell connected to the data line through a second TFT and a third TFT;
The first TFT and the second TFT are turned on when the first gate line is activated by the scan signal, and the third TFT is turned on when the second gate line is activated by the scan signal. A liquid crystal display device. The method of claim 1,
The scan signal includes a first pulse having a first width and a second pulse generated following the first pulse and having a second width that is wider than the first width;
And a scan signal of the second pulse applied to the first gate line overlaps with a scan signal of the first pulse applied to the second gate line. 3. The method of claim 2,
And a scan signal of the second pulse applied to the first gate line and a scan signal of the first pulse applied to the second gate line overlap each other by the first width. 3. The method of claim 2,
And the first width is wider than half of the second width. The method of claim 1,
And a third gate line facing the first gate line with the second gate line therebetween,
The liquid crystal cells form a second pair in units of two liquid crystal cells between the second gate line and the third gate line;
The two liquid crystal cells forming the second pair include a third liquid crystal cell connected to the data line through a fourth TFT, and a fourth liquid crystal cell connected to the data line through a fifth TFT and a sixth TFT. and;
The fourth TFT and the fifth TFT are turned on when the second gate line is activated by the scan signal, and the sixth TFT is turned on when the third gate line is activated by the scan signal. A liquid crystal display device. The method of claim 5, wherein
The first liquid crystal cell and the second liquid crystal cell forming the first pair are adjacent to each other horizontally along the extending direction of the gate line;
And the third liquid crystal cell and the fourth liquid crystal cell forming the second pair are adjacent to each other horizontally along the extending direction of the gate line. The method according to claim 6,
Each horizontal cell line has K (K is a positive even number) liquid crystal cells along the extension direction of the gate line, and each vertical cell line has J (J is a positive even) liquid crystal cell along the extension direction of the data line. When they form,
And (K / 2 + 1) data lines and (J + 1) gate lines in the display panel. The method of claim 7, wherein
Each of the two liquid crystal cells constituting the first pair in an odd horizontal cell line is connected to a data line disposed on either of their left or right sides;
And each of the two liquid crystal cells forming the second pair in the even-numbered horizontal cell line is connected to a data line disposed on the other side of the left side or the right side thereof. The method of claim 8,
In the display panel,
And liquid crystal cells connected to the data line through one TFT and liquid crystal cells connected to the data line through two TFTs are arranged in a check board type. The method of claim 5, wherein
The first liquid crystal cell and the second liquid crystal cell forming the first pair are adjacent to each other vertically along an extension direction of the data line;
And the third liquid crystal cell and the fourth liquid crystal cell forming the second pair are adjacent to each other vertically along the extension direction of the data line. 11. The method of claim 10,
Each horizontal cell line has K (K is a positive even number) liquid crystal cells along the extension direction of the gate line, and each vertical cell line has J (J is a positive even) liquid crystal cell along the extension direction of the data line. When they form,
And (K + 1) data lines and (J / 2 + 1) gate lines in the display panel. 11. The method of claim 10,
When a horizontal cell line pair is formed for every two vertically neighboring horizontal cell lines,
Each of the two liquid crystal cells constituting the first pair in an odd horizontal cell line pair is connected to a data line disposed on either of their left or right sides;
And each of the two liquid crystal cells constituting the second pair in the even-numbered horizontal cell line pair is connected to a data line disposed on the other side of the left side or the right side thereof. 13. The method of claim 12,
In the display panel,
And liquid crystal cells connected to the data line through one TFT and the liquid crystal cells connected to the data line through two TFTs are arranged in a stripe type, respectively. The method of claim 1,
The data lines formed on the display panel are applied with a data voltage whose polarity is inverted every frame period.
The polarities of the data voltages applied to the neighboring data lines are opposite to each other.

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