KR101777133B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of reducing color distortion due to polarity shift and a dim in a horizontal or vertical direction, and a liquid crystal display device having m / 2 data lines and 2n (where m and n are natural numbers) A liquid crystal panel including m x n liquid crystal cells defined as intersections of gate lines of the liquid crystal cells and TFTs connected to the liquid crystal cells; A data driving circuit for supplying a data voltage to the data lines in response to a polarity control signal; And a gate driving circuit outputting a plurality of scan signals for driving the gate lines; The liquid crystal cells are supplied with the data voltage in the order of the first to fourth liquid crystal cells, the first liquid crystal cell is arranged at the upper left of the first intersection where the odd data lines and the four gate lines intersect, And the second liquid crystal cell is disposed at a lower left end of the first intersection and disposed at a lower right end of the second intersection, and the third liquid crystal cell is disposed at a lower right end of the second intersection, Wherein the liquid crystal cell is disposed at a right upper end of the first intersection and disposed at a left upper end of the second intersection, the fourth liquid crystal cell is disposed at a right lower end of the first intersection, .

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

The present invention relates to a liquid crystal display device capable of reducing color distortion due to polarity deviation and a dim in a horizontal or vertical direction.

2. Description of the Related Art In recent years, liquid crystal displays (LCDs) have been the most popular display devices due to the characteristics of even image quality, light weight, thinness and low power.

In order to reduce the DC offset component and reduce the deterioration of the liquid crystal, such a liquid crystal display apparatus is applied with inversion driving in which the polarity is inverted between neighboring liquid crystal cells and the polarity is inverted on a frame basis.

Meanwhile, in order to reduce the circuit cost of the liquid crystal display device, the number of data lines is reduced by connecting adjacent thin film transistors (hereinafter referred to as TFTs) on the same display line to the same data line, DRD (Double Rate Driving) panel structure is being developed.

In a liquid crystal display device to which a DRD panel is applied, version driving with vertical 2 dots or horizontal 2 dots is applied. Of the RGB colors, only the cells having a specific color are repeatedly charged with the same polarity, There is a problem that a dim in the horizontal or vertical direction occurs.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of reducing a color distortion due to a polarity shift and a dim in a horizontal or vertical direction.

In order to achieve the above object, a liquid crystal display according to an embodiment of the present invention includes m × n liquid crystal cells defined by intersections of m / 2 data lines and 2n gate lines (m and n are natural numbers) A liquid crystal panel including TFTs connected to the liquid crystal cells; A data driving circuit for supplying a data voltage to the data lines in response to a polarity control signal; And a gate driving circuit outputting a plurality of scan signals for driving the gate lines; The liquid crystal cells are supplied with the data voltage in the order of the first to fourth liquid crystal cells, the first liquid crystal cell is arranged at the upper left of the first intersection where the odd data lines and the four gate lines intersect, And the second liquid crystal cell is disposed at a lower left end of the first intersection and disposed at a lower right end of the second intersection, and the third liquid crystal cell is disposed at a lower right end of the second intersection, Wherein the liquid crystal cell is disposed at a right upper end of the first intersection and disposed at a left upper end of the second intersection, the fourth liquid crystal cell is disposed at a right lower end of the first intersection, .

The gate driving circuit sequentially outputs the plurality of scan signals to the odd gate lines and sequentially supplies the odd gate lines to the even gate lines; And the plurality of scan signals are alternately supplied to the odd gate lines and the even gate lines.

A data voltage having the same polarity is applied to the first and second liquid crystal cells and a data voltage having a polarity opposite to that of the first and second liquid crystal cells is applied to the third and fourth liquid crystal cells .

The first and second liquid crystal cells arranged at diagonal positions are applied with data voltages of the same polarity and the third and fourth liquid crystal cells arranged at diagonal positions are applied with a data voltage of the same polarity .

And the polarity control signal is phase-inverted in four horizontal period periods.

The embodiment of the present invention can reduce the power consumption and heat generation compared to the two-dot inversion driving by inverting the polarity of the data voltage in four horizontal periods, and makes the luminance uniform for each RGB color, thereby reducing color distortion and horizontal or vertical dimming can do.

1 is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention.
2 is an equivalent circuit diagram of the pixel array shown in Fig.
3 is a driving waveform diagram of a scan signal according to an embodiment.
4 is a driving waveform diagram of a data voltage according to an embodiment.

Hereinafter, a liquid crystal display according to an embodiment of the present invention will be described in more detail with reference to the accompanying drawings.

1 is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention. 2 is an equivalent circuit diagram of the pixel array shown in Fig.

1 and 2, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal panel 100, a timing controller 101, a data modulation logic circuit 102, a data driving circuit 103, And a driving circuit (104).

The liquid crystal panel 100 includes an upper glass substrate and a lower glass substrate opposed to each other with a liquid crystal layer interposed therebetween. The liquid crystal panel 100 includes a pixel array 10 for displaying video data. The pixel array 10 is formed by the intersection structure of m (m is a positive integer) / 2 data lines D1 to Dm / 2 and 2n (n is a positive integer) gate lines G1 to G2n And m x n liquid crystal cells Clc arranged in a matrix form.

The m x n liquid crystal cells Clc include m vertical display lines in which the liquid crystal cells Clc are arranged in the data line direction and n horizontal display lines in which the liquid crystal cells Clc are arranged in the gate line direction . The liquid crystal cells Clc of the pixel array 10 are connected to the electric field generated by the voltage difference between the data voltage supplied to the pixel electrode 1 through the TFT and the common voltage Vcom supplied to the common electrode 2 The data voltage is charged and the data voltage is maintained for a predetermined period by the storage capacitor Cst to display an image.

The pixel array 10 includes m / 2 data lines D1 to Dm / 2, 2n gate lines G1 to G2n, mxn pixel electrodes 1, M × n TFTs connected to the pixel electrodes 1 and m × n storage capacitors Cst connected to the pixel electrodes 1. The TFTs adjacent to the left and right in the same line are connected to the same data line. Such a connection structure of the TFT and the data line is shown in Fig.

A gate driving circuit 104 connected to the gate lines G1 to G2n may be directly formed on the non-display surface outside the pixel array 10 on the lower glass substrate of the liquid crystal panel 100. [ In this case, the pixel array 10 and the gate drive circuit 104 are simultaneously formed on the lower glass substrate of the liquid crystal panel 100 by the same thin film process.

On the upper glass substrate of the liquid crystal panel 100, a black matrix, a color filter, and a common electrode are formed. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the driving method.

An alignment film is formed on each of the upper glass substrate and the lower glass substrate of the liquid crystal panel 100 to attach a polarizing plate and set a pre-tilt angle of the liquid crystal.

The liquid crystal mode of the liquid crystal panel 100 applicable to the present invention can be realized in any liquid crystal mode as well as the TN mode, the VA mode, the IPS mode, and the FFS mode described above. Further, the liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, a reflective liquid crystal display device, and the like. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as an edge type backlight unit or a direct type backlight unit. The edge type backlight unit has a structure in which a light source is disposed so as to face the side face of the light guide plate and a plurality of optical sheets are disposed between the liquid crystal panel and the light guide plate. The direct-type backlight unit has a structure in which the optical sheets and the diffusion plate are stacked under the liquid crystal panel 100 and a plurality of light sources are disposed under the diffusion plate. The light source of the backlight unit may include at least one of a hot cathode fluorescent lamp (HCFL), a cold cathode fluorescent lamp (CCFL), an external electro fluorescent lamp (EEFL), and a light emitting diode (LED).

The odd data lines D1, D3, ..., Dm / 2-1 and the TFT disposed on the left side of the odd data lines D1, D3, ..., Dm / The liquid crystal cell Clc and the TFT disposed on the right side of the even-numbered data lines D2, D4, ..., Dm / 2 arranged on the left side of the liquid crystal cell The liquid crystal cell Clc and the TFT disposed on the right side of the even-numbered data lines D2, D4, ..., Dm / 2 and the TFT are referred to as the C liquid crystal cell and the third TFT respectively, TFT.

The first TFT is turned on in response to the gate pulse (or scan signal) from the odd-numbered gate lines G1, G3, ..., G2n-1 to the odd-numbered data lines D1, D3 ... Dm / To the pixel electrode (1) of the A liquid crystal cell (Clc). To this end, the gate electrode of the first TFT is connected to odd-numbered gate lines (G1, G3 ... G2n-1), and the drain electrode is connected to odd-numbered data lines D1, D3 ... Dm / 2-1 . The source electrode of the first TFT is connected to the pixel electrode 1 of the A liquid crystal cell Clc.

The second TFT supplies the data voltage from the odd data lines D1, D3, ..., Dm / 2-1 to the liquid crystal cell Clc in response to the gate pulse from the even gate lines G2, G4, To the pixel electrode (1). To this end, the gate electrode of the second TFT is connected to the even gate lines G2, G4 ... G2n, and the drain electrode is connected to the odd data lines D1, D3 ... Dm / 2-1. And the source electrode of the second TFT is connected to the pixel electrode 1 of the B liquid crystal cell Clc.

The third TFT supplies the data voltage from the even data lines D2, D4, ..., Dm / 2 to the third liquid crystal cell Clc in response to the gate pulse from the even gate lines G2, G4, To the pixel electrode (1). To this end, the gate electrode of the third TFT is connected to the even gate lines G2, G4, ... G2n, and the drain electrode is connected to the even data lines D2, D4, ..., Dm / 2. And the source electrode of the third TFT is connected to the pixel electrode 1 of the C liquid crystal cell Clc.

The fourth TFT supplies a data voltage from the even data lines D2, D4, ..., Dm / 2 to the liquid crystal cell Clc in response to the gate pulse from the odd gate lines G1, G3 ... G2n- To the pixel electrode (1). To this end, the gate electrode of the fourth TFT is connected to the odd-numbered gate lines G1, G3 ... G2n-1, and the drain electrode is connected to the even-numbered data lines D2, D4 ... Dm / 2. And the source electrode of the fourth TFT is connected to the pixel electrode 1 of the D liquid crystal cell Clc.

The data of the liquid crystal cells connected to the odd data lines D1, D3, ..., Dm / 2-1 in accordance with the connection relationship between the TFTs T1 to T4 and the data lines D1 to Dm / The charging sequence and the data charging sequence of the liquid crystal cells connected to the even data lines D2, D4, ..., Dm / 2 are reversed. In other words, the data charging order of the liquid crystal cells connected to the odd data lines D1, D3, ..., Dm / 2-1 and the data charging order of the even data lines D2, D4 ... Dm / The data filling order of the connected liquid crystal cells is a left-right symmetrical direction.

The timing controller 101 receives timing signals such as a vertical / horizontal synchronizing signal (Vsync, Hsync), a data enable signal and a clock signal (CLK) from the system board 105 and supplies the timing signal to the data driving circuit 103 The gate drive circuit 104, and the polarity control signal (hereinafter, POL) and the data modulation logic circuit 102. [ The timing controller 101 supplies the RGB digital video data to the POL and the data modulation logic circuit 102. The timing controller 101 generates a data timing control signal for controlling the data driving circuit 103 and a gate timing control signal for controlling the gate driving circuits 104 using the timing signal. The timing controller controls the gate timing control signal and the timing control signal so that digital video data input at a frame frequency of 60 Hz can be reproduced in the pixel array 10 of the liquid crystal display panel at a frame frequency of 60 x i (i is a positive integer of 2 or more) The frequency of the data timing control signal can be multiplied by a frame frequency of 60 x i Hz.

The control signals output from the timing controller 101 include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE), and a POL. The gate start pulse (GSP) indicates a starting horizontal line at which the scanning starts from one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to the shift register in the gate drive circuit and is a timing control signal for sequentially shifting the gate start pulse GSP. The gate shift clock signal GSC is generated with a pulse width corresponding to the ON period of the TFT. The gate output enable signal GOE indicates the output of the gate drive circuit 104. [ The source start pulse SSP indicates a starting pixel in one horizontal line where data is to be displayed. The source sampling clock SSC instructs the latch operation of data in the data driving circuit 103 on the basis of the rising or falling edge. The source output enable signal (SOE) indicates the output of the data driving circuit 103. The POL indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 100. [ The POL is phase-inverted at four horizontal period intervals.

The data modulation logic circuit 102 receives the gate start pulse GSP, the source output enable signal SOE and the POL so as to sequentially receive the first and second POLs whose phases are inverted to prevent the afterimage and the flicker Output.

The data driving circuit 103 latches the digital video data RGB 'modulated by the POL and the data modulation logic circuit 102 under the control of the timing controller 101. The data driving circuit 103 converts the latched digital video data into an analog positive / negative gamma compensation voltage in response to the POL from the data modulation logic circuit 102 to generate positive / negative data voltages. Then, the data driving circuit 103 supplies the positive polarity / negative polarity data voltages to the data lines D1 to Dm / 2.

The gate driver circuit 104 includes a level shifter for converting the output signal of the shift register and the shift register into a swing width suitable for driving the TFT of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to G2n And a plurality of gate drive ICs. The gate drive circuit 104 outputs a scan signal having a pulse width of approximately one horizontal period synchronized with the positive / negative polarity data voltage. 3, the gate driving circuit 104 applies a plurality of scan signals to the odd-numbered gate lines G1, G3, ..., G2n-1 and the even-numbered gate lines G2, G4 ... G2n G2n-1 and even-numbered gate lines G2, G4, ..., G2n, respectively, while supplying a plurality of scan signals alternately.

Hereinafter, the data charging sequence of the liquid crystal cells according to the embodiment will be described.

As shown in FIG. 2, the liquid crystal cells according to the embodiment are filled with data in the order of the first to fourth liquid crystal cells (1, 2, 3, and 4). Here, the first liquid crystal cell (1) includes a first liquid crystal cell (1) in which odd data lines D1, D3, ..., Dm / 2-1 and four gate lines G1 to G4, G5 to G8, And a second intersecting portion (D1, D2, D3, ..., D4) arranged at the left upper end of the first pixel portion P1 and crossing the even data lines D2, D4 ... Dm / 2 and the four gate lines G1 to G4, G5 to G8, The second liquid crystal cell is disposed at the lower left end of the first intersection P1 and the lower liquid crystal cell is disposed at the lower right end of the second intersection P2, 3) are arranged at the right upper end of the first intersection P1 and at the upper left end of the second intersection P2 and the fourth liquid crystal cell 4 is disposed at the lower right end of the first intersection P1 And is disposed at the lower left of the second intersection P2.

4 is a driving waveform diagram of a data voltage according to an embodiment.

On the other hand, as shown in FIG. 4, the data driving circuit 103 outputs a data voltage whose polarity is inverted to four horizontal periods using the POL. At this time, the data voltages having the same polarity are applied to the first and second liquid crystal cells (1, 2), and the third and fourth liquid crystal cells (3, 4) are applied to the first and second liquid crystal cells , ≪ / RTI > (2)). In addition, the first and second liquid crystal cells (1, 2) arranged at diagonal positions to each other are connected to the third and fourth liquid crystal cells (3, 4) Are applied with a data voltage of the same polarity.

That is, in the embodiment, the data driving circuit 103 inverts the polarity of the data voltage in four horizontal periods, but the liquid crystal cells are driven in the vertical two-dot inversion driving mode. Accordingly, the embodiment can reduce the power consumption and heat generation of the data driving circuit 103 more than when the vertical or horizontal two-dot inversion driving is performed. Of course, the embodiment is advantageous in that the image degradation phenomenon such as vertical / horizontal crosstalk or afterimage is reduced as compared with an inversion driving method such as a 4-dot inversion or a line inversion driving, as is known from the application of the 2-dot inversion driving.

Meanwhile, the present invention can improve the color distortion phenomenon and the dim phenomenon which are generated in the liquid crystal display device using the conventional DRD panel.

First, in the conventional liquid crystal display device, the color distortion phenomenon is caused by the intensification of the luminance of the liquid crystal cell of a specific color for each RGB color. The lowering of the luminance of the liquid crystal cell occurs when the input data voltage is the polarity of the previous data and the inverted data voltage because the polarity is inverted and the charge / discharge time is needed more than when the same polarity is maintained.

Referring to Table 1 and FIG. 4, the embodiment is reversed when the polarity of the data voltage is supplied from the second liquid crystal cell (2) to the third liquid crystal cell (3). Therefore, the luminance of the liquid crystal cells corresponding to the third liquid crystal cell (3) is lowered according to the charge / discharge time delay, but it is understood that the number of the liquid crystal cells (3) is the same for each RGB color. Therefore, the embodiment can prevent a color distortion phenomenon in which only the luminance of a specific color is lowered in RGB colors.

In addition, the embodiment can reduce the dim phenomenon that has occurred in the conventional liquid crystal display device. In Table 1, the third liquid crystal cell (3) in which the luminance is lowered is indicated by a dotted line. Referring to Table 1, it can be seen that the third liquid crystal cells (3) in the embodiment are arranged in such a manner that not only the numbers of the third liquid crystal cells (R, G, and B) are the same, but are alternately arranged in the respective vertical lines. Therefore, in the embodiment, since the normal fourth liquid crystal cell (4) and the third liquid crystal cell (3) in which the luminance is not lowered are alternately arranged, there is an effect that the horizontal or vertical dim phenomenon is reduced.

As described above, according to the embodiment of the present invention, the polarity of the data voltage is inverted in four horizontal periods, power consumption and heat generation can be reduced as compared with the two-dot inversion driving, and the luminance can be uniformized for each RGB color, The vertical dim phenomenon can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

100: liquid crystal panel 101: timing controller
102: Data modulation logic circuit 103: Data driving circuit
104: Gate drive circuit

Claims (5)

a liquid crystal panel including m × n liquid crystal cells defined by intersections of m / 2 data lines and 2n (m, n is a natural number) gate lines, and TFTs connected to the liquid crystal cells;
A data driving circuit for supplying a data voltage to the data lines in response to a polarity control signal;
And a gate driving circuit outputting a plurality of scan signals for driving the gate lines;
The liquid crystal cells are supplied with the data voltage in the order of the first to fourth liquid crystal cells,
The first liquid crystal cell is disposed at the upper left of the first intersection where the odd data lines and the four gate lines intersect and is disposed at the upper right of the second intersection where the even data lines intersect with the four gate lines,
Wherein the second liquid crystal cell is disposed at a lower left end of the first intersection and is disposed at a lower right end of the second intersection,
Wherein the third liquid crystal cell is disposed at a right upper end of the first intersection and is disposed at a left upper end of the second intersection,
Wherein the fourth liquid crystal cell is disposed at a lower right end of the first intersection and is disposed at a lower left end of the second intersection. The method according to claim 1,
The gate drive circuit
Sequentially outputting the plurality of scan signals to the odd gate lines and sequentially supplying the odd gate lines to the even gate lines;
And the plurality of scan signals are alternately supplied to the odd gate lines and the even gate lines. The method according to claim 1,
Wherein a data voltage having the same polarity is applied to the first and second liquid crystal cells and a data voltage having a polarity opposite to that of the first and second liquid crystal cells is applied to the third and fourth liquid crystal cells Liquid crystal display device. The method of claim 3,
The first and second liquid crystal cells arranged diagonally to each other are supplied with a data voltage having the same polarity,
And data voltages having the same polarity are applied to the third and fourth liquid crystal cells arranged diagonally to each other. The method according to claim 1,
Wherein the polarity control signal is phase-inverted in four horizontal periods.

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