KR102013381B1 - Gamma Reference Voltage Generation Circuit And Liquid Crystal Display Including It - Google Patents

Abstract

A gamma reference voltage generation circuit according to the present invention includes: a common gamma reference voltage generator for generating a common gamma reference voltage by dividing a power supply voltage through a common gamma string; And an R offset applying circuit for generating an R target gamma reference voltage by applying a first offset to the common gamma reference voltage, and a G for generating a G target gamma reference voltage by applying a second offset to the common gamma reference voltage. And a target gamma reference voltage generator including an offset applying circuit and a B offset applying circuit for generating a B target gamma reference voltage by applying a third offset to the common gamma reference voltage.

Description

Gamma Reference Voltage Generation Circuit And Liquid Crystal Display Including It}

The present invention relates to a liquid crystal display device, and more particularly, to a gamma reference voltage generation circuit and a liquid crystal display device including the same.

Liquid crystal display devices have a wide range of applications ranging from notebook computers, monitors, spacecrafts, aircrafts, etc. to the advantages of low power consumption and low power consumption. The liquid crystal display device includes a lower substrate on which a thin film transistor array is formed, an upper substrate on which a color filter array is formed, and a liquid crystal layer formed between the lower substrate and the upper substrate. The liquid crystal display displays an image by adjusting the arrangement of the liquid crystal layer according to the data voltage for each gray level of the video data.

In general, gradation means dividing the amount of light felt by human vision in stages. Human vision reacts nonlinearly to the brightness of light according to Weber's law. When the brightness of light is recorded linearly within a limited amount of information, the change of light does not feel smooth to the human eye. It is necessary to non-linearly encode the brightness of light in order to achieve optimal image quality within the limits of a given information expression. To this end, a task of matching a difference between driving characteristics of a display panel and human visual perception characteristics is performed, which is called gamma correction. In general, the gamma correction method sets a plurality of gamma reference voltage values differently according to characteristics of the display panel, divides the set gamma reference voltage values, and matches each of the input digital video data.

Gamma reference voltage values are generated in a gamma reference voltage generating circuit. There are two methods of generating gamma reference voltages, an integrated gamma method and an independent gamma method. The integrated gamma method generates one type of gamma reference voltage regardless of R (red), G (green), and B (blue). In the case of the integrated gamma method, white color coordinate correction is not possible. In contrast, the independent gamma method generates gamma reference voltage values separately for each of R (red), G (green), and B (blue), thereby allowing white color coordinate correction.

The gamma reference voltage generation circuit of the independent gamma method implements independent gamma by forming a separate gamma string for each of R / G / B. Therefore, in the conventional gamma reference voltage generator circuit, a total of six gamma strings are required as shown in FIG. 1 in consideration of polarities (+ and-) for inversion driving. In FIG. 1, gamma strings 1, 3, and 5 divide R_Pos, G_Pos, and B_Pos, respectively, to generate gamma reference voltages Vp1 to Vpn of positive polarity. Gamma strings 2, 4, and 6 divide R_Neg, G_Neg, and B_Neg, respectively, to generate gamma reference voltages Vn1 to Vnn of negative polarity.

Since the gamma string includes resistors for voltage dividers connected in series, when a separate gamma string is applied to each of R / G / B to implement independent gamma as in the related art, the size of the gamma reference voltage generation circuit is inevitably increased.

Accordingly, an object of the present invention is to provide a gamma reference voltage generation circuit and a liquid crystal display including the same, which can reduce the number of gamma strings for implementing independent gamma.

In order to achieve the above object, a gamma reference voltage generation circuit according to an embodiment of the present invention includes a common gamma reference voltage generator for generating a common gamma reference voltage by dividing a power supply voltage through a common gamma string; And an R offset applying circuit for generating an R target gamma reference voltage by applying a first offset to the common gamma reference voltage, and a G for generating a G target gamma reference voltage by applying a second offset to the common gamma reference voltage. And a target gamma reference voltage generator including an offset applying circuit and a B offset applying circuit for generating a B target gamma reference voltage by applying a third offset to the common gamma reference voltage.

The R offset applying circuit, the G offset applying circuit and the B offset applying circuit each include an op amp; A first variable resistor connected to the inverting input terminal of the op amp; A first switch connected between the first variable resistor and a base voltage input terminal; A second switch connected between the first variable resistor and the subtracted reference voltage input terminal; A first resistor connected between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier; A third switch connected between the non-inverting input terminal of the operational amplifier and the input terminal of the common gamma reference voltage; A second variable resistor connected between the non-inverting input terminal of the op amp and the input terminal of the common gamma reference voltage; A fourth switch connected between the non-inverting input terminal of the op amp and the second variable resistor; A second resistor connected between the non-inverting input terminal of the op amp and the base voltage input terminal; And a fifth switch connected between the non-inverting input terminal of the op amp and the second resistor.

The target gamma reference voltage output from the output terminal of the op amp may be changed according to the first variable resistor while the first, third, and fifth switches are turned on and the second, fourth, and fifth switches are turned off. It is adjusted to a value equal to or greater than the common gamma reference voltage.

The target gamma reference voltage output from the output terminal of the op amp includes the first and second variable resistors while the first, third, and fifth switches are turned off and the second, fourth, and fifth switches are turned on. And a value equal to or less than the common gamma reference voltage according to the subtraction reference voltage.

The first and second variable resistors are programmable set to be linked to an input register value.

In addition, the liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel for displaying an image; A gamma reference voltage generation circuit for generating a target gamma reference voltage for each R / G / B; A data driving circuit for generating a plurality of gamma compensation voltages by dividing the target gamma reference voltage, selecting a gamma compensation voltage corresponding to input digital video data as a data voltage, and supplying the gamma compensation voltages to data lines of the liquid crystal display panel; And a gate driving circuit configured to select a horizontal pixel line to which the data voltage is supplied by supplying scan pulses to gate lines of the liquid crystal display panel; The gamma reference voltage generation circuit includes a common gamma reference voltage generator for generating a common gamma reference voltage by dividing a power supply voltage through a common gamma string; And an R offset applying circuit for generating an R target gamma reference voltage by applying a first offset to the common gamma reference voltage, and a G for generating a G target gamma reference voltage by applying a second offset to the common gamma reference voltage. And a target gamma reference voltage generator having an offset applying circuit and a B offset applying circuit for generating a B target gamma reference voltage by applying a third offset to the common gamma reference voltage.

According to the present invention, one common gamma reference voltage generated through a common gamma string is commonly input to three offset applying circuits corresponding to R / G / B to independently generate a target gamma reference voltage for each R / G / B. do. In the past, six gamma strings were required to implement independent gamma for each R / G / B considering polarity, whereas the present invention can implement independent gamma for each R / G / B with only two gamma strings. The size and manufacturing cost of the reference voltage generating circuit can be greatly reduced.

1 is a diagram illustrating six gamma strings for implementing independent gamma in a conventional gamma reference voltage generator.
2 is a view showing a liquid crystal display device according to an embodiment of the present invention.
3 is a diagram illustrating a configuration of a gamma reference voltage generator circuit.
4 is a diagram illustrating an example of a common gamma reference voltage generator and a target gamma reference voltage generator illustrated in FIG. 3.
FIG. 5 is a diagram illustrating a configuration of each of the offset applying circuits shown in FIG. 4. FIG.
6 shows an on / off control state for switches in an offset application circuit for offset value addition and offset value subtraction.
7 illustrates an example of programmably adjusting the variable resistors in the offset applying circuit.
FIG. 8 is a diagram illustrating an example in which positive gamma reference voltages are generated differently for each R / G / B by adjusting an offset value for each R / G / B.
9 is a view showing a gamma output simulation result according to the application of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 9.

2 shows a liquid crystal display according to an embodiment of the present invention.

2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10, a gamma reference voltage generation circuit 12, a data driving circuit 14, a gate driving circuit 16, and a timing controller ( 18).

The liquid crystal display panel 10 has a liquid crystal layer formed between two glass substrates. The liquid crystal display panel 10 includes a plurality of liquid crystal cells Clc arranged in a matrix by a cross structure of a plurality of data lines DL and a plurality of gate lines GL. Data lines DL, gate lines GL, TFTs, and a storage capacitor Cst are formed on the lower glass substrate of the liquid crystal display panel 10. The liquid crystal cells Clc are connected to the TFT and are driven by an electric field between the pixel electrodes 1 and the common electrode 2. The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 10. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and is formed in IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed.

The liquid crystal cells Clc include a plurality of R (red) liquid crystal cells, G (green) liquid crystal cells, and B (blue) liquid crystal cells. The R liquid crystal cell includes an R color filter, the G liquid crystal cell includes a G color filter, and the B liquid crystal cell includes a B color filter. One R pixel, one G liquid crystal cell, and one B liquid crystal cell are included in one unit pixel. The liquid crystal display panel 10 may be implemented in any form, such as a transmissive type, a transflective type, or a reflective type. In the transmissive and transflective types, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 18 uses a timing signal such as a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable signal DE, and a dot clock DCLK supplied from a system (not shown). A data control signal DDC for controlling the operation timing of the furnace 12 and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13 are generated. The data control signal DDC is based on a source start pulse SSP, a rising edge or a falling edge indicating the sampling start point of the digital video data RGB in the data driving circuit 12. The source sampling clock SSC instructing the latching operation of the digital video data RGB in the data driving circuit 12, the source output enable signal SOE indicative of the output of the data driving circuit 12, and the liquid crystal display. And a polarity control signal POL for controlling the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the panel 10. The gate control signal GDC is input to a gate start pulse GSP indicating a start horizontal line at which scanning starts in one vertical period in which one screen is displayed, and a gate start pulse GSP input to a shift register in the gate driving circuit 13. ) Is a timing control signal for sequentially shifting the?), The gate shift clock signal GSC generated at a pulse width corresponding to the ON period of the TFT, and the gate output enable signal instructing the output of the gate driving circuit 13. It includes (GOE).

In addition, the timing controller 18 arranges the digital video data RGB supplied from the system to the data driving circuit 12 in alignment with the pixel arrangement of the liquid crystal display panel 10.

The gamma reference voltage generation circuit 12 generates common gamma reference voltages through a common gamma string, and then applies the common gamma reference voltages to an R offset applying circuit to generate R target gamma reference voltages GMA_R. The common gamma reference voltages are applied to the G offset applying circuit to generate G target gamma reference voltages GMA_G, and the common gamma reference voltages are applied to the B offset applying circuit to generate B target gamma reference voltages GMA_B. . The R / G / B target gamma reference voltages GMA_R, GMA_G, and GMA_B include positive polarity target gamma reference voltages and negative polarity target gamma reference voltages, respectively. The gamma reference voltage generation circuit 12 may further include an offset applying circuit for each R / G / B, thereby reducing the number of gamma strings for implementing independent gamma to one third of the existing gamma string.

The data driving circuit 14 divides the target gamma reference voltages GMA_R, GMA_G, and GMA_B from the gamma reference voltage generation circuit 12 to generate a plurality of gamma compensation voltages for each R / G / B. The data driving circuit 14 selects a gamma compensation voltage for each R / G / B corresponding to the input digital video data RGB in response to the data control signal DDC, and then uses the gamma compensation voltage as the data voltage to form a liquid crystal. The data lines DL of the display panel 10 are supplied.

The gate driving circuit 16 generates a scan pulse for selecting a horizontal pixel line of the liquid crystal display panel 10 to which a data voltage is supplied, according to the gate control signal GDC, and transmits the scan pulse to the gate lines GL. Supply in line sequential manner. To this end, the gate driving circuit 16 includes a shift register, a level shifter for converting the output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell Clc, and an output circuit connected between the level shifter and the gate line. Each includes. Some circuits of the gate driving circuit 16 may be directly formed on the lower glass substrate of the liquid crystal display panel 10 by a gate-driver in panel (GIP) method.

Meanwhile, the gamma reference voltage generation circuit 12, the data driving circuit 14, the gate driving circuit 16, and the timing controller 18 may be embedded in one integrated driver IC 20.

3 shows the configuration of the gamma reference voltage generating circuit 12.

Referring to FIG. 3, the gamma reference voltage generation circuit 12 includes a common gamma reference voltage generator 121 generating a plurality of common gamma reference voltages VIN0 to VINn, and the common gamma reference voltages VIN0 to. A target gamma reference that individually generates R target gamma reference voltages VIN0_R to VINn_R, G target gamma reference voltages VIN0_G to VINn_G, and B target gamma reference voltages VIN0_B to VINn_B by adding or subtracting an offset to VINn. The voltage generator 122 is provided.

The common gamma reference voltage generator 121A divides the first power supply voltage VGMP through the first common gamma string to generate the first common gamma reference voltages VIN0 to VINn to generate the first common gamma reference voltage generator 121A. And a second common gamma reference voltage generator 121B for dividing the second power supply voltage VGMN through the second common gamma string to generate common gamma reference voltages VIN0 to VINn.

The target gamma reference voltage generator 122 includes a first target gamma reference voltage generator 122A and a second target gamma reference voltage generator 122B each including an offset application circuit for each R / G / B.

The first target gamma reference voltage generator 122A adds or subtracts a first offset from the common gamma reference voltages VIN0 to VINn input from the first common gamma reference voltage generator 121A to generate a positive R target gamma reference voltage. And (+) GMA_R, VIN0_R to VINn_R, and by adding or subtracting a second offset to the common gamma reference voltages VIN0 to VINn, the positive G target gamma reference voltages ((+) GMA_G, VIN0_G to VINn_G ) And add and subtract a third offset to the common gamma reference voltages VIN0 to VINn to generate positive B target gamma reference voltages (+) GMA_B and VIN0_B to VINn_B. The first target gamma reference voltage generator 122A includes an R offset applying circuit for generating positive R target gamma reference voltages ((+) GMA_R, VIN0_R to VINn_R), and G target gamma reference voltages of positive polarity (+ ) And a G offset applying circuit for generating GMA_G, VIN0_G to VINn_G), and a B offset applying circuit for generating positive B target gamma reference voltages (+) GMA_B, VIN0_B to VINn_B.

The second target gamma reference voltage generator 122B adds or subtracts a first offset from the common gamma reference voltages VIN0 to VINn input from the second common gamma reference voltage generator 121B, thereby providing a negative R target gamma reference. Generating voltages (−) GMA_R, VIN0_R to VINn_R, and subtracting a second offset to the common gamma reference voltages VIN0 to VINn to negative G target gamma reference voltages ((-) GMA_G, VIN0_G ˜VINn_G), and a third offset is added to the common gamma reference voltages VIN0 to VINn to generate negative B target gamma reference voltages (−) GMA_B and VIN0_B to VINn_B. The second target gamma reference voltage generator 122B includes an R offset applying circuit for generating the negative R target gamma reference voltages (−) GMA_R and VIN0_R to VINn_R, and the negative G target gamma reference voltages ( A G offset applying circuit for generating (-) GMA_G, VIN0_G to VINn_G), and a B offset applying circuit for generating negative B target gamma reference voltages ((-) GMA_B, VIN0_B to VINn_B).

4 illustrates an example of the common gamma reference voltage generator 121 and the target gamma reference voltage generator 122 illustrated in FIG. 3.

Referring to FIG. 4, the common gamma reference voltage generator 121 may include eight positive common gamma reference voltages through a first common gamma string connected between a first power supply voltage VGMP and a ground voltage GND. In addition to generating VIN0 to VIN7, eight negative common gamma reference voltages VIN0 to VIN7 are generated through the second common gamma string connected between the second power supply voltage VGMN and the ground voltage GND. can do. Here, VIN1 to VIN6 may be adjusted such that their value is programmable according to the selection signal SEL applied from the outside. That is, VIN1 to VIN6 may be applied to the selector 8 to 1 Sel with eight different values, respectively, and then may be selected to any one of eight values according to the selection signal SEL.

The target gamma reference voltage generator 122 includes eight positive R target gamma reference voltages VIN0_R to VIN7_R including eight positive offset applying circuits OCR, OGG, and OBC for each R / G / B. , Eight positive G target gamma reference voltages VIN0_G to VIN7_G, and eight positive B target gamma reference voltages VIN0_B to VIN7_B are generated according to the white color coordinate target. In addition, the target gamma reference voltage generator 122 includes eight negative R target gamma reference voltages VIN0_R to eight negative offset applying circuits OCR, OGG, and OBC for each R / G / B. VIN7_R), eight negative G target gamma reference voltages (VIN0_G to VIN7_G), and eight negative B target gamma reference voltages (VIN0_B to VIN7_B) are generated for the white color coordinate target.

As described above, the present invention commonly inputs one common gamma reference voltage generated through the common gamma string to three offset applying circuits corresponding to R / G / B to input the target gamma reference voltage for each R / G / B. Occurs independently. In the related art, six gamma strings were required to implement independent gamma for each R / G / B considering polarity, whereas the present invention further includes offset applying circuits, so that the two gamma strings are independent for R / G / B. Gamma can be implemented.

FIG. 5 shows a configuration of each of the offset applying circuits OCR, OGG, and OBB shown in FIG. 4. 6 shows an on / off control state for switches in an offset application circuit for offset value addition and offset value subtraction. 7 shows an example of programmably adjusting the variable resistors in the offset applying circuit.

The R / G / B offset applying circuits OCR, OGG, and OBC of FIG. 4 are configured in the same manner as in FIG. 5. Referring to FIG. 5, the offset applying circuit includes a first variable resistor VR1 and a first variable resistor VR1 connected to an op amp (OP-Amp, OA), an inverting input terminal (-) of the op amp (OA). The first switch SW1 connected between the ground voltage GND input terminal, the second switch SW2 connected between the first variable resistor VR1 and the subtraction reference voltage Vx, and the op amp. Between the first resistor R1 connected between the inverting input terminal (-) of the OA and the output terminal (the output of Vout), the non-inverting input terminal (+) of the operational amplifier (OA), and the common gamma reference voltage (VINn) input terminal. The second variable resistor VR2 connected between the third switch SW3 connected to the second switch SW3, the non-inverting input terminal (+) of the operational amplifier OA, and the common gamma reference voltage VINn input terminal, and the operational amplifier OA. The fourth switch SW4 connected between the non-inverting input terminal (+) and the second variable resistor VR2 of the amplifier, and the non-inverting input terminal (+) and the ground voltage (GND) input terminal of the operational amplifier OA. Inverse of the second resistor R2 and the op amp OA The fifth switch SW5 is connected between the previous input terminal (+) and the second resistor (R2).

The target gamma reference voltage Vout output from the offset applying circuit may be adjusted up and down based on the common gamma reference voltage VINn according to the switch control shown in FIG. 6. The target gamma reference voltage Vout is represented by the following equation while the first and third switches SW1 and SW3 are turned on and the second, fourth and fifth switches SW2, SW4 and SW5 are turned off. It becomes like 1.

According to Equation 1, the target gamma reference voltage Vout may be adjusted to a value equal to or greater than the common gamma reference voltage VINn according to the first variable resistor VR1. The user may set the target gamma reference voltage Vout to a desired value by appropriately adjusting the first variable resistor VR1 with on / off control of the switches SW1 to SW5 during gamma tuning.

The target gamma reference voltage Vout is represented by the following equation while the first and third switches SW1 and SW3 are turned off and the second, fourth and fifth switches SW2, SW4 and SW5 are turned on. It becomes like 2. Equation 2 is a result of assuming that the first and second variable resistors VR1 and VR2 are identical to each other and the first and second resistors R1 and R2 are identical to each other.

According to Equation 2, the target gamma reference voltage Vout is equal to or smaller than the common gamma reference voltage VINn according to the first and second variable resistors VR1 and VR2 and the subtraction reference voltage Vx. Can be adjusted. In gamma tuning, the user adjusts the first and second variable resistors VR1 and VR2 and the subtraction reference voltage Vx as well as the on / off control of the switches SW1 to SW5 to adjust the target gamma reference voltage Vout. ) Can be set to the desired value.

In Equations 1 and 2, the first and second variable resistors VR1 and VR2 may be adjusted in hardware according to a user's physical manipulation.

In addition, in Equations 1 and 2, the first and second variable resistors VR1 and VR2 may be adjusted in software according to a built-in register value. To this end, the first and second variable resistors VR1 and VR2 may be designed and programmable in the driver IC to be interlocked with the input register value. 7 shows an example of controlling with a 3-bit register. In this case, the registers of FIG. 7 are required as many as (maximum value of n in VINn + 1) x 3 (R / G / B) x 2 (Positive / Negative).

Referring to FIG. 7, the first and second variable resistors VR1 and VR2 may be adjusted differently according to a resistor value. As a result, the target gamma reference voltage (Vout) is adjusted to be 0.8, 0.85, 0.9 and 0.95 times the common gamma reference voltage (VINn) or 1.05 times, 1.1 and 1.15 times the common gamma reference voltage (VINn). Can be adjusted to be larger. In addition, the target gamma reference voltage Vout may be adjusted to be the same as the common gamma reference voltage VINn.

FIG. 8 shows an example in which positive gamma reference voltages are generated differently for each R / G / B by adjusting an offset value for each R / G / B.

In FIG. 8, nine positive common gamma reference voltages VIN1 to VIN9 are generated through one common gamma string, and common gamma reference voltages VIN1 to VIN9 using an offset application circuit for each R / G / B. ) Offset for each R / G / B.

For example, in a positive high gradation, when the target gamma reference voltage for white color coordinate correction is 5.21 / 5.30 / 5.11 V for each of R / G / B, the present invention provides a common gamma reference of 5.21 V through a common gamma string. An R offset application circuit for generating a voltage VIN1 and applying this (VIN1) to an offset of 0 V, a G offset application circuit for applying an offset of +0.09 V, and a B offset for applying an offset of -0.1 V Commonly input to the application circuit, it is possible to generate a target gamma reference voltage for each R / G / B of 5.21 / 5.30 / 5.11V.

Also, in the positive halftone, when the target gamma reference voltage for white color coordinate correction is 2.56 / 2.75 / 2.36 V for each of R / G / B, the present invention provides a common gamma reference voltage of 2.56 V through the common gamma string. A V offset applying circuit for applying an offset of 0V, a G offset applying circuit for applying an offset of + 0.19V, and a B offset applying circuit for applying an offset of -0.18V. By inputting in common, R / G / B target gamma reference voltage of 2.56 / 2.75 / 2.36V can be generated.

Further, in the positive low gray level, when the target gamma reference voltage for white color coordinate correction is 0.85 / 0.94 / 0.75 V for each of R / G / B, the present invention provides a common gamma reference voltage of 0.85V through the common gamma string. VIN8), R offset applying circuit for applying offset of 0V, G offset applying circuit for applying offset of + 0.09V, and B offset applying circuit for applying offset of -0.1V. Commonly input to, a target gamma reference voltage for each R / G / B of 0.85 / 0.94 / 0.75 V can be generated.

9 shows a gamma output simulation result according to the application of the present invention.

Applicant generated the positive and negative gamma reference voltages using the common gamma string and the offset application circuit as described above, calculates the output based on the same, and compares the output with the target output for white color coordinate matching. Experimentally, the output of the present invention was exactly matched to the target output as shown in FIG. As can be easily seen through these results, the present invention can easily implement the independent gamma while reducing the number of gamma string to the existing 1/3.

As described above, in the present invention, one common gamma reference voltage generated through the common gamma string is input to three offset applying circuits corresponding to R / G / B in common so that the target gamma reference voltage is R / G /. It occurs independently for each B. In the past, six gamma strings were required to implement independent gamma for each R / G / B considering polarity, whereas the present invention can implement independent gamma for each R / G / B with only two gamma strings. The size and manufacturing cost of the reference voltage generating circuit can be greatly reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

10 liquid crystal display panel 12 gamma reference voltage generation circuit
14 data driving circuit 16 gate driving circuit
18: timing controller 121: common gamma reference voltage generator
122: target gamma reference voltage generator

Claims (10)

A common gamma reference voltage generator for generating a common gamma reference voltage by dividing a power supply voltage through a common gamma string; And
An R offset applying circuit for generating an R target gamma reference voltage by applying a first offset to the common gamma reference voltage under switch control, and a G target gamma by applying a second offset to the common gamma reference voltage under switch control A target gamma reference voltage generator including a G offset applying circuit for generating a reference voltage and a B offset applying circuit for generating a B target gamma reference voltage by applying a third offset to the common gamma reference voltage according to a switch control. A gamma reference voltage generator circuit, characterized in that. The method of claim 1,
Each of the R offset applying circuit, the G offset applying circuit, and the B offset applying circuit,
Op amp;
A first variable resistor connected to the inverting input terminal of the op amp;
A first switch connected between the first variable resistor and a base voltage input terminal;
A second switch connected between the first variable resistor and the subtracted reference voltage input terminal;
A first resistor connected between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier;
A third switch connected between the non-inverting input terminal of the operational amplifier and the input terminal of the common gamma reference voltage;
A second variable resistor connected between the non-inverting input terminal of the op amp and the input terminal of the common gamma reference voltage;
A fourth switch connected between the non-inverting input terminal of the op amp and the second variable resistor;
A second resistor connected between the non-inverting input terminal of the op amp and the base voltage input terminal; And
And a fifth switch connected between the non-inverting input terminal of the op amp and the second resistor. The method of claim 2,
The target gamma reference voltage output from the output terminal of the op amp is
The common gamma reference voltage is equal to or equal to the common gamma reference voltage according to the first variable resistor when the first, third, and third switches are turned on and the second, fourth, and fifth switches are turned off. A gamma reference voltage generator circuit, characterized in that it is adjusted to a larger value. The method of claim 2,
The target gamma reference voltage output from the output terminal of the op amp is
The common gamma reference voltage is equal to the common gamma reference voltage according to the first and second variable resistors and the subtraction reference voltage while the first and third switches are turned off and the second, fourth and fifth switches are turned on. Or, the gamma reference voltage generator circuit is adjusted to a value smaller than the common gamma reference voltage. The method of claim 2,
And the first and second variable resistors are programmed to be interlocked with an input resistor value. A liquid crystal display panel for displaying an image;
A gamma reference voltage generation circuit for generating a target gamma reference voltage for each R / G / B;
A data driving circuit for generating a plurality of gamma compensation voltages by dividing the target gamma reference voltage, selecting a gamma compensation voltage corresponding to input digital video data as a data voltage, and supplying the gamma compensation voltages to data lines of the liquid crystal display panel; And
A gate driving circuit configured to select a horizontal pixel line to which the data voltage is supplied by supplying scan pulses to gate lines of the liquid crystal display panel;
The gamma reference voltage generator circuit,
A common gamma reference voltage generator for generating a common gamma reference voltage by dividing a power supply voltage through a common gamma string; And
An R offset applying circuit for generating an R target gamma reference voltage by applying a first offset to the common gamma reference voltage under switch control, and a G target gamma by applying a second offset to the common gamma reference voltage under switch control A target gamma reference voltage generator having a G offset applying circuit for generating a reference voltage and a B offset applying circuit for generating a B target gamma reference voltage by applying a third offset to the common gamma reference voltage according to a switch control. Liquid crystal display characterized in that. The method of claim 6,
Each of the R offset applying circuit, the G offset applying circuit, and the B offset applying circuit,
Op amp;
A first variable resistor connected to the inverting input terminal of the op amp;
A first switch connected between the first variable resistor and a base voltage input terminal;
A second switch connected between the first variable resistor and the subtracted reference voltage input terminal;
A first resistor connected between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier;
A third switch connected between the non-inverting input terminal of the operational amplifier and the input terminal of the common gamma reference voltage;
A second variable resistor connected between the non-inverting input terminal of the op amp and the input terminal of the common gamma reference voltage;
A fourth switch connected between the non-inverting input terminal of the op amp and the second variable resistor;
A second resistor connected between the non-inverting input terminal of the op amp and the base voltage input terminal; And
And a fifth switch connected between the non-inverting input terminal of the op amp and the second resistor. The method of claim 7, wherein
The target gamma reference voltage output from the output terminal of the op amp is
The common gamma reference voltage is equal to or equal to the common gamma reference voltage according to the first variable resistor when the first, third, and third switches are turned on and the second, fourth, and fifth switches are turned off. Liquid crystal display device characterized in that the adjustment to a larger value. The method of claim 7, wherein
The target gamma reference voltage output from the output terminal of the op amp is
The common gamma reference voltage is equal to the common gamma reference voltage according to the first and second variable resistors and the subtraction reference voltage while the first and third switches are turned off and the second, fourth and fifth switches are turned on. Or a value smaller than the common gamma reference voltage. The method of claim 7, wherein
And the first and second variable resistors are programmablely set to be linked to an input register value.

Images