KR101970798B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device, which includes a data driver for outputting a reference voltage to data lines and then outputting a data voltage to the data lines, And a gate driver sequentially outputting two gate pulses to the gate lines and shifting the first and second gate pulses. The reference voltage is a precharge voltage having the same potential as a common voltage applied to the pixels or a charge sharing voltage generated when the data lines are short-circuited. The pixels precharge the reference voltage in response to the first gate pulse and then charge the reference voltage in response to the second gate pulse and then charge the data voltage.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as " TFT ") as a switching element. Liquid crystal cells of a liquid crystal display display an image by changing the transmittance according to the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode.

The pixels of the liquid crystal display charge the data voltage for one horizontal period and maintain the data voltage for one frame period. One horizontal period of the liquid crystal display device is inversely proportional to the frame rate. For example, in a liquid crystal display of FHD (1920 * RGB * 1080) resolution, one horizontal period (1H in FIG. 1A) is approximately 14.9 μs when the frame frequency is 60 Hz. In a liquid crystal display device of the same resolution, if the frame rate is 120 Hz, one horizontal period (1H in Fig. 1B) is approximately 7.2 mu s. If the frame rate is 240 Hz, one horizontal period (1H in Fig. 1C) is approximately 3.3 mu s. 1A to 1C, 'G1 to Gn' are gate lines of the liquid crystal display panel, and pulse signals are gate pulses sequentially applied to the gate lines G1 to Gn. As shown in FIGS. 1A to 1C, as the frame rate of the liquid crystal display device increases, the data voltage charging time of the pixels becomes insufficient as shown in FIG. In FIG. 2, 'Vdata' is a data voltage output from the source drive IC (integrated circuit), and 'Vgate' is a gate pulse synchronized with the data voltage (Vdata). 'Vpix' is the data voltage charged in the pixel.

The frame rate of a liquid crystal display device is increasing in high-resolution products. As the frame rate increases, crosstalk, flicker, vertical / horizontal line noise, and smudge may appear due to insufficient data voltage charging of the pixels.

To obtain a pre-charge effect, the pixel may be charged with the data voltage to be displayed after the previous data voltage is charged to the pixel. However, in the precharge method, since the precharge voltage of a pixel changes depending on the polarity and the voltage level of the previous data voltage, it is difficult to uniformly control the charging characteristics of the pixels.

The present invention provides a liquid crystal display device capable of reducing the charge amount drop of pixels when the frame rate is raised and making charging characteristics of pixels uniform.

A liquid crystal display of the present invention includes: a display panel in which data lines and gate lines are crossed and pixels are arranged in a matrix type; A data driver for outputting a data voltage to the data lines during a low logic period of the source output enable signal after outputting a reference voltage to the data lines in response to a pulse of the source output enable signal; A gate driver for sequentially outputting first and second gate pulses to the gate lines within one frame period in response to a gate timing control signal and shifting the first and second gate pulses; And a timing controller for supplying data of the dummy data and the input image to the data driver and generating the source output enable signal and the gate timing control signal to control the operation timing of the data driver and the gate driver.

The reference voltage is a precharge voltage having the same potential as a common voltage applied to the pixels or a charge sharing voltage generated when the data lines are short-circuited.
The first gate pulse P1 applied to the Nth (N is an integer equal to or greater than 3) gate line is synchronized with the (N-2) th data voltage and the reference voltage. And a second gate pulse applied to the Nth gate line is synchronized with the reference voltage and the N data voltage. The pixels charge the reference voltage after charging the N-2 data voltage in response to the first gate pulse and then charge the reference voltage in response to the second gate pulse, .

The liquid crystal display of the present invention sequentially supplies first and second gate pulses to each of the gate lines to precharge the pixels with the reference voltage and then charges the pixels with the data voltage to be displayed. As a result, the liquid crystal display of the present invention can increase the charge amount of the pixels when the frame rate rises, and can uniformly control the charge characteristics of the pixels as compared with the prior art.

1A to 1C are waveform diagrams showing one horizontal period in inverse proportion to the frame rate.
Fig. 2 is a waveform diagram showing a lack of charge amount of pixels that become insufficient as the frame rate increases.
3 is a block diagram illustrating a liquid crystal display device according to an embodiment of the present invention.
4 is a waveform diagram showing gate pulses output from the gate driver shown in FIG.
FIG. 5 is a waveform diagram showing the gate pulse and the data voltage shown in FIG. 4 in detail.
6 is a waveform diagram showing one horizontal period and charging characteristics of pixels when the frame rate is 60 Hz, 120 Hz, and 240 Hz in the liquid crystal display according to the embodiment of the present invention.
7 is a circuit diagram showing a circuit for outputting the charge share voltage and the data voltage in the source drive IC.
8 is a circuit diagram showing a circuit for outputting the precharge voltage and the data voltage in the source drive IC.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

3 and 4, a liquid crystal display according to an exemplary embodiment of the present invention includes a display panel 10, a timing controller 20, a data driver 12, a gate driver 14, and the like.

In the display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel includes pixels arranged in a matrix form by an intersection structure of the data lines S1 to Sm and the gate lines G1 to Gn. The pixels are divided into a red subpixel, a green subpixel, and a blue subpixel. Each of the subpixels includes liquid crystal cells Clc, a TFT, and a storage capacitor Cst.

The pixel array in which the input image is displayed on the display panel 10 is divided into a TFT array and a color filter array. On the lower glass substrate of the display panel 10, a TFT array is formed. The TFT array includes TFTs connected to the pixel electrodes 1 of the liquid crystal cells Clc, gate lines G1 to Gn crossing the data lines S1 to Sm, data lines S1 to Sm, And a storage capacitor Cst. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the display panel 10, a color filter array including a black matrix, a color filter and the like is formed. On the upper glass substrate and the lower glass substrate of the display panel 10, an alignment film for attaching a polarizing plate and setting a pre-tilt angle of liquid crystal is formed.

The active area in which the image is displayed in the pixel array may be composed of n-2 lines including the third to n-th lines excluding the first and second lines. In this case, the first and second lines are dummy lines in which the input image is not displayed.

The common electrode 2 is supplied with the common voltage Vcom. The liquid crystal cell Clc adjusts the transmittance using liquid crystal molecules driven by an electric field generated by a potential difference between a data voltage applied to the pixel electrode 1 and a common voltage Vcom applied to the common electrode 2 . The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system.

The display panel 10 applicable to the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 20 supplies the digital video data of the input image input from the host system 30 to the data driver 12. The timing controller 20 generates dummy data for precharging the third and fourth lines of the pixel array. The dummy data is data generated in the timing controller 20 regardless of the input image data. The dummy data can be generated with the gray level value, for example, the gray level 128 data when the maximum expressible gray level is 256. [

The timing controller 20 receives a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock CLK from the host system 30. The timing controller 20 generates timing control signals for controlling the operation timing of the data driver 12 and the gate driver 14 based on the timing signal input from the host system 30. [ The timing control signals include a gate timing control signal for controlling the operation time of the gate driver 14 and a data timing control signal for controlling the operation timing of the data driver 12 and the vertical polarity of the data voltage.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP controls the operation start timing of the gate drive IC constituting the gate driver 14. [ The gate shift clock GSC controls the shift timing of the gate pulse by a clock signal commonly input to the gate drive ICs. The gate output enable signal GOE controls the output timing of the gate drive ICs. The timing controller 20 controls the gate driver 14 so that a gate pulse as shown in FIG. 4 is output using the gate timing control signal.

The data timing control signal includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, a source output enable signal SOE, and the like. The source start pulse SSP controls the data sampling start timing of the source drive ICs constituting the data driver 12. [ The source sampling clock SSC is a clock signal for controlling the sampling timing of data in each of the source drive ICs. The source output enable signal SOE controls the data voltage of the data driver 12 and the charge share voltage output timing. The charge share voltage is the average voltage of the positive and negative data voltages generated when the data lines are short-circuited. The source start pulse SSP and the source sampling clock SSC may be omitted if the interface for signal transmission between the timing controller 20 and the data driving unit 12 is mini LVDS (Low Voltage Differential Signaling).

The host system 30 may be implemented in any one of a television system, a home theater system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), and a phone system. The host system 30 scales the digital video data RGB of the input image according to the resolution of the display panel 10. The host system 30 transmits the timing signals Vsync, Hsync, DE, and MCLK to the timing controller 20 together with the digital video data RGB of the input image.

The data driver 12 includes one or more source drive ICs. Each of the source drive ICs includes a shift register, a latch, a digital-to-analog converter (DAC), an output buffer, and the like. The source driver ICs convert the dummy data input from the timing controller 20 into an analog positive / negative gamma compensation voltage to generate positive / negative dummy data voltages, and in response to the polarity control signal POL, Inverts the polarity of the voltage. Subsequently, the source drive ICs convert the data of the input image input from the timing controller 20 into an analog positive / negative gamma compensation voltage to generate positive / negative data voltages, and in response to the polarity control signal POL The polarity of the data voltage is inverted. The source drive ICs output the reference voltage in response to the source output enable signal SOE and output the positive / negative data voltages to the data lines S1 to Sm. Here, the reference voltage may be a charge sharing voltage or a preset precharge voltage. The pre-charge voltage may be set to a voltage of the same potential as the common voltage Vcom applied to the common electrode 2 of the pixels.

The gate driver 14 includes a shift register and a level shifter. The gate driver 14 generates gate pulses as shown in Fig. 4 under the control of the timing controller 20. [ The gate pulse includes first and second gate pulses P1 and P2 that are continuously generated with a predetermined time difference. The first and second gate pulses P1 and P2 are successively supplied to the gate lines G1 to Gn within one frame period. The first and second gate pulses P1 and P2 are sequentially shifted.

The first gate pulse P1 is generated with a pulse width of approximately one horizontal period (1H). The first gate pulse P1 is a gate pulse for precharging the pixels. The first gate pulse P1 applied to the Nth (N is a positive integer equal to or greater than 3) gate line is synchronized with the N-2th data voltage (or the pre-charge data voltage) and the reference voltage. The first gate pulse P1 applied to the first and second gate lines G1 and G2 which are dummy gate lines is synchronized with the dummy data voltage and the reference voltage. The TFT of the pixels is turned on in response to the second gate pulse P2 after being turned on in response to the first gate pulse P1 and turned on twice within one frame period. The dummy line TFTs are turned on according to the first gate pulse P1 to supply a reference voltage to the liquid crystal cell Clc immediately after supplying the dummy data voltage to the liquid crystal cell Clc. The TFT of the active region is turned on in accordance with the first gate pulse P1 to supply the reference voltage to the liquid crystal cell Clc immediately after supplying the dummy data voltage or the N-2th data voltage to the liquid crystal cell Clc Supply. Accordingly, the pixels pre-charge the reference voltage after pre-charging the N-2 data voltage or the dummy data voltage in response to the first gate pulse Pl.

The second gate pulse P2 is generated following the first gate pulse P1 with a time difference of 1H - t1 as shown in FIG. Here, 1H is one horizontal period. t1 is the reference voltage supply time or the pulse width of the source output enable signal SOE. The second gate pulse P2 is generated with a pulse width of approximately one horizontal period (1H). The second gate pulse P1 is a gate pulse for charging the data voltage of the input image to be displayed into the pixels. And the second gate pulse P2 applied to the Nth gate line is synchronized with the Nth data voltage. The second gate pulse P2 applied to the first and second gate lines G1 and G2 which are the dummy gate lines are synchronized with the dummy gate voltage. The TFTs of the dummy lines are turned on according to the second gate pulse P2 to supply the dummy data voltage to the liquid crystal cell Clc of the dummy lines following the reference voltage. The TFTs of the active region are turned on according to the second gate pulse P2 to supply the Nth data voltage of the input image following the reference voltage. Therefore, since the pixels always charge the data voltage with the reference voltage precharged, the data voltage can be sufficiently charged regardless of the polarity or the voltage level of the data voltage and has a uniform charging characteristic.

FIG. 5 is a waveform diagram showing the gate pulse and the data voltage shown in FIG. 4 in detail. In FIG. 5, 'Vdata' is a data voltage output from the source drive IC of the data driver 12, and 'Vgata' is a gate pulse synchronized with the data voltage Vdata. 'Vpix' is the data voltage charged in the pixel.

Referring to FIG. 5, the data driver 12 outputs the reference voltage Vref to the data lines S1 to Sm at time t1 in response to the pulse of the source output enable signal SOE. The reference voltage Vref may be the common voltage Vcom or the charge share voltage. The data driver 12 outputs the dummy data voltage or the data voltage of the input image to the data lines S1 to Sm in response to a low logic period of the source output enable signal SOE.

The gate driver 14 sequentially supplies the first and second gate pulses P1 and P2 to the gate lines G1 to Gn, respectively. The first gate pulse P1 applied to the first and second gate lines G1 and G2 which are dummy gate lines are synchronized with the dummy data voltage and synchronized with the reference voltage Vref. The first gate pulse P1 applied to the third to nth gate lines G3 to Gn is synchronized with the precharge data voltage of the input image and is synchronized with the reference voltage Vref. The first gate pulse P1 applied to the Nth gate line is overlapped with the second gate pulse P2 applied to the (N-1) th gate line by t1.

The gate driver 14 causes the second gate pulse P1 to rise after the elapse of 1H - t1 from the falling edge of the first gate pulse P1. The second gate pulse P1 applied to the first and second gate lines G1 and G2 which are dummy gate lines are synchronized with the dummy data voltage. The second gate pulse P2 applied to the third to nth gate lines G3 to Gn is synchronized with the data voltage of the input image to be displayed.

Since the pixels charge the reference voltage immediately after the dummy data voltage or the N-2th data voltage (or the pre-charge data voltage) in response to the first gate pulse P1, The reference voltage is maintained before the Nth data voltage is charged. Therefore, since the pixels always start to charge the data voltage to be displayed from the reference voltage irrespective of the polarity of the data voltage or the difference in the voltage level, the data voltage can be sufficiently charged and has a uniform charging characteristic.

6, when the data voltage to be displayed is charged into the pixels, the voltage of the pixels is raised from the reference voltage at the second gate pulse P2. Therefore, even if the frame rate rises to 120 Hz or more, The charging characteristics of the pixels can be uniformly controlled over the whole. In FIG. 6, 'Vdata' is a data voltage output from the source drive IC and 'Vgate' is a gate pulse synchronized with the data voltage (Vdata). 'Vpix' is the data voltage charged in the pixel.

The reference voltage Vref may be generated with a precharge voltage or charge share voltage having the same potential as the common voltage Vcom. The pre-charge voltage may be supplied to the source drive ICs from an external voltage source with a positive / negative gamma compensation voltage. The source drive IC turns on the second switch SW2 in response to the pulse of the source output enable signal SOE as shown in Fig. 7, thereby shorting the data lines S1 to S4. A charge sharing voltage is applied to the data lines S1 to S4 when the data lines S1 to S4 are short-circuited. The source driver IC charges and shares the data lines S1 to S4 and then turns on the first switch SW1 during the low logic period of the source output enable signal SOE to generate a digital-to-analog converter (DAC) 21 ) To the data lines (S1 to S4). In Fig. 7, reference numeral 22 denotes an output buffer for minimizing the attenuation of a signal applied to the data lines S1 to S4. Reference numeral 23 denotes an inverter for inverting the source output enable signal SOE.

The source drive IC turns on the third switch SW3 in response to the pulse of the source output enable signal SOE and outputs the precharge voltage Vpre to the data lines S1 to S4 . The pre-charge voltage may be set to a voltage of the same potential as the common voltage Vcom. Then, the source driver IC turns on the first switch SW1 during the low logic interval of the source output enable signal SOE after outputting the pre-charge voltage to turn on the first switch SW1 from the digital-to-analog converter (DAC) And outputs the polarity / negative polarity data voltages to the data lines S1 to S4.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 12: data driver
14: Gate driver 20: Timing controller

Claims (8)

A display panel in which data lines and gate lines are crossed and pixels are arranged in a matrix type;
A data driver for outputting a data voltage to the data lines during a low logic period of the source output enable signal after outputting a reference voltage to the data lines in response to a pulse of the source output enable signal;
A gate driver for sequentially outputting first and second gate pulses to the gate lines within one frame period in response to a gate timing control signal and shifting the first and second gate pulses; And
And a timing controller which supplies data of the dummy data and the input image to the data driver and controls the operation timing of the data driver and the gate driver by generating the source output enable signal and the gate timing control signal,
Wherein the reference voltage is a precharge voltage having a potential equal to a common voltage applied to the pixels or a charge sharing voltage generated when the data lines are short-
The first gate pulse P1 applied to the Nth (N is an integer equal to or greater than 3) gate line is synchronized with the (N-2) th data voltage and the reference voltage,
A second gate pulse applied to the Nth gate line is synchronized with the reference voltage and the N data voltage,
The pixels charge the reference voltage after charging the N-2 data voltage in response to the first gate pulse and then charge the reference voltage in response to the second gate pulse, Is charged. The method according to claim 1,
1 horizontal period is '1H' and a pulse width time of the source output enable signal is '1t'
And the second gate pulse is lengthened after a lapse of 1H - t1 from the falling edge of the first gate pulse. 3. The method of claim 2,
And the first gate pulse applied to the Nth gate line is overlapped with the second gate pulse applied to the (N-1) th gate line by t1. The method of claim 3,
Wherein each of the first and second gate pulses has a pulse width of one horizontal period. 5. The method of claim 4,
The timing controller includes:
Generating dummy data irrelevant to the input image and transmitting the dummy data and the data of the input image to the data driver,
Wherein the data driver converts the data of the dummy data and the input image into positive / negative data voltages and outputs the data voltages to the data lines,
The first gate pulse applied to the first and second gate lines is synchronized with the dummy data voltage and the reference voltage,
And a second gate pulse applied to the first and second gate lines is synchronized with the dummy data voltage. 6. The method of claim 5,
And the dummy data is halftone data. delete A display panel in which data lines and gate lines are crossed and pixels are arranged in a matrix type;
A data driver for outputting a data voltage to the data lines during a low logic period of the source output enable signal after outputting a reference voltage to the data lines in response to a pulse of the source output enable signal;
A gate driver for sequentially outputting first and second gate pulses to the gate lines within one frame period in response to a gate timing control signal and shifting the first and second gate pulses; And
And a timing controller which supplies data of the dummy data and the input image to the data driver and controls the operation timing of the data driver and the gate driver by generating the source output enable signal and the gate timing control signal,
Wherein the reference voltage is a precharge voltage having a potential equal to a common voltage applied to the pixels or a charge sharing voltage generated when the data lines are short-
Wherein the pixels charge the reference voltage in response to the first gate pulse and then charge the reference voltage in response to the second gate pulse and then charge the data voltage.

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