KR100525734B1 - Method for Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel that increases contrast ratio and prevents miswriting.

In the method of driving the plasma display panel, after the first voltage is supplied to at least one of the first and second electrodes, the voltage rises from the first voltage to a voltage 100 to 130 [V] higher than the first voltage. Initialize the cells by supplying an up rising ramp waveform.

Description

Driving Method for Plasma Display Panel {Method for Driving Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel to increase contrast ratio and prevent mis-writing.

Plasma Display Panels (hereinafter referred to as "PDPs") display an image including characters or graphics by emitting phosphors by ultraviolet rays of 147 nm generated upon discharge of He + Xe or Ne + Xe gas. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP lowers the voltage required for discharge by using wall charges accumulated on the surface during discharge, and has advantages of low voltage driving and long life because it protects the electrodes from sputtering caused by the discharge.

1 and 2, the discharge cells of the three-electrode AC surface discharge type PDP are formed on the scan electrodes Y1 to Yn and the sustain electrode Z formed on the upper substrate 10, and on the lower substrate 18. The formed address electrodes X1 to Xm are provided.

The discharge cells 1 of the PDP are formed at the intersections of the scan electrodes Y1 to Yn, the sustain electrodes Z and the address electrodes X1 to Xm.

Each of the scan electrodes Y1 to Yn and the sustain electrode Z includes a transparent electrode 12 and a metal bus electrode 11 having a line width smaller than that of the transparent electrode 12 and formed at one edge of the transparent electrode. The transparent electrode 12 is typically formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrode 11 is formed of a metal on the transparent electrode 12 to reduce the voltage drop caused by the transparent electrode 12 having a high resistance. The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 on which the scan electrodes Y1 to Yn and the sustain electrode Z are formed. On the upper dielectric layer 13, wall charges generated during plasma discharge are accumulated. The passivation layer 14 protects the electrodes Y1 to Yn and Z and the upper dielectric layer 13 from sputtering generated during plasma discharge and increases the emission efficiency of secondary electrons. As the protective film 14, magnesium oxide (MgO) is usually used.

The address electrodes X1 to Xm are formed on the lower substrate 18 in a direction crossing the scan electrodes Y1 to Yn and the sustain electrode Z. The lower dielectric layer 17 and the partition wall 15 are formed on the lower substrate 18. The phosphor layer 16 is formed on the surfaces of the lower dielectric layer 17 and the partition wall 15. The partition wall 15 is formed in parallel with the address electrodes X1 to Xm to physically distinguish the discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 16 is excited and emitted by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue.

An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne for discharging is injected into the discharge space of the discharge cell provided between the upper and lower substrates 10 and 18 and the partition wall 15.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. When the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. Each subfield SF1 to SF8 is divided into a reset period for initializing discharge cells, an address period for selecting discharge cells, and a sustain period for implementing gray levels according to the number of discharges. The reset period and the address period of each subfield SF1 to SF8 are the same for each subfield, while the sustain period and the number of discharges thereof are 2 ⁿ in each subfield (where n = 0,1,2,3,4). , 5,6,7).

4 shows driving waveforms used in the PDP.

Referring to FIG. 4, at the beginning of the reset period, the sustain pulse su of the sustain voltage Vs is first supplied to the scan electrodes Y, and then the sustain electrodes Z are supplied. Then, the initializing sustain pulse is supplied to the sustain electrodes Y again. These sustain pulse groups SUG serve to form initial wall charges on the electrodes X, Y, and Z in place of the setup rising ramp waveform Rsuy shown in FIG. 0 [V] is supplied to the address electrodes X while the sustain pulses (sus, isus) are supplied to the scan electrodes (Y) and the sustain electrodes (Z). Thus, when the sustain pulses (sus, isus) are supplied to the scan electrodes (Y) and the sustain electrodes (Z), the surface discharge occurs between the scan electrodes (Y) and the sustain electrodes (Z), the scan electrodes Wall charges are accumulated between (Y) and the sustain electrodes (Z). The set down falling ramp waveform Rsdy is supplied to the scan electrodes Y subsequent to the initializing sustain pulse isus. The sustain voltage Vs is supplied to the sustain electrodes Y while the set-down falling ramp waveform Rsdy is supplied to the scan electrodes Y. When the set-down falling ramp waveform Rsdy is supplied in this way, a set-down discharge occurs with a weak discharge between the scan electrodes Y and the sustain electrodes Z and between the scan electrodes Y and the address electrodes X. . This set-down discharge eliminates unnecessary wall charges unnecessary for the address discharge among the wall charges formed during the setup discharge.

In the address period, the scan pulse of the negative scan voltage Vscan is sequentially supplied to the scan electrodes Y and the data pulse of the positive data voltage Vd synchronized with the scan pulse scan. Is supplied to the address electrodes (X). As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the reset period are added, an address discharge is generated in the cell to which the data pulse data is supplied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is supplied. A sustain voltage Vs is supplied to the sustain electrode Z during this address period.

In the sustain period, sustain pulses sus are alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. The first sustain pulse (sus) has a wider pulse width than the sustain pulse generated thereafter so that the sustain discharge can be stably started. On-cells selected by the address discharge have a sustain discharge, i.e., a sustain discharge between the scan electrodes Y and the sustain electrodes Z whenever the sustain pulse sus is added while the wall voltage and the sustain pulse sus are added to the cells. Display discharge occurs. After the sustain discharge is completed, the erase ramp waveform ers is supplied to the sustain electrode Z to erase wall charge remaining in the cells of the full screen.

However, as shown in FIG. 4, when the setup discharge is generated using only the sustain pulse, the initial discharge charge accumulated on the scan electrodes Y and the address electrodes X may be reduced. Therefore, the address discharge may occur in the cell to which data is applied during the address period. It is often the case that miss-writing occurs without it.

Accordingly, it is an object of the present invention to provide a method of driving a PDP that increases contrast ratio and prevents miswriting.

In order to achieve the above object, a driving method of a PDP according to the present invention includes an upper plate on which a plurality of electrode pairs including first and second electrodes are formed, and a lower plate on which a plurality of third electrodes intersect the plurality of electrode pairs are formed. And driving a PDP in which cells are formed at the intersections of the electrodes, wherein the first voltage is supplied from at least one of the first and second electrodes during a reset period from the first voltage. A first step of initializing the cells by supplying a charge-up rising ramp waveform whose voltage rises to a voltage of 100 to 130 [V] higher than the voltage; Supplying a stabilization rising ramp waveform at which a voltage increases from a base voltage (GND) to a stabilization voltage lower than the charge-up voltage to the first electrode, and supplying the base voltage to the second electrode; A third step of supplying a scan voltage to one of the first and second electrodes and a data voltage to the third electrode to address the cells during an address period; And a fourth step of performing display by alternately supplying sustain voltages to the first and second electrodes. Before the charge-up rising ramp waveform is supplied, the voltage of at least one of the first and second electrodes is maintained at the first voltage for approximately several [μs]. The driving method includes a fifth step of supplying at least one of the first and second electrodes a set-down falling ramp waveform in which a voltage drops from the first voltage to a negative set-down voltage following the charge-up rising ramp waveform. It includes more. The driving method further includes a sixth step of supplying the first voltage to at least one of the first and second electrodes prior to the set-down falling ramp waveform. Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 7.

Referring to FIG. 5, the PDP driving method according to an embodiment of the present invention time-divisions a PDP into a plurality of subfields for one frame period, and performs wall charge amount with a charge-up rising ramp waveform Rchuy in at least one subfield. Will be replenished.

At the beginning of the reset period, the sustain pulse sus of the sustain voltage Vs is first supplied to the scan electrodes Y and then the sustain electrodes Z. Then, the initializing sustain voltage Vs is supplied to the sustain electrodes Y again for a predetermined t1 period, for example, for about 3 to 4 [μs]. 0 [V] is supplied to the address electrodes X while the sustain pulses sus and the sustain voltage Vs are supplied to the scan electrodes Y and the sustain electrodes Z. FIG. Thus, when the sustain pulses sus and the sustain voltage Vs are supplied to the scan electrodes Y and the sustain electrodes Z, surface discharge occurs between the scan electrodes Y and the sustain electrodes Z. FIG. The negative wall charges are accumulated on the scan electrodes Y and the positive wall charges are accumulated on the sustain electrodes Z and the address electrodes X. The sustain voltage Vs is supplied during the t1 period, and the charge-up rising ramp waveform Rchuy, which rises from approximately 100 V to about 130 [V] from the sustain voltage Vs, is supplied to the scan electrodes Y. The slope of the charge-up rising ramp waveform Rchuy is set equal to the conventional setup ramp waveform Rsuy. In addition, the slope of the charge-up rising ramp waveform Rchuy may be set differently from the conventional setup ramp waveform Rsuy. This charge-up rising ramp waveform Rchuy causes weak write discharge between the scan electrodes Y and the sustain electrodes Z and between the scan electrodes Y and the address electrodes Z. As a result, more negative wall charges are accumulated on the scan electrodes Y, and positive wall charges are accumulated on the address electrodes Y to supplement the wall charge amount. The charge-up group (SUG) includes a plurality of sustain pulses (sus) and charge-up rising ramp waveforms (Rchuy) to prevent discharge from occurring significantly, thereby stabilizing initialization write operations, preventing contrast ratios, and preventing wall charges. It is supplemented enough to prevent miswriting. Subsequently, after the sustain voltage Vs is supplied to the scan electrodes Y for a period of t2, the set-down falling ramp waveform Rsdy in which the voltage falls from approximately the sustain voltage Vs to the setdown voltage Vsetdn is measured. The sustain voltage Vs is supplied to the sustain electrodes Y while being supplied to Y). When the setdown falling ramp waveform Rsdy is supplied, a setdown discharge occurs with a weak discharge between the scan electrodes Y and the sustain electrodes Z and between the scan electrodes Y and the address electrodes X. This set-down discharge eliminates unnecessary wall charges unnecessary for the address discharge among the wall charges formed during the setup discharge.

At the beginning of the address period, the stabilization in which the voltage rises from the base voltage GND or 0 [V] to the stabilization voltage Vsf after a scan bias voltage having a lower polarity than the sustain voltage Vs is supplied to the scan electrodes Y. The rising ramp waveform Rsfy is supplied to the scan electrodes Y. While the scan bias voltage and the stabilization ramp ramp Rsfy are supplied to the scan electrodes Y, the sustain electrodes Z and the address electrodes X are supplied with the ground voltage GND or 0 [V]. The stabilization rising ramp waveform Rsfy discharges the scan electrodes Y and the address electrodes X before the scan pulses and the data pulses are generated, thereby causing the negative electrode walls to the scan electrodes Y. By accumulating electric charges and accumulating more positive wall charges on the address electrodes X, address discharge occurs stably, and serves to lower address voltage, address discharge delay, and increase address driving margin. Subsequently, the scan pulse of the negative scan voltage Vscan is sequentially supplied to the scan electrodes Y and the data pulse data of the positive data voltage Vd synchronized with the scan pulse scan is It is supplied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage in the cell are added, an address discharge is generated in the cell to which the data pulse data is supplied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is supplied. A sustain voltage Vs is supplied to the sustain electrode Z during this address period.

In the sustain period, sustain pulses sus are alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. The first sustain pulse (sus) has a wider pulse width than the normal sustain pulse generated thereafter so that the sustain discharge starts stably. The pulse width of the last sustain pulse is set wider than the normal sustain pulse so that the erase discharge thereafter can occur stably. On-cells selected by the address discharge have a sustain discharge, i.e., a sustain discharge between the scan electrodes Y and the sustain electrodes Z whenever the sustain pulse sus is added while the wall voltage and the sustain pulse sus are added to the cells. Display discharge occurs. After the sustain discharge is completed, the erase rising ramp waveform ers is supplied to the sustain electrodes Z to erase the wall charge remaining in the cells of the full screen.

6 shows an apparatus for driving a PDP according to an embodiment of the present invention.

Referring to FIG. 6, a driving apparatus of a PDP according to an exemplary embodiment of the present invention uses a data driver 72 for supplying data to address electrodes X1 to Xm of the PDP, and scan electrodes Y1 to Yn. A scan driver 73 for driving, a sustain driver 74 for driving the sustain electrodes Z serving as a common electrode, a timing controller 71 for controlling each of the drivers 72, 73, and 74; A driving voltage generator 75 for supplying driving voltages to the driving units 72, 73, and 74 is provided.

The data driver 72 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then data mapped to each subfield is supplied by the subfield mapping circuit. The data driver 72 samples and latches data in response to the timing control signal CTRX from the timing controller 71, and then supplies the data to the address electrodes X1 to Xm.

The scan driver 73 supplies the sustain pulses su and the charge-up rising ramp waveform Rchuy and the like shown in FIG. 4 to the scan electrodes Y1 to Yn during the reset period under the control of the timing controller 71. . The scan driver 73 sequentially supplies the scan pulses to the scan electrodes Y1 to Yn during the address period, and supplies the sustain pulse sus and the erase rising ramp waveform ers during the sustain period to the scan electrodes Y1 to Yn. Supplies). As shown in FIG. 7, the charge-up rising ramp waveform Rchuy in the scan driver 73 may be generated by changing only the voltage source in the ramp generation circuit for generating the existing setup rising ramp waveform Rsuy. Accordingly, the circuit for generating the charge-up rising ramp waveform Rchuy may be simply implemented by replacing the voltage source with the charge-up voltage source in the existing circuit rather than being added to the conventional scan driver 73.

The sustain driver 74 alternately operates with the scan driver 73 under the control of the timing controller 71 to supply the sustain pulse su to the sustain electrodes Z.

The timing controller 71 receives the vertical / horizontal synchronization signal and the clock signal and generates timing control signals CTRX, CTRY, and CTRZ required for each driver, and outputs the timing control signals CTRX, CTRY, and CTRZ to the corresponding driver 72. , 73, 74 to control each of the driving units 72, 73, 74. The data control signal CTRX includes a sampling clock for latching data, a latch control signal, a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element. The scan control signal CTRY includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the scan driver 73. The sustain control signal CTRZ includes a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element in the sustain driver 74.

The driving voltage generator 75 generates a setup voltage Vsetup, a setdown voltage Vsetdn, a scan bias voltage Vscan-com, a scan voltage Vscan, a sustain voltage Vs, a data voltage Vd, and the like. . These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

7 shows the scan driver 73 in detail.

Referring to FIG. 7, the scan driver 73 includes first to third switch elements Q1 to Q3 and sixth switch elements connected to the first node between the energy recovery circuit 81 and the drive switch circuit 82. (Q6) is provided.

The energy recovery circuit 81 recovers energy of reactive power not contributing to the discharge from the PDP and charges the scan electrodes Y by using the recovered energy. This energy recovery circuit 81 may be implemented by any known energy recovery circuit.

The driving switch circuit 82 includes fourth and fifth switch elements Q4 and Q5 connected in a push-pull form between the scan bias voltage source Vscan-com and the first node n1. Each of the fourth and fifth switch elements Q5 and Q6 supplies a scan bias voltage Vscan-com or a voltage on the first node n1 to the scan electrodes Y under the control of the timing controller 71. .

The first switch element Q1 is connected between the sustain voltage source Vs and the first node n1 to supply the sustain voltage Vs to the first node n1 under the control of the timing controller 71.

The second switch element Q2 is connected between the ground voltage source GND and the first node n1 to supply the ground voltage GND or 0 [V] to the first node n1 under the control of the timing controller 71. Supply.

The third switch element Q3 is connected between the charge-up voltage source Vs + 100 to 130V and the first node n1 to increase the charge-up with a slope determined according to a predetermined RC time constant under the control of the timing controller 71. The ramp waveform Rchuy is supplied to the first node n1. In addition, the third switch element Q3 supplies the stabilization rising ramp waveform Rsfy and the erase rising ramp waveform ers to the first node n1 under the control of the timing controller 71. The control terminal of the third switch element Q3 is connected to a variable resistor VR for adjusting the inclination of the charge-up rising ramp waveform Rchuy and the stabilized rising ramp waveform Rsfy and a capacitor (not shown).

The sixth switch element Q6 is connected between the scan voltage source Vscan and the first node n1 to supply the scan voltage Vscan to the first node n1 under the control of the timing controller 71.

As described above, in the driving method of the PDP according to the present invention, after the sustain voltage is supplied to the sustain electrodes for a predetermined time, an initial write discharge is generated by supplying a rising ramp waveform having a charge-up voltage lower than the existing setup voltage. As a result, the driving method of the PDP according to the present invention can increase the contrast ratio by reducing the emission of visible light during the initialization write discharge, and can prevent the miswriting by sufficiently replenishing the wall charges of the electrodes before the address is started. According to an experiment applied to a high resolution 42 ″ PDP according to the present invention, the PDP driving method has improved to about 1000: 1 compared with the contrast ratio (600: 1) of the conventional driving method.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a perspective view showing in detail the structure of the discharge cell shown in FIG.

3 is a diagram illustrating a conventional frame including eight subfields in a method of driving a conventional plasma display panel.

4 is a waveform diagram showing a driving waveform of a conventional plasma display panel.

5 is a waveform diagram illustrating a method of driving a plasma display panel according to an exemplary embodiment of the present invention.

6 is a block diagram illustrating an apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating in detail the scan driver illustrated in FIG. 6.

<Description of Symbols for Main Parts of Drawings>

71: timing controller 72: data driver

73: scan driver 74: sustain driver

75: drive voltage generator

Claims (10)

A plasma display panel including an upper plate on which a plurality of electrode pairs including first and second electrodes are formed, and a lower plate on which a plurality of third electrodes intersect the plurality of electrode pairs are formed, and cells are formed at the intersections of the electrodes. In the method for Charge-up rising ramp waveform in which the voltage rises from the first voltage to a voltage 100 to 130 [V] higher than the first voltage after supplying a first voltage to at least one of the first and second electrodes during the reset period. A first step of initializing the cells by supplying; Supplying a stabilization rising ramp waveform at which a voltage increases from a base voltage (GND) to a stabilization voltage lower than the charge-up voltage to the first electrode, and supplying the base voltage to the second electrode; A third step of supplying a scan voltage to one of the first and second electrodes and a data voltage to the third electrode to address the cells during an address period; And driving the display by alternately supplying sustain voltages to the first and second electrodes. The method of claim 1, And the voltage of at least one of the first and second electrodes is maintained at the first voltage for approximately several [μs] before the charge-up rising ramp waveform is supplied. delete The method of claim 1, And a fifth step of supplying at least one of the first and second electrodes a set-down falling ramp waveform in which a voltage drops from the first voltage to a negative set-down voltage following the charge-up rising ramp waveform. A method of driving a plasma display panel. The method of claim 1, And a sixth step of supplying the first voltage to at least one of the first and second electrodes prior to the set-down falling ramp waveform. delete delete delete delete delete