KR100508256B1 - Method and Apparatus for Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method and apparatus for driving a plasma display panel to reduce discharge delay and enable single scan, as well as to lower voltage required for address discharge and to reduce mis-discharge.

The present invention provides an upper plate including a plurality of electrode pairs including first and second electrodes, a lower plate including a plurality of third electrodes intersecting the plurality of electrode pairs, and the first and second electrodes and the third electrode. A method of driving a plasma display panel including discharge cells formed at an intersection portion, the method comprising: supplying a first rising ramp waveform of which a voltage increases during a first period of a reset period to the first electrode, on the upper plate and the lower plate; Forming a wall charge; Supplying a second rising ramp waveform of which voltage rises during the second period of the reset period to the second electrode to erase a part of the wall charges formed on the upper plate; Supplying a falling ramp waveform in which the voltage falls during the third period of the reset period to the first electrode and the second electrode to erase wall charges formed on the upper plate and a part of the wall charges formed on the lower plate; ; During the address period, scan pulses are superimposed and supplied to the first electrodes, and a data voltage is supplied to the third electrodes to generate a priming discharge in a first section of the scan pulse and an address discharge in a second section of the scan pulse. Selecting and selecting the discharge cells; And performing a display by alternately supplying a sustain voltage to the first and second electrodes during the sustain period.

Description

Method and apparatus for driving plasma display panel {Method and Apparatus for Driving Plasma Display Panel}

The present invention relates to a method and apparatus for driving a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel, which not only enables a single scan by reducing discharge delay, but also lowers a voltage required for address discharge and reduces false discharge. It is about.

Plasma Display Panels (hereinafter referred to as "PDPs") display images by emitting phosphors by ultraviolet rays generated during discharge of He + Xe, Ne + Xe, He + Ne + Xe gases. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP lowers the voltage required for discharge by using wall charges accumulated on the surface during discharge, and has advantages of low voltage driving and long life because it protects the electrodes from sputtering caused by the discharge.

1 and 2, the three-electrode AC surface discharge type PDP includes scan electrodes Y1 to Yn and sustain electrodes Z formed on the upper substrate 10, and addresses formed on the lower substrate 18. Electrodes X1 to Xm are provided.

The discharge cells 1 of the PDP are formed at the intersections of the scan electrodes Y1 to Yn, the sustain electrodes Z and the address electrodes X1 to Xm.

The scan electrodes Y1 to Yn and the sustain electrodes Z each include a transparent electrode 12 and a metal bus electrode 11 having a line width smaller than that of the transparent electrode 12 and formed at one edge of the transparent electrode. do. The transparent electrode 12 is typically formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrode 11 is formed of a metal on the transparent electrode 12 to reduce the voltage drop caused by the transparent electrode 12 having a high resistance. The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 on which the scan electrodes Y1 to Yn and the sustain electrode Z are formed. On the upper dielectric layer 13, wall charges generated during plasma discharge are accumulated. The passivation layer 14 protects the electrodes Y1 to Yn and Z and the upper dielectric layer 13 from sputtering generated during plasma discharge and increases the emission efficiency of secondary electrons. As the protective film 14, magnesium oxide (MgO) is usually used.

The address electrodes X1 to Xm are formed on the lower substrate 18 in a direction crossing the scan electrodes Y1 to Yn and the sustain electrode Z. The lower dielectric layer 17 and the partition wall 15 are formed on the lower substrate 18. The phosphor layer 16 is formed on the surfaces of the lower dielectric layer 17 and the partition wall 15. The partition wall 15 is formed in parallel with the address electrodes X1 to Xm to physically distinguish the discharge cells to block electrical and optical interference between neighboring discharge cells 1. The phosphor layer 16 is excited and emitted by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue.

An inert mixed gas such as He + Xe, Ne + Xe, He + Ne + Xe for discharging is injected into the discharge space of the discharge cell provided between the upper and lower substrates 10 and 18 and the partition wall 15.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. When the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. Each of the subfields SF1 to SF8 is divided into a reset period for initializing the discharge cells 1, an address period for selecting the discharge cells, and a sustain period for implementing gray scale according to the number of discharges. The reset period and the address period of each subfield SF1 to SF8 are the same for each subfield, while the sustain period and the number of discharges thereof are 2 ⁿ (where n = 0,1,2,3, 4,5,6,7).

4 shows a driving waveform of the PDP.

Referring to FIG. 4, the rising ramp waveform Ramp-up is simultaneously supplied to all the scan electrodes Y in the setup period SU of the reset period. At the same time, 0 [V] is supplied to the sustain electrode Z and the address electrode X. The rising ramp waveform Ramp-up causes a setup discharge with weak discharge between the scan electrode Y and the address electrode X and between the scan electrode Y and the sustain electrode Z in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. In the set-down period SD of the reset period, the falling ramp waveform Ramp-dn whose voltage starts to drop from approximately the sustain voltage Vs and drops to the base voltage GND or 0 [V] or the negative voltage is scanned. It is supplied to (Y) at the same time. While the falling ramp waveform Ramp-dn is supplied to the scan electrodes Y, the sustain electrode Z is supplied with a positive sustain voltage Vs, and 0 [V] is supplied to the address electrode X. do. When the falling ramp waveform Ramp-dn is supplied in this way, a set-down discharge occurs with a weak discharge between the scan electrode Y and the sustain electrode Z and between the scan electrode Y and the address electrode X. This set-down discharge eliminates unnecessary wall charges unnecessary for the address discharge among the wall charges formed during the setup discharge. Looking at the wall charge change during this reset period, there is almost no wall charge change on the address electrode (X), and negative (-) wall charges on the scan electrode (Y) formed during the setup discharge are partially reduced by the setdown discharge. . On the other hand, positive wall charges are formed on the sustain electrode Z during setup discharge, but negative wall charges are accumulated on the self as much as the decrease of the negative wall charges of the scan electrode Y during the set-down discharge. .

In the address period, the negative scan pulse scan is sequentially supplied to the scan electrodes Y, and the positive data pulse data is supplied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the reset period are added, an address discharge is generated in the on-cell to which the data pulse is supplied. In the on-cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is supplied. During this address period, the positive pole DC voltage Zdc is supplied to the sustain electrode Z.

In the sustain period, sustain pulses sus are alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. On-cells selected by the address discharge are sustain discharge, that is, display discharge, between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is supplied as the wall voltage and the sustain pulse sus are added in the cell. Is generated.

After the sustain discharge is completed, the erasing period is continued. In the erase period, an erase ramp waveform (ramp-ers) having a small pulse width and a low voltage level is supplied to the sustain electrode Z to erase wall charge remaining in the cells of the full screen.

These PDPs are getting higher resolution and image quality has been greatly improved recently. However, if a subfield is added to increase the resolution or to improve the image quality, the driving time is insufficient because the address period becomes long. This lack of driving time can be solved by a dual scan method that can simultaneously scan two lines in the PDP, but there is another problem that a drive integrated circuit must be added by the dual scan method. Therefore, in recent years, research has been actively conducted to increase the image quality while driving the PDP with a single scan that does not require the addition of a drive integrated circuit.

Recently, a method of increasing the content of Xe in the discharge gas by 10% or more has been proposed in order to achieve high efficiency with low power consumption of the PDP. However, increasing the content of Xe increases the lamp voltage in the reset period and increases the discharge delay, in particular, the address jitter value, which increases the scan time and the address period and thus cannot drive the PDP in a single scan.

As a method for reducing the address period, a method of overlapping scan pulses by t1 time, as shown in FIG. 5, has been proposed. However, the overlap scan has a high possibility of false discharge occurring at the overlap time t1, and there is a limit in reducing the address period because the overlap time t1 cannot be widened sufficiently.

Accordingly, it is an object of the present invention to provide a method and apparatus for driving a PDP that not only enables a single scan by reducing discharge delay, but also lowers a voltage required for address discharge and reduces false discharge.

In order to achieve the above object, a method of driving a plasma display panel according to an embodiment of the present invention includes a top plate having a plurality of electrode pairs including first and second electrodes respectively, and a plurality of third intersecting the plurality of electrode pairs. A method of driving a plasma display panel including a lower plate having an electrode formed therein and discharge cells formed at an intersection of the first and second electrodes and the third electrode, the method comprising: a first voltage having a voltage increased during a first period of a reset period; Supplying a ramp ramp waveform to the first electrode to form wall charges on the upper plate and the lower plate; Supplying a second rising ramp waveform of which voltage rises during the second period of the reset period to the second electrode to erase a part of the wall charges formed on the upper plate; Supplying a falling ramp waveform in which the voltage falls during the third period of the reset period to the first electrode and the second electrode to erase wall charges formed on the upper plate and a part of the wall charges formed on the lower plate; ; During the address period, scan pulses are superimposed and supplied to the first electrodes, and a data voltage is supplied to the third electrodes to generate a priming discharge in a first section of the scan pulse and an address discharge in a second section of the scan pulse. Selecting and selecting the discharge cells; And displaying a sustain voltage by alternately supplying sustain voltages to the first and second electrodes during a sustain period. The first section of the scan pulse precedes the second section of the scan pulse. The scan pulses supplied to the first electrode overlap each other in a second section of the scan pulse. The data voltage is supplied to the third electrode during a second section of the scan pulse. A driving apparatus of a plasma display panel according to an exemplary embodiment of the present invention includes an upper plate on which a plurality of electrode pairs including first and second electrodes are formed, and a lower plate on which a plurality of third electrodes intersecting the plurality of electrode pairs are formed. And discharge cells formed at an intersection of the first and second electrodes and the third electrode. A second rising ramp waveform in which the voltage rises during the first period of the period to supply the first electrode to form wall charges on the upper plate and the lower plate, and to increase the voltage during the second period of the reset period. A ramp waveform is supplied to the second electrode to erase a portion of the wall charges formed on the top plate, and a ramp ramp waveform in which the voltage falls during the third period of the reset period is supplied to the first electrode and the second electrode. An initialization driver to erase a part of the wall charges formed on the top plate; During the address period, scan pulses are superimposed and supplied to the first electrodes, and a data voltage is supplied to the third electrodes to generate a priming discharge in a first section of the scan pulse and an address discharge in a second section of the scan pulse. A scan / address driver which selects the discharge cells by generating a; And a sustain driver for alternately supplying sustain voltages to the first and second electrodes during the sustain period. The other objects and advantages of the present invention in addition to the above object are described with reference to the accompanying drawings. It will be apparent from the description of the preferred embodiment of the present invention.

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

Hereinafter, with reference to Figures 6 to 12 attached to an embodiment of the present invention will be described in detail.

6 and 7, the driving method of the PDP according to the embodiment of the present invention sequentially supplies rising ramp waveforms Ruy and Ruz to the scan electrode Y and the sustain electrode Z during the reset period. Overlap scan pulses for a period of time.

In the period a of the reset period, all of the scan electrodes Y are supplied with a first rising ramp waveform Ruy that starts rising from approximately the sustain voltage Vs and rises to the setup voltage Vry at the same time. At the same time, 0 [V] is supplied to the sustain electrode Z and the address electrode X. Section a is a period in which wall charges are accumulated on the electrodes Y and Z on the upper plate and the address electrodes X on the lower plate. The weak discharge occurs between the scan electrode Y and the address electrode X and between the scan electrode Y and the sustain electrode Z in the cells of the full screen by the first rising ramp waveform Ruy. Due to this discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

In the period b of the reset period, the second rising ramp waveform Ruz that starts rising from the sustain voltage Vs and rises to the setup voltage Vrz is simultaneously supplied to the sustain electrodes Z. During this period b, the sustain voltage Vs is supplied to the scan electrodes Y, and 0 [V] is supplied to the address electrode X. Section b is a period of erasing some of the wall charges accumulated on the electrodes Y and Z of the upper plate and further accumulating wall charges on the address electrodes X of the lower plate. A weak discharge occurs between the sustain electrode Z and the address electrode X and between the scan electrode Y and the sustain electrode Z in the cells of the full screen by the second rising ramp waveform Ruz. At this time, the negative wall charges on the scan electrode Y are erased by the sustain electrode Z and the scan discharge, and the negative wall charges are accumulated on the sustain electrode Z by the decrease of the negative wall charges of the scan electrode Y. Polar wall charges are erased and the polarity of the wall charges is reversed to negative polarity. As a result of the discharge between the sustain electrode Z and the address electrode X, the positive wall charges are further accumulated on the address electrode X as much as the decrease in the positive wall charges accumulated on the sustain electrode Z.

According to the conventional driving waveform as shown in FIG. 4, the amount of positive wall charge flowing into the lower plate among the charged particles generated during the setup period SU in which the rising ramp signal Ramp-up is applied to the scan electrode Y is small. In the next set-down period SD, the wall charge loss of the positive polarity formed on the lower plate by erasing the wall charges becomes large enough that the address discharge is unstable. In other words, the conventional drive waveform causes the lower wall charges to be insufficient in the address period, thereby increasing the amount of delay or address jitter of the address discharge. In contrast, in the driving method of the PDP according to the present invention, as described above, after the rising ramp waveform Ru is applied to the scan electrodes Y in section a, the rising ramp waveform Ruz is sustained during the section b. It is applied to (Z) and the positive wall charge is continuously supplied to the lower plate in two successive discharges. At this time, the discharge in section a occurs smaller than the conventional setup waveform, and even though the positive wall charges formed on the lower plate in section a are small, the positive wall charges are supplemented on the lower plate by the discharge occurring in section b. Because of this, even if the voltages Vry and Vrz of the rising ramp waveforms Ruy and Ruz are lower than the conventional setup voltage Vsetup as shown in FIG. 4, a sufficient amount of positive wall charges can be accumulated on the bottom plate, resulting in subsequent address discharge. The discharge delay can be reduced.

Meanwhile, the voltages Vry and Vrz of the first and second rising ramp waveforms Ruy and Ruz may be set identically or differently. In addition, the slopes of the first and second rising ramp waveforms Ruy and Ruz may be set identically or differently.

In the period c of the reset period, the second falling ramp waveform Rdz, which starts to fall from the sustain voltage Vs and drops to the base voltage GND or 0 [V], is supplied to the sustain electrodes Y. The first falling ramp waveform Rdy, which starts to fall from approximately the sustain voltage Vs and drops to a predetermined voltage (−Vny) of negative polarity, is supplied to the scan electrodes Y. While the falling ramp waveforms Rdz and Rdy are supplied to the sustain electrodes Z and the scan electrodes Y, 0 [V] is supplied to the address electrodes X. When the falling ramp waveforms Rdz and Rdy are supplied in this way, a weak discharge occurs between the scan electrodes Y and the address electrodes X. FIG. By this discharge, unnecessary wall charges unnecessary for address discharge are erased among the wall charges formed on the scan electrodes Y and the address electrodes X in all the discharge cells.

Meanwhile, the voltages Vry and Vrz of the first and second falling ramp waveforms Rdy and Rdz may be set identically. In addition, the slopes of the first and second falling ramp waveforms Rdy and Rdz may be set differently or the same as shown in the drawing.

According to the conventional driving waveform as shown in FIG. 4, the surface discharge between the scan electrodes Y and the sustain electrodes Z is mainly generated during the set down period SU to adjust the wall charges of the upper plate and the lower half to meet the address condition. . On the other hand, the driving method of the PDP according to the present invention adjusts the wall charge using only the opposite discharge between the scan electrodes (Y) and the address electrodes (X) during the period c, so that the wall charges required for the address discharge can be easily adjusted. By appropriately adjusting the voltage Vny, the wall charges related to the address discharge are appropriately erased to ideally set the address initial conditions to realize more stable address driving conditions. In addition, by implementing ideal initial conditions necessary for address discharge, the present invention can increase address driving margin and reduce address discharge delay.

In the address period, the scan pulse of the negative scan voltage (-Vy) is sequentially supplied to the scan electrodes Y and the data pulse of the positive data voltage Vd synchronized with the scan pulse (scan). Is supplied to the address electrodes (X). Scan pulses (scan) supplied to the neighboring scan electrodes (Y) are overlapped by t2 as shown in FIG. 8. FIG. 8 is a waveform diagram illustrating an enlarged address period in the driving waveform of FIG. 6, wherein the first and second scan electrodes Y1 and Y3 are connected without selecting the second scan line including the second scan electrode Y2. Shows the scan and data pulses for selecting the first and third scanlines included. The data pulse data is supplied to the address electrodes X during the t2 period. The period t before the scan pulse except for the period t2 is supplied only with the scan pulse, and the period t does not occur as shown in FIG. In the t period, address discharge does not occur as shown in FIG. In this time period, no address discharge occurs, but as shown in FIG. 10, a self-priming discharge occurs along with generation of space charges. This self-priming discharge is less than 1/100 of the address discharge. For this reason, even if self-priming discharge occurs, the magnitude thereof is small. Thus, if the address discharge does not occur normally in the period t2 where the scan pulse and the data pulse are synchronized, no false discharge occurs. This self-priming discharge depends on the negative wall charge amount formed on the sustain electrodes Z after the reset period. That is, the self-priming discharge mainly occurs between the scan electrodes Y and the sustain electrodes Z. When the negative wall charges on the sustain electrodes Z become small as in the conventional driving waveform shown in FIG. The self-priming discharge cannot occur because the voltage difference between the field Y and the sustain electrodes Z is low. In contrast, as shown in FIG. 7, if the negative wall charges are sufficiently increased on the sustain electrodes Z before the address discharge starts, self-priming discharge occurs. The space charges generated by the self-priming discharge, that is, the priming charged particles move from the upper cell 1 to the lower cell 1 along the scanning direction as shown in FIG. 11. These priming charged particles are supplied into the cell 1 during the t1 period before the address discharge occurs so that the address discharge occurs quickly and easily and stably with little address jitter. The priming charged particles can also lower the scan voltage (-Vy) and / or the data voltage (Vd) for causing the address discharge by the voltage precharged in the cell by the priming charged particles. When the data voltage Vd is lowered in this manner, the t2 period in which the address discharge occurs is sufficiently long, that is, the overlap width is increased, and the address period is greatly shortened.

As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the reset period are added, an address discharge is generated in the cell 1 to which the data pulse data is supplied. In the cells 1 selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is supplied. During this address period, the positive pole DC voltage Vzdc is supplied to the sustain electrode Z.

In the conventional driving waveforms, the DC voltage Zdc supplied to the sustain electrodes Z during the address period is clearly seen in FIGS. 4 and 5, and is generally set to the sustain voltage Vs so that the sustain electrodes Z are maintained. It is used for the purpose of making it possible to stably stack negative wall charges in a phase. On the other hand, in the driving method of the PDP according to the present invention, the DC voltage Vzdc supplied to the sustain electrodes Z during the address period is sustained by discharge generated by the rising ramp waveform Ruz applied in the b section. Since the negative wall charges are sufficiently accumulated on (Z), the voltage may be lowered while playing the same role as the conventional DC voltage Zdc set to the sustain voltage Vs. That is, the driving method of the PDP according to the present invention can lower the voltage of the DC voltage Vzdc supplied to the sustain electrodes Z to the voltage lower than the sustain voltage Vs during the address period.

The rising ramp waveforms Ruy and Ruz are successively supplied to the scan electrodes Y and the sustain electrodes Z, so that the PDP in which a large amount of negative wall charges remain on the sustain electrodes Z is shown in FIG. When driven by the same conventional superimposition scan method, mis-discharge is likely to occur. For example, when a data voltage for selecting the k + 2 th scan line scan k + 2 is generated in FIG. 5, an erroneous discharge may occur at the k + 1 th scan line scan k + 1.

In the sustain period, the sustain pulse sus of the sustain voltage Vs is supplied to the scan electrodes Y and the sustain electrodes Z alternately. On-cells selected by the address discharge are sustain discharge, that is, display discharge, between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is supplied as the wall voltage and the sustain pulse sus are added in the cell. Is generated.

In the erasing period following the sustain discharge, an erase ramp waveform (ramp-ers) rising at a predetermined slope from 0 V or the base voltage (GND) to the sustain voltage (Vs) is simultaneously supplied to the sustain electrodes (Z) so that the cells in the full-surface cells The remaining wall charges are eliminated.

12 shows an apparatus for driving a PDP according to an embodiment of the present invention.

Referring to FIG. 12, a driving apparatus of a PDP according to an embodiment of the present invention may include a data driver 122 for supplying data to address electrodes X1 to Xm of the PDP, and scan electrodes Y1 to Yn. A scan driver 123 for driving, a sustain driver 124 for driving the sustain electrodes Z serving as a common electrode, a timing controller 121 for controlling the driving units 122, 123, and 124; And a driving voltage generator 125 for supplying driving voltages necessary for the driving units 122, 123, and 124.

The data driver 122 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then data mapped to each subfield is supplied by the subfield mapping circuit. The data driver 122 samples and latches data in response to the timing control signal CTRX from the timing controller 121, and then supplies the data to the address electrodes X1 to Xm.

The scan driver 123 supplies the first rising ramp waveform Ruy to the scan electrodes Y1 to Yn during a section of the reset period under the control of the timing controller 121, and maintains the sustain voltage Vs for a section b. Then, the first falling ramp waveform (Rdy) is supplied for a period c. During the sustain period, the scan driver 73 sequentially supplies the scan pulses overlapped by the time t as shown in FIGS. 6 and 8 to the scan electrodes Y1 to Yn under the control of the timing controller 71 during the address period. Sustain pulses (sus) are supplied.

The sustain driver 124 continuously supplies the base voltage GND or 0V to the sustain electrodes Z under the control of the timing controller 121 during a section of the reset period, and then, during the b section, the second rising ramp waveform Ruz. ), And then a second falling ramp waveform Rdz is supplied during section c. The sustain driver 74 supplies the scan electrodes Y1 to Yn with the DC voltage Vzdc lower than the sustain voltage Vs during the address period under the control of the timing controller 71, and then the scan driver during the sustain period. In operation alternately with 73, the sustain pulse su is supplied to the sustain electrodes Z.

The timing controller 121 receives the vertical / horizontal synchronization signal and the clock signal, generates timing control signals CTRX, CTRY, and CTRZ required for each driver, and transmits the timing control signals CTRX, CTRY, and CTRZ to the corresponding driver 122. , Respectively, to control the driving units 122, 123, and 124. The data control signal CTRX includes a sampling clock for latching data, a latch control signal, a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element. The scan control signal CTRY includes a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element in the scan driver 123. The sustain control signal CTRZ includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the sustain driver 124.

The driving voltage generator 125 includes the voltages Vry and Vrz of the rising ramp waveforms Ruy and Ruz, the DC voltage Vzdc applied to the sustain electrodes Z during the address period, the scan bias voltage Vscb, and the scan. A voltage (-Vy), a sustain voltage (Vs), a data voltage (Vd), and the like are generated. These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

As described above, the method and apparatus for driving a PDP according to the present invention sequentially apply rising ramp waveforms to the scan electrode and the sustain electrode with time difference and simultaneously apply the falling ramp waveforms to the scan electrode and the sustain electrode to initialize all the cells. The self-priming discharge and the address discharge are continuously generated by overlapping scan pulses during the address period. Accordingly, the method and apparatus for driving a PDP according to the present invention can reduce the discharge delay and enable a single scan, and can also prevent mis-discharge even if the voltage required for address discharge is lowered and the scan pulses overlap.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a perspective view showing in detail the structure of the discharge cell shown in FIG.

3 is a diagram illustrating a conventional frame including eight subfields in a method of driving a conventional plasma display panel.

4 is a waveform diagram showing a conventional driving waveform.

5 is a waveform diagram showing a conventional superimposed scan driving method.

6 is a waveform diagram illustrating a method of driving a plasma display panel according to an exemplary embodiment of the present invention.

7 is a view schematically showing a change in the wall charge distribution during the reset period in the plasma display panel according to the embodiment of the present invention.

FIG. 8 is an enlarged waveform diagram of an address period in the driving waveform of FIG. 6.

9 is a result screen of the simulation showing the time difference between the scan pulse and the address discharge.

FIG. 10 is a result screen of a simulation showing that a scan pulse is supplied to a scan electrode and a data pulse is not supplied to an address electrode and showing self-priming discharges generated in the simulation.

11 is a diagram illustrating movement of space charges generated during self-priming discharges.

12 is a block diagram illustrating an apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

121: timing controller 122: data driver

123: scan driver 124: sustain driver

125: drive voltage generator

Claims (10)

An upper plate having a plurality of electrode pairs each including first and second electrodes, a lower plate having a plurality of third electrodes intersecting the plurality of electrode pairs, and an intersection portion of the first and second electrodes and the third electrode. In a driving method of a plasma display panel including discharge cells formed, Supplying a first rising ramp waveform of which voltage rises during the first period of a reset period to the first electrode to form wall charges on the upper plate and the lower plate; Supplying a second rising ramp waveform of which voltage rises during the second period of the reset period to the second electrode to erase a part of the wall charges formed on the upper plate; Supplying a falling ramp waveform in which the voltage falls during the third period of the reset period to the first electrode and the second electrode to erase wall charges formed on the upper plate and a part of the wall charges formed on the lower plate; ; During the address period, scan pulses are superimposed and supplied to the first electrodes, and a data voltage is supplied to the third electrodes to generate a priming discharge in a first section of the scan pulse and an address discharge in a second section of the scan pulse. Selecting and selecting the discharge cells; And supplying a sustain voltage to the first and second electrodes alternately during the sustain period to perform display. delete The method of claim 1, And the first section of the scan pulse precedes the second section of the scan pulse. The method of claim 1, And the scan pulses supplied to the first electrode overlap each other in a second section of the scan pulse. The method of claim 1, And the data voltage is supplied to the third electrode during the second period of the scan pulse. An upper plate having a plurality of electrode pairs each including first and second electrodes, a lower plate having a plurality of third electrodes intersecting the plurality of electrode pairs, and an intersection portion of the first and second electrodes and the third electrode. In the driving apparatus of the plasma display panel including the formed discharge cells, A first rising ramp waveform in which the voltage rises during the first period of the reset period is supplied to the first electrode to form wall charges on the upper plate and the lower plate, and the voltage rises during the second period of the reset period. A second ramp waveform is supplied to the second electrode to erase a portion of the wall charges formed on the upper plate, and a falling ramp waveform in which the voltage falls during the third period of the reset period is applied to the first electrode and the second electrode. An initialization driver for supplying and erasing part of wall charges formed on the upper plate; During the address period, scan pulses are superimposed and supplied to the first electrodes, and a data voltage is supplied to the third electrodes to generate a priming discharge in a first section of the scan pulse and an address discharge in a second section of the scan pulse. A scan / address driver which selects the discharge cells by generating a; And a sustain driver which supplies sustain voltage alternately to the first and second electrodes during the sustain period to perform display. delete The method of claim 6, And the first section of the scan pulse precedes the second section of the scan pulse. The method of claim 6, And the scan pulses supplied to the first electrode overlap each other in a second section of the scan pulse. The method of claim 6, And the data voltage is supplied to the third electrode during the second period of the scan pulse.