JPS6353948A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve an integration by a method wherein input/output buffer circuit basic cells are composed of input buffer circuit basic cells and output buffer circuit basic cells which are independently formed and those cells are alternately arranged along the direction of the arrangement of external terminals. CONSTITUTION:Input buffer circuit basic cells 3A and output buffer circuit basic cells 3B are alternately arranged in the circumferential part of a semiconductor integrated circuit device 1 along the direction of the arrangement of external terminals 2. With this constitution, the sizes of the cells 3A and 3B can be independently determined without being restricted by the size of the cell 3B whose size is large in order to make the driving capability of an external device large so that a useless area can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device, particularly a semiconductor integrated circuit device that employs a mask slicing method.

[Conventional technology]

Semiconductor integrated circuit devices that use the mask slicing method are
Many logic functions and memory functions can be formed by changing the wiring pattern (mask pattern in the wiring formation process) applied to the master wafer.

The master wafer is one or M of Fv number connected in series.
A basic cell formed by an ISFET.

A plurality of cells are arranged in the column direction to form a basic cell column.

The basic cell is, for example, a complementary type M I S FET consisting of a P channel M I S FET and an n channel M I S FET.
Consists of 5 FETs. 1, a plurality of cell columns are arranged at predetermined intervals in the row direction with wiring regions interposed therebetween.

In the periphery of the semiconductor integrated circuit device, a plurality of basic cells for human output buffer circuits corresponding to respective external terminals are arranged in the same direction as the direction in which the external terminals are arranged. Basic cells for input/output buffer circuits.

In order to increase the number of external terminals (multiple pins), install the output buffer circuit in the direction crossing the direction in which the external terminals are arranged.
A 1ls FET and a MIS FET for the human buffer circuit are arranged. This basic cell for human output buffer circuit is configured so that either an input buffer circuit or an output buffer circuit can be formed by changing the wiring pattern.

Semiconductor integrated circuit devices that use the master slice method are
Produce products in a short time in response to user requests! ! ! : There is a characteristic that can be completed.

Regarding semiconductor integrated circuit devices that adopt the master slice method, for example, see Nikkei Electronics, published by Nikkei McGraw-Hill, June 30, 1985, pp151.
-177.

[Problem that the invention seeks to solve]

The present inventor conducted a study on a semiconductor integrated circuit device that employs the above-mentioned master slicing method.

It was found that the following problem occurred.

The basic cell for the input/output buffer circuit is M I S F for the input buffer circuit in order to increase the driving capacity of external devices.
The size of the MTS FET for the output buffer circuit is larger than that of the ET. In other words.

Although the size of the basic cell for the output buffer circuit is small, the size of the MISFET for the input buffer circuit is small.
It is defined by the dimensions of MTS FET for the output buffer circuit. Therefore, since there is wasted area in the human output buffer circuit, a problem arises in that the degree of integration of the semiconductor integrated circuit device is reduced.

An object of the present invention is to provide a technique that can improve the degree of integration in a semiconductor integrated circuit device that employs a master slice method.

Another object of the present invention is to provide a technique that achieves the above object and can reduce the area occupied by the input buffer circuit and the output buffer circuit.

Another object of the present invention is to provide a technique that can achieve the above object and improve the electrical reliability of a buffer circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

Outline of typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device that adopts the master slice method, a basic cell for an input/output buffer circuit is divided into a basic cell for a manual buffer circuit and a basic cell for an output buffer circuit, and a basic cell for a human cover sofa circuit and a basic cell for an output buffer circuit are used. The first and second cells are arranged alternately in the same direction as the direction in which the external terminals are arranged.

[For production]

According to the above means, the size of the basic cell for the human-powered buffer circuit and the basic cell for the output buffer circuit is
Since they can be formed independently without being defined by the size of one of the basic cells and waste area can be eliminated, the area occupied by both basic cells can be reduced and the degree of integration can be improved.

Hereinafter, the configuration of the present invention will be explained along with one embodiment.

In all the figures, parts having the same functions are denoted by the same reference numerals, and repeated explanations thereof will be omitted.

[Example I]

FIG. 1 (schematic plan view) shows a schematic configuration of a semiconductor volume circuit device using one type of master slice method, which is Embodiment I of the present invention.

In FIG. 1, l is a semiconductor integrated circuit device that employs a mask slicing method.

In the peripheral part of this semiconductor integrated circuit device 1, external terminals (bonding terminals) 2, basic cells 3A for input buffer circuits, and basic cells 3B for output buffer circuits are provided, respectively.
Multiple locations are placed in the same direction.

The external terminal 2 is used for input when connected to the input buffer circuit basic cell 3Δ, and used for output when connected to the output buffer circuit basic cell 3B. The external terminal 2 is configured to be connected to an external device (not shown).

Each of the input buffer circuit basic cell 3Δ and the output buffer circuit basic cell 3A is shown in FIG. 2 (a copy of the main part of FIG. 1).
As shown, they are arranged alternately in the same direction as the direction in which the external terminals 2 are arranged.

That is, each of the input buffer circuit basic cell 3Δ and the output buffer circuit basic cell 3B is configured by dividing one human output buffer circuit basic cell and arranging a plurality of them in the above-mentioned direction. One input buffer circuit basic cell 3A and one output buffer circuit basic cell 3A form one set, which is arranged for each external terminal 2.

As shown in FIG. 3 (principal plan view showing a specific configuration), the input buffer circuit basic cell 3A is composed of two input element regions 3Ap and 3An. Each of the input element regions 3Ap and 3An is arranged in a direction intersecting the direction in which the external terminals 2 are arranged.

The input element region 3Ap is formed on the external terminal 2 side, and is a P-channel MI S FETQ p + =Qp.
It consists of 7. MISFETQP, ~QP3 and Q
A three-manpower NAND gate circuit can be formed with n , .about.Q n 3. MISFET Qp4 and QP5 and MISFET Q n4 and Q
The n5 is designed to allow a two-person NAND gate circuit to be formed.

The input element region 3An is formed on the side separated from the external terminal 2, and is connected to the n-channel MISFETQ n + =
It is composed of Q n 7. Mr S FETQ
A three-manpower NAND gate circuit can be formed by n + "Q n 3 and Q p + -Q P 3.

MISFET Qn4 and Qn5 and MISFETQp4 and Qps can form a two-manpower NAND gate circuit. In other words, the input element areas 3AP and 3An are complementary MI
It is now possible to configure SFET.

The output buffer circuit basic cell 3B is composed of two output element regions 3Bp and 3Bn.

Each of the input element regions 3Bp and 3Bn is arranged in a direction intersecting the direction in which the external terminals 2 are arranged.

The output element region 3Bp is formed on the external terminal 2 side, and the P channel MISFET Qp a~
It is composed of Qp++. This MISFET Qpo
= Q p II and Qna ~ Qn II for 4-man NA
It is now possible to form an ND gate circuit.

The output element region 3Bn is formed on the side separated from the external terminal 2, and is connected to the n-channel MISFETQ n 8 to Q.
It is composed of nll. This MTSFETQn8~Q
4 manpower N with n II and Q Pa ~Q p + 1
It is now possible to form an AND gate circuit. In other words, the output element regions 3Bp and 3Bn are complementary MIS
It is now possible to configure an FET.

Basic cell 3B for output buffer circuit (3Bp and 3Bn
MISFETs Qp and Qn formed in ) are larger in size than MISFETs QP and Qn formed in input buffer circuit basic cells 3A (3Ap and 3An). This is to increase the driving capacity of the external device. Conversely, MISFETQP and Qn formed in the input buffer circuit basic cell 3A are similar to MISFETQ formed in the output buffer circuit basic cell 3B.
It is configured with a smaller size than p and Qn.

The area ratio between the two is, for example, about 2:1 (the input buffer circuit basic cell 3A is composed of 100 x 400 [μm], and the output buffer circuit basic cell 3B is composed of 200 [μm]).
x400 [μm]).

In this way, the basic cell for the input/output buffer circuit.

By dividing the basic cells 3A for input buffer circuits and the basic cells 3B for output buffer circuits, and arranging the respective basic cells 3A and 3B alternately in the same direction as the direction in which the external terminals 2 are arranged, Since the size of each of the basic cells 3A and 3B can be formed independently without being defined by the size of the latter basic cell 3B, wasted area can be eliminated. In other words, the input buffer circuit basic cell 3A is no longer defined by the size of the output buffer circuit basic cell 3B, and there is no wasted area, so the size can be reduced. Therefore, since the area required for the input buffer circuit and the output buffer circuit can be reduced, the degree of integration of the semiconductor integrated circuit device 1 can be improved.

Moreover, in the basic cell 3A for input buffer circuit.

Since dedicated input wiring regions (wiring channel regions) and output buffer circuit basic cells 3B can each have dedicated output wiring regions, it is possible to reduce the area occupied by the wiring regions. In other words.

When wiring areas for input and output are provided in advance, it is possible to prevent any of them from being wasted. Therefore, the degree of integration of the semiconductor integrated circuit device 1 can be further improved.

Further, each of the dedicated input wiring region and the dedicated output wiring region can be provided in the respective regions of the input buffer circuit basic cell 3A and the output buffer circuit basic cell 3B, separated from each other. . Therefore, it is possible to reduce the occurrence of noise (potential fluctuation) in the input signal or the output signal, so that the electrical reliability of the semiconductor integrated circuit device 1, particularly the input buffer circuit or the output buffer circuit, can be improved. .

Moreover, MISFETQp forming each of the input buffer circuit basic cell 3A and the output buffer circuit basic cell 3B
Alternatively, since the gate length direction of the gate electrode of Qn is made to match the direction in which the external terminal 2 is arranged, a large number and various types of MISFETs Qp or Qn can be arranged in that direction.

As shown in FIG. 1, a basic cell 4 is provided in the center of the semiconductor integrated circuit device 1. As shown in FIG.

A plurality of basic cells 4 are arranged in one column direction to form a basic cell column 5. A plurality of basic cell columns 5 are arranged at predetermined intervals in the row direction with wiring regions (wiring channel regions) 6 interposed therebetween. The wiring area 6 is mainly used as an area for forming wiring that connects between the basic cells 4 or between logic circuits and memory circuits formed by the basic cells 4. The basic cell 4 is composed of, for example, a complementary MI S FET,
It is possible to form a two-person NAND gate circuit, a three-person NAND gate circuit, etc.

First layer wiring (for example, aluminum wiring) is provided in the basic cell 4, the input buffer circuit basic cell 3A, the output buffer circuit basic cell 3B, etc. Second layer wiring (for example, aluminum wiring) is provided between the basic cells 4 and between the circuits formed by the basic cells 4. The power supply wiring extending over the input buffer circuit basic cell 3A and the output buffer circuit basic cell 3B is formed, for example, from a second layer wiring.

[Example ■]

Embodiment 2 is another embodiment of the present invention in which a plurality of input buffer circuit basic cells and a plurality of output buffer circuit basic cells are arranged alternately.

FIG. 4 (a schematic diagram of the main parts) shows a schematic configuration of a semiconductor integrated circuit device that adopts the mask slicing method, which is Embodiment 2 of the present invention.
Indicated by

As shown in FIG. 4, the semiconductor integrated circuit 'JA 1 is.

Two input buffer circuit basic cells 3A and two output buffer circuit basic cells 3B are arranged alternately. That is, the two input buffer circuit basic cells 3A and the two output buffer circuit basic cells 3B are arranged adjacent to each other.

The semiconductor integrated circuit device 1 configured as described above can obtain substantially the same effects as in the embodiment (2), and also has the fourth embodiment.
As surrounded by a dashed line in the figure, one output buffer circuit (the same applies to the input buffer circuit) can be configured into an nID using two output buffer circuit basic cells 3B. That is, for example, an output buffer circuit that requires a large driving capability, such as an interface circuit for a crystal oscillator, can be easily configured.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention may be applied to a semiconductor integrated circuit device that employs a master slicing method in which basic cells 4 are spread over the entire surface and the basic cells 4 are used as wiring regions 6 as necessary.

Furthermore, the present invention may incorporate bipolar transistors into basic cells for input or output buffer circuits.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects that can be obtained by typical ones are as follows.

In a semiconductor integrated circuit device that employs the master slice method, the area occupied by basic cells for input and output buffer circuits can be reduced, so that the degree of integration can be improved.

[Brief explanation of drawings]

Figure 1 is an embodiment of the present invention! 2 is a schematic plan view of a semiconductor integrated circuit device adopting the mask slicing method, FIG. 2 is a schematic diagram of the main parts of the semiconductor integrated circuit device of FIG. 1, and FIG. FIG. 4 is a schematic diagram of the main parts of a semiconductor integrated circuit device employing the mask slicing method, which is Embodiment 2 of the present invention. In the figure, 1... semiconductor integrated circuit device, 2... external terminal. 3A... Basic cell for input buffer circuit, 3B... Basic cell for output buffer circuit, 3Ap, 3An... Input element area, 3Bp, 3Bn... Output element area, 4
. . . basic cell, 5 . . . basic cell column, 6 . . . wiring area. 7・′-＼

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device that employs a master slice method and has a basic cell for an input/output buffer circuit, the basic cell for an input/output buffer circuit is combined with a basic cell for an input/output buffer circuit and an output buffer circuit. Split into basic cell and
A semiconductor integrated circuit device characterized in that the input buffer circuit basic cells and the output buffer circuit basic cells are arranged alternately in the same direction as the direction in which external terminals are arranged. 2. The semiconductor integrated circuit device according to claim 1, wherein each of the basic cells for input buffer circuits and the basic cells for output buffer circuits are arranged alternately in plural numbers. 3. Claim 1 or 2, characterized in that the basic cell for the input buffer circuit has smaller dimensions than the basic cell for the output buffer circuit in the direction in which it is arranged. The semiconductor integrated circuit device described in . 4. The input buffer circuit basic cell or the output buffer circuit basic cell is configured with a MISFET, and the gate length direction of the gate electrode of the MISFET is configured in the same direction as the direction in which both the basic cells are arranged. Each of the semiconductor integrated circuit devices according to claims 1 to 3 is characterized in that: