JPH0821625B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device requiring a large number of input / output pins, and more particularly to a structure of an input / output buffer of a gate array.

[Prior Art] FIG. 5 is a block diagram of a complementary MOS semiconductor integrated circuit device forming a conventional gate array. In FIG. 5, a bonding pad 2 is arranged around the semiconductor chip 1 and an internal logic gate portion 3 is provided at the center of the semiconductor chip 1.
Is arranged. This internal logic gate unit 3 has a plurality of P-types.
A basic cell consisting of a pair of a MOS transistor and a plurality of N-type MOS transistors is regularly arranged on the array. An input / output buffer 4 is provided between the bonding pad 2 and the internal logic gate unit 3 so as to surround the internal logic gate unit 3 in order to interface the internal logic gate unit 3 with the outside of the chip. .

FIG. 6 is a diagram showing a detailed configuration of the peripheral portion of the input / output buffer 4. In FIG. 6, the input / output buffer 4 is divided into the same number of input / output buffer cells 5 as the number of bonding pads 2, and the bonding pads 2 and the input / output buffer cells 5 correspond to each other in a one-to-one correspondence. The input / output buffer cell 5 includes an output P-type MOS transistor region (hereinafter referred to as an output P-MOS) 6, an output N-type MOS transistor region (hereinafter referred to as an output N-MOS) 7, and an input. Logic P-type MOS transistor region (hereinafter referred to as an input logic P-MOS) necessary to configure the input and input circuits and a logic N-type MOS transistor required to configure the input and input circuits It is composed of a region (hereinafter referred to as an input logic N-MOS) 9.

Here, in the direction from the bonding pad 2 toward the internal logic gate portion 3 (hereinafter, referred to as arrangement direction), the P-type area PA is formed.
And the N-type region NA are arranged in this order. In the P-type area PA, the output P-MOS 6 and the input logic P-MOS 8 are arranged in the direction in which the bonding pads 2 are arranged (hereinafter referred to as the arrangement direction), while the N-type area is formed. NA
, The output N-MOS7 and the input logic P-MOS6 correspond to the output logic P-MOS6 and the input logic P-MOS8, respectively.
N-MOS9 is arranged. The input / output buffer cell 5 has four types of roles: an input buffer, an output buffer, a tristate output buffer, and an input / output bidirectional buffer.

First, when used as an input buffer, the input logic P-MOS 8 and the input logic N-MOS 9 are connected, and the regions 6 and 7 other than these are not used. Next, when used as an output buffer, the output P-MOS 6 and the output N-MOS 7 are connected, and the regions 8 and 9 other than these are not used. And
When used as a tri-state output buffer and an input / output bidirectional buffer, respectively, the output P-MOS6 is connected to the output N-MOS7 and also to the input logic P-MOS8. -MOS9 is connected to the output N-MOS7 and also to the input logic P-MOS8. Therefore, considering the connection relationship of each area, the input / output buffer cell 5
Inside, the arrangement is as shown in FIG.

[Problems to be Solved by the Invention] The conventional input / output buffer cells 5 are arranged as shown in FIG. 6, and the size of the input / output buffer cells 5 in the arrangement direction corresponds to that of the bonding pad 2. Greater than. In the conventional semiconductor integrated circuit device,
One input / output buffer cell 5 is provided for one bonding pad 2. From the above, the maximum number of input / output pins that can be provided on one semiconductor chip is determined by the size of the input / output buffer cells 5 in the arrangement direction.

By the way, recently, the degree of integration of internal logic gates has improved with the progress of miniaturization technology. The number of input / output pins also needs to be increased accordingly. However, since the conventional semiconductor integrated circuit device is configured as described above, in order to increase the number of input / output pins, the number of input / output buffer cells 5 must be increased by the same number for the above reason.
Taking into consideration the size of the conventional input / output buffer cells 5 in the arrangement direction, there is a limit to the number that can be arranged on one semiconductor chip 1, and beyond that, the number of input / output buffer cells 5 can be exceeded. If the number is increased, there is a problem that the chip size of the semiconductor chip 1 is significantly increased.

Further, although the input transistor in the conventional input / output buffer cell 5 is formed in a fixed and fixed size,
The gate array must flexibly deal with a wide variety of logic circuits, and if the size of the input transistor is constant, only a certain level of interface can be obtained.

Therefore, the present invention has been made to solve the above-described problems, and it is possible to increase the number of input / output pins while suppressing the increase in the chip size without impairing the performance of the input / output buffer. An object is to obtain a semiconductor integrated circuit device that can efficiently take various input interfaces.

[Means for Solving Problems] In a semiconductor integrated circuit device according to the present invention, an internal logic gate portion provided in a central portion of a semiconductor chip and a plurality of input / output buffer cells surround the internal logic gate portion. In the semiconductor integrated circuit device including the input / output buffer provided as described above and the plurality of bonding pads provided on the outer periphery of the semiconductor chip corresponding to the plurality of input / output buffer cells, the input / output buffer cell is A first transistor region of the first conductivity type for output, a second transistor region of the second conductivity type for output, and a first transistor region of the first conductivity type for input and for the logic necessary to configure an input circuit. A third transistor region and a fourth transistor region of the second conductivity type for logic necessary for configuring an input circuit and an input circuit, and the first to fourth transistors. Region is sequentially arranged in the first direction from the bonding pad to the internal logic gate portion, and each of the third and fourth transistor regions includes a gate electrode each extending in the first direction, and A plurality of transistors arranged regularly in a second direction orthogonal to the first direction, wherein a transistor in the third transistor region and a transistor in the fourth transistor region form a pair, and a plurality of transistors in the third transistor region are included. A first metal wiring is formed above an end portion on the bonding pad side of the second metal wiring, and a second metal wiring is formed above an end portion on the internal logic gate side of the plurality of transistors in the fourth transistor region. A third metal wiring is formed above the transistor in the third transistor region and the transistor in the fourth transistor region forming the first metal region. The first power supply potential is applied to the selected transistor in the third transistor region from the line, and the second power supply potential is applied to the selected transistor in the fourth transistor region from the second metal wiring. Then, the selected transistors in the third and fourth transistor regions are connected by the third metal wiring to form an inverter necessary for forming an input circuit.

[Operation] In the semiconductor integrated circuit device according to the present invention, the first transistor region for output of the input / output buffer cell,
The second transistor region for output, the third transistor region for input logic, and the fourth transistor region for input logic are arranged in this order in one row in the first direction. Therefore, the size of the input / output buffer cell in the second direction is smaller than that in the conventional case where the first to fourth transistor regions are arranged in two columns, and more bonding pads can be arranged.

Further, each of the third and fourth transistor regions includes a plurality of transistors arranged regularly in the second direction, and the transistors in the third transistor region and the transistors in the fourth transistor region form a pair, A first metal wiring for supplying the first power supply potential is formed above the end portion of the third transistor region on the side of the bonding pad, and above the end portion of the fourth transistor region on the side of the internal logic gate portion. A second metal wiring for supplying a second power supply potential is formed on the first transistor, a third metal wiring is formed above the paired transistors, and the selected transistor and the first to third metal wirings are formed. When connected, an inverter for the input circuit is constructed. Therefore, the inverter for the input circuit can be easily configured, and the input buffer having a desired input level and the buffer with various logic circuits can be efficiently configured.

[Embodiment] FIG. 1 is a diagram showing a detailed structure of a peripheral portion of an input / output buffer of a semiconductor integrated circuit device constituting a gate array according to an embodiment of the present invention. In FIG. 1, in the arrangement direction,
An output P-MOS 6, an output N-MOS 7, and a basic cell 12 for logic (hereinafter referred to as input logic) necessary for forming an input and an input circuit are arranged. Further, on the semiconductor chip 1, between the bonding pad 2 and the output P-MOS 6, between the output P-MOS 6 and the output N-MOS 7, and the output N-MO.
An oxide film is provided between S7 and the input logic basic cell 12 and between the input logic basic cell 12 and the internal logic gate portion 3 to separate the respective regions. A plurality of input logic basic cells 12 are regularly arranged.

FIG. 2 is an enlarged view of the transistor region for input logic. In FIG. 2, the input logic basic cell 12 comprises a pair of one input logic P-MOS 13 and one input logic N-MOS 14. The basic cell 12 is an output N-MOS 7 and an internal logic gate unit 3
And are regularly arranged in the buffer array direction. Then, the power supply line 15 and the GND line 16 are respectively arranged along the arrangement direction in the input logic P-MOS 13 and the input logic N-MOS 14
Is passing over.

FIG. 3A is a diagram showing an example of an input buffer using the basic cells of the input logic area. FIG. 3B is an equivalent circuit diagram thereof. When configuring an input buffer circuit, for example, as shown in FIG. 3A, contact hole 17, first layer aluminum wiring 18, through hole 19 and second layer aluminum wiring 20 are provided.
Should be provided. In FIG. 3B, the circuit section 30 of the input buffer is an inverter composed of one P-MOS 13 and four N-MOS 14 connected in parallel, and has a TTL level interface. The circuit part 40 has two P-MOSs 13 and 2 connected in parallel.
It is an inverter consisting of N-MOS14 connected in parallel,
Drive the internal gate.

FIG. 4 is a block diagram showing the entire semiconductor integrated circuit described above. The output area 10 is composed of the output P-MOS 6 and the output N-MOS 7, and the input logic area 11 is the input logic basic cell.
It is composed of 12.

When the input / output buffer cell 5 configured as described above is used as an input buffer as in the conventional case, as shown in FIG. 3A, for example, as shown in FIG.
-When MOS14 is connected and used as an output buffer, output P-MOS6 and output N-MOS7 are connected, and when used as a tri-state output buffer and an input / output bidirectional buffer, output The P-MOS 6 for input is connected to the N-MOS 7 for output, and is also connected to the P-MOS 13 for input logic.The N-MOS 14 for input logic is connected to the N-MOS 7 for output and the P-MOS for input logic is connected. It is also connected to MOS13 and is used depending on the case.

With this configuration, the size of the input / output buffer cells 5 in the arrangement direction becomes smaller than the conventional size, and the number of the bonding pads 2 can be increased by that amount. In addition to suppressing the increase in chip size, it is possible to configure input buffers of various input levels and various buffer logic circuits simply by changing the metal wiring pattern.

In the above-described embodiment, the input logic area 11 is provided around the internal logic gate 3, the output area 10 is provided at the outer circumference thereof, and the bonding pad 2 is provided at the outer circumference thereof. The output region 10 may be provided around the gate 3, the input logic region 11 may be provided on the outer periphery thereof, and the bonding pad 2 may be provided on the outer periphery thereof. Also, P-MO for output
The S6 and the output N-MOS 7 may be replaced with each other. Further, the input logic P-MOS 13 and the input logic N-MOS 14 may be replaced with each other.

As described above, according to the present invention, since the four transistor regions of the input / output buffer cell are arranged in one column in the first direction, the input / output buffer cell in the second direction is arranged. The size is smaller than before, and more bonding pads and I / O pins can be arranged.

The third and fourth transistor regions of the input / output buffer cell include a plurality of transistor pairs regularly arranged in the second direction, and the first to third metal regions are provided above the third and fourth transistor regions. The wiring is formed, and the selected transistor and the metal wiring are connected to form an inverter for the input circuit. Therefore, an inverter for an input circuit can be easily obtained, and various input buffers and buffer logic circuits can be efficiently configured.

[Brief description of drawings]

FIG. 1 is a diagram showing a detailed structure of a peripheral portion of an input / output buffer of a semiconductor integrated circuit device which constitutes a gate array of an embodiment of the present invention. FIG. 2 is an enlarged view of the input and logic areas. FIG. 3A is a diagram showing an example of an input buffer using basic cells in the input and logic areas. First
FIG. 3B is an equivalent circuit diagram of FIG. 3A. FIG. 4 is a block diagram showing the entire semiconductor integrated circuit device of the present invention. FIG. 5 is a block diagram of a semiconductor integrated circuit device which constitutes a conventional gate array. FIG. 6 is a diagram showing a detailed structure of a peripheral portion of an input / output buffer of a conventional semiconductor integrated circuit device. In the figure, 1 is a semiconductor chip, 2 is a bonding pad, 3 is an internal logic gate section, 5 is an input / output buffer cell,
6 is an output P-MOS, 7 is an output N-MOS, 10 is an output area,
11 is an input logic area, 12 is a basic cell, 13 is an input logic P-
MOS, 14 are N-MOS for input logic, 15 is a power supply wiring, and 16 is a GND wiring. In each drawing, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiro Okuno 4-chome, Mizuhara, Itami City, Hyogo Prefecture LS Electric Co., Ltd. LSE Research Institute (72) Ichiro Tomioka 4-chome, Mizuhara, Itami City, Hyogo Prefecture (56) References JP-A-58-190036 (JP, A) JP-A-62-95852 (JP, A)

Claims (6)

[Claims] 1. An internal logic gate portion provided in a central portion of a semiconductor chip, an input / output buffer provided with a plurality of input / output buffer cells surrounding the internal logic gate portion, and a plurality of input / output buffers. In a semiconductor integrated circuit device having a plurality of bonding pads respectively provided on an outer peripheral portion of the semiconductor chip corresponding to an output buffer cell, the input / output buffer cell is of a first conductivity type first for output. Transistor region, second transistor region of second conductivity type for output, third transistor region of first conductivity type for input and logic necessary to form an input circuit, and input and input A fourth transistor region of the second conductivity type for logic necessary to form a circuit, and the first to fourth regions extend from the bonding pad to the internal logic. Are sequentially arranged in a first direction toward the gate portion, and each of the third and fourth transistor regions includes a gate electrode extending in the first direction, and in the first direction. A plurality of transistors arranged regularly in a second direction orthogonal to each other, wherein a transistor in the third transistor region and a transistor in the fourth transistor region form a pair; A first metal wiring is formed above the end on the side of the bonding pad, and a second metal wiring is formed above the end on the side of the internal logic gate of the plurality of transistors in the fourth transistor region.
Metal wiring is formed, and a third metal wiring is formed above the transistor in the third transistor area and the transistor in the fourth transistor area forming the pair, and
A first power supply potential is applied to the selected transistor in the third transistor region from the metal wiring of the second transistor, and a second power supply potential is applied to the selected transistor in the fourth transistor region from the second metal wiring. Power source potential is applied, and the selected transistor in the third and fourth transistor regions is connected by the third metal wiring to form an inverter necessary for forming the input circuit. A semiconductor integrated circuit device characterized by the above. 2. The second transistor region, the first transistor region, the third transistor region and the fourth transistor region are arranged in this order in a row in the first direction. The semiconductor integrated circuit device according to claim 1, which is characterized in that. 3. The first transistor region, the second transistor region, the fourth transistor region and the third transistor region are arranged in this order in a row in the first direction. The semiconductor integrated circuit device according to claim 1, which is characterized in that. 4. The third transistor region, the fourth transistor region, the first transistor region, and the second transistor region are arranged in this order in a row in the first direction. The semiconductor integrated circuit device according to claim 1, which is characterized in that. 5. The first transistor region, the second transistor region, the fourth transistor region and the third transistor region are arranged in this order in one row in the first direction. The semiconductor integrated circuit device according to claim 1. 6. The semiconductor integrated circuit device according to claim 1, wherein all transistors formed in the third and fourth transistor regions have the same shape.