JP2521943B2 - Programmable logic array device - Google Patents

Description

The present invention relates to a programmable logic array device.

[Prior Art] Conventionally, this type of programmable logic array (hereinafter,
(Referred to as PLA) as shown in FIGS. 4 (a) to 4 (c),
Alternatively, a programmable logic array unit (hereinafter, PLA) as shown in FIGS. 5 (a) to 5 (b) is used.
As shown in FIG. 7, there is known a matrix arrangement of i rows (i is 2 or more) and j columns (j is 2 or more) to construct an AND plane or an OR plane.

In FIG. 4 (a), 141 is a first MOS field effect transistor (hereinafter referred to as MOSFET) row, and 142 is a second MOS field effect transistor.
The respective FET columns are shown. Each MOSFET constituting the first MOSFET row 141 has drain electrodes 841 to 84n and a common gate electrode 241 made of polysilicon, and the second MOSFET row 1
Each of the MOSFETs constituting 42 has drain electrodes 941 to 94n and a common gate electrode 242 of polysilicon. 341 to
346, 441A to 44nA, 441B to 44nB, 541A to 54nA and 5
41B to 54nB indicate contact holes. First MOSFE
Since the T column 141 and the second MOSFET column 142 are connected by the common source electrode 741 formed of a diffusion layer, the equivalent circuit diagram of them is as shown in FIG. 4 (b). FIG. 4 (c) shows metal wiring 651 on the PLA unit shown in FIG. 4 (a).
6 to 662 are shown.

The PLA unit shown in FIG. 5 (a) is the first MOS.
It is composed of a FET row 161 and a second MOSFET row 162.
Each MOSFET that constitutes the first MOSFET row 161 has a drain electrode 8
The MOSFETs 61 to 86m and the common gate electrode 261 made of polysilicon are included. Each MOSFET constituting the second MOSFET row 162 has drain electrodes 961 to 96m and a common gate electrode 26 made of polysilicon.
Has 2 and. 361 to 366, 461 to 46m and 561 to
56m is a contact hole. The first MOSFET row 161 and the second MOSFET row 162 have a common source electrode 7 made of a diffusion layer.
Since they are connected by 61, they are represented by an equivalent circuit diagram as shown in FIG. 5 (b). The PLA unit shown in FIG. 5 (a) is shown in FIG. 4 (a) except that one contact hole is formed on the drain electrode.
It is the same as the PLA unit.

PLA shown in FIG. 4 (a) or FIG. 5 (a)
Placing the units in the i-th row and the j-th column as described above and connecting them by metal wiring 671 to 673 as shown in FIG.
Is completed. The PLA having such a configuration is supplied with an input signal and its inverted signal to the gate electrodes 241 and 261 of the first MOSFET row and the gate electrodes 242 and 262 of the second MOSFET row, which form each PLA unit, and is represented by a predetermined logical polynomial. Output is generated.

[Problems to be Solved by the Invention] However, when the ratio between the input signal included in a predetermined logical polynomial and its inverted signal is not 1: 1 as in the case of the enable signal of the 3-8 decoder, for example, The number of MOSFETs used in the first MOSFET string to which the input signal is supplied and the M number of the second MOSFET string to which the inverted signal is supplied are used.
There was a problem that the number of unused MOSFETs increased due to a difference from the number of OSFETs used.

Therefore, the object of the present invention is to configure the PLA unit MOSFE.
It is to improve the usage rate of T.

[Means for Solving the Problems] The present invention arranges a plurality of programmable logic array units in a matrix on a single semiconductor substrate, and each of the plurality of programmable logic array units extends in a column direction. A first transistor group controlled by an input signal supplied to an electrode and a second transistor group controlled by an inverted signal of an input signal supplied to another control electrode extending in the column direction.
In a programmable logic array device having a first wiring group that selectively connects the first transistor group and the second transistor group of the plurality of programmable logic array units, including a transistor group, between adjacent rows of programmable logic array units. Is provided with a short-circuit wiring, and the control electrodes belonging to the rows of the programmable logic array units adjacent to each other are selectively connected by the second wiring group via the short-circuit wiring.

[Operation of the Invention] In order to generate an output in accordance with a predetermined logical polynomial in the programmable logic array device having the above-described configuration, the first wiring group is connected. However, the first input signal is supplied
When the number of constituent transistors of the transistor group and the number of constituent transistors of the second transistor group to which the inverted signal of the input signal is supplied are far from the ratio of 1: 1, programmable by the wiring for short circuit and the second wiring group The control electrodes of the logic array unit can be connected, and the constituent transistors can be interchanged between the first transistor group and the second transistor group.

[Examples] Examples of the present invention will be described below.

1 (a) and 1 (b) show a first embodiment of the present invention. In FIG. 1 (a), reference numeral 1 denotes a first PLA unit, and first PLA unit 1 is a first PLA unit. It has one MOSFET row 2 and a second MOSFET row 3. The PLA according to the first embodiment further includes a second PLA unit 4, and the second PLA unit 4
Also has a first MOSFET row 5 and a second MOSFET row 6. 1st P
The LA unit 1 includes a common source electrode 701 composed of a diffusion layer and a first
It has a drain electrode 801 and a common gate electrode 201 of the MOSFETs forming the MOSFET row 2, and further forms a second MOSFET row 3.
A drain electrode 802 of the MOSFET and a common gate electrode 202 are provided. On the other hand, the second PLA unit 4 has a common source electrode 702 formed of a diffusion layer, a drain electrode 803 of the MOSFETs forming the first MOSFET row 5, and a common gate electrode 203, and further has a second MOS.
The drain electrode 804 and the common gate electrode 204 of the MOSFETs forming the FET row 6 are provided. The PLA according to this embodiment is further
A wiring layer of polysilicon between the region where the 1PLA unit 1 is formed and the region where the second PLA unit 4 is formed.
It has a common gate electrode 201, 202, 203, 204
Is a short-circuiting metal wiring 60 that passes through the contact holes 301 to 306.
It is connected by 1, 602 and 603.

These short-circuiting metal wirings can be selectively provided, and as shown in FIG.
The use of metal wiring 611 to 613 passing through
The common gate electrode 202 of the second MOSFET row 3 of the PLA unit 1 can be connected to the common gate electrodes 203, 204 of the second PLA unit 4. As a result, the constituent MOSFETs can be interchanged between the first PLA unit and the second PLA unit.

For example, 4 with an enable signal in the output logic polynomial
When a −16 decoder is included, the ratio of the number of MOSFETs to which the enable signal is supplied and the number of MOSFETs to which the inverted signal of the enable signal is supplied deviates significantly from 1: 1. Is a ratio close to 1: 1. Therefore, the size of the PLA included in this decoder is calculated according to the following conditions.

H = (contact hole size) = 2 microns HM = (contact hole-metal wiring margin) = 2 microns MW = (metal wiring width) = 2 microns MG = (metal wiring interval) = 2 microns FG = (diffusion Interval) = 1 micron HF = (contact hole-diffusion margin) = 2.5 micron HP = (contact hole-polysilicon margin) = 2.5 micron PW = (polysilicon width) = 2 micron PG = (polysilicon interval) = 2 micron PFG = (polysilicon-diffusion interval) = 1 micron Also, the number of transistors in each MOSFET row of the PLA unit is 4.

The column direction length U of the PLA unit shown in FIG. 4 (a) is U = (HP + H + HP + PFG) × 2 + 4 × (HF + H + HM + H + HF) + 3 × FG or U = (HP + H + HM + MG) × 2 + 4 (MW + MG + HM + H + HM) + 3 × HG Above Substituting the numerical values of the conditions gives U = 63 microns. On the other hand, if the PLA unit interval in Fig. 6 is G1, then G1 = PG = 2 microns.

The number of PLA units in the column direction when the 4-16 decoder is implemented by conventional PLA units is A = (the number of required product terms) ÷ (the number of product terms that can be used in one PLA unit) = 16 ÷ 4 = 4 Conventional PLA The length H1 in the column direction when realized with a unit is H1 = U * A + (A-1) * G1 = 258 microns.

Next, calculation will be made for the case where the PLA unit shown in FIG. 1 constitutes a 4-16 decoder. When the spacing between the PLA units shown in FIG. 1 is G2, G2 = 2 × PG + 2 × HP + H = 11 microns, and in this embodiment, the number of product terms used in one PLA unit can be increased to eight. , 2 PLA units
One is enough. As a result, the length H2 in the column direction is H2 = U * 2 + (2-1) * G2 = 137 microns, which was 258 microns in the conventional example but 137 microns in this example.

Comparing the case of the conventional example shown in FIG. 5 (a), the column length U1 is U1 = (HP + H + HP + PFG) × 2 + 4 × (HF + H + HF) + 3 × FG or U1 = (HP + H + HM + MG) × 2 + 4 X (HM + H + HM) + 3 x FG and U1 = 47 microns.

Therefore, the total column length H3 is H3 = U1 × 4 + (4-1) × G1 = 194 microns. The advantages of the present embodiment are also apparent when this H3 is compared with the above H2.

FIG. 2 is a plan view showing the configuration of the second embodiment of the present invention. In the PLA according to the second embodiment, the short circuit wiring is realized by the diffusion layer 723. Since other configurations are the same as those of the PLA of the first embodiment, only the corresponding numbers are attached and the description is omitted.

FIG. 3 shows a PLA according to the third embodiment of the present invention. In the PLA according to the third embodiment, the line width of the short circuit wiring 235 other than the contact region is narrowed. Other configurations are first
Since it is the same as the PLA of the embodiment, only the corresponding numbers are attached and the explanation is omitted.

EFFECTS OF THE INVENTION As described above, according to the present invention, the short circuit wiring is provided between the rows of the programmable logic array units adjacent to each other, and the control electrodes belonging to the rows of the programmable logic array units adjacent to each other are connected to the short circuit wiring. Since the second wiring group is selectively connected through the wirings, even if the number of transistors to which an input signal is supplied and the number of transistors to which an inverted signal of the input signal is supplied are different, the above-mentioned transistors are similar. The number can be balanced, and the use efficiency of the transistor can be improved.

[Brief description of drawings]

FIG. 1 (a) is a plan view showing a configuration of a first embodiment of the present invention, FIG. 1 (b) is a plan view showing another wiring example of the first embodiment of the present invention, and FIG. FIG. 4 is a plan view showing the configuration of the second embodiment of the invention, FIG. 3 is a plan view showing the configuration of the third embodiment of the present invention, and FIG. 4 (a) is a plan view showing a conventional PLA unit. b) is an equivalent circuit diagram showing a conventional PLA unit, FIG. 4 (c) is a plan view showing a program sequence of the conventional PLA unit, and FIG. 5 (a) is a plan view showing another conventional PLA unit. FIG. 5 (b) is an equivalent circuit diagram showing another conventional PLA unit, FIG. 6 is a plan view showing connection wiring of a conventional PLA, and FIG. 7 is a plan view showing wiring of a conventional PLA. . 1 ... 1st PLA unit, 2 ... 1st MOSFET row, 3 ... 2nd MOSFET row, 4 ... 2nd PLA unit, 5 ... 1st MOSFET row, 6 ... 2nd MOSFET row, 205 ... Short circuit wiring, 235 ...... Short circuit wiring, 601, 602, 603 ... Second wiring group, 701 ... Control electrode (gate electrode), 702 ... Control electrode (gate electrode), 723 ... Short circuit wiring.

Claims (1)

(57) [Claims] 1. A plurality of programmable logic array units are arranged in a matrix on a single semiconductor substrate, each of the plurality of programmable logic array units is provided with an input signal supplied to a control electrode extending in a column direction. A first transistor group to be controlled and a second transistor controlled by an inversion signal of an input signal supplied to another control electrode extending in the column direction.
In a programmable logic array device having a first wiring group that selectively connects the first transistor group and the second transistor group of the plurality of programmable logic array units, including a transistor group, between adjacent rows of programmable logic array units. A programmable logic array device characterized in that a short-circuit wiring is provided in the control circuit, and the control electrodes belonging to rows of the programmable logic array units adjacent to each other are selectively connected by the second wiring group via the short-circuit wiring.