JPS6258487A - Static type memory - Google Patents

Abstract

PURPOSE:To reduce the power consumption due to the decrease in the electric current consumption time by executing a precharging equalizing action by a precharging equalizing circuit until the selection of a section word line is started in a selecting cycle, concerning the bit line in the selecting section. CONSTITUTION:At respective columns in the selecting section, before the selection of a section word line SWL is selected in an address cycle, a bit line precharging equalizing circuit 1 is operated by a bit line precharging signal phiPC, and bit lines BL and the inverse of BL are precharged and equalized. Next, after a section word line SWL is selected and a memory cell is selected, the bit line precharging and equalizing circuit 1 comes to be the off condition, at the time of the reading mode, the bit lines BL and the inverse of BL are driven only by the selected memory cell and therefore, the bit line at the low electric potential side drops from the precharging level to a VSS level finally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory, and more particularly to a bit line drive system of a static memory in which a memory cell array is divided into a plurality of sections and has an auto power-down function.

[Technical background of the invention]

Traditionally, static type random access memo! J (S
In order to speed up the read operation of RAM), the voltage amplitude of the bit line during read is reduced. For this purpose, for example, a pair of bit lines BL in each column as shown in FIG.

An always-on type load MOS) transistor (for example, P-channel type) Q51'Q5□ is connected to i, and the low potential (L) side of the static deaf memory cell MC selected by word 6wr during reading is connected to A drive transistor (Q5 in this example) and a transfer gate transistor Q connected in series with it.
54 are turned on, and the bit line I3 on the low potential side is turned on.
The potential of L is set to an intermediate level between the DD power supply potential and V,8 (ground potential).The bit line BL on the high potential (H) side is at VDDt.In this case, naturally the low potential A DC through current flows through the path of the side load transistor Q5□→pit line BL→transfer transistor Q54→drive transistor Q53.

On the other hand, in an SRAM in which the memory cell array is divided into two sections, one section is selected and the other section is deselected by address input, each section has, for example, an 81c x 8 pit configuration of 128 columns x 2560. SRAM is known. In this SRAM, the through current flows in each of the 128 columns in one selected section, so a very large operating current is consumed.

In order to reduce such bit line through current, it is sufficient to reduce the number of memory cells that are simultaneously selected. For example, in the above-mentioned 8 x 8 pit SRAM, if the memory cell array is divided into eight sections and the word line is in the non-selected state in four sections other than the selected section, the bit line through current can be reduced. Since the number of columns in which this occurs is significantly reduced from 128 columns to 32 columns, the power consumption due to the pit line through current is reduced to τ.

On the other hand, if the memory is operated only for the minimum cycle time indicated to the user, and the data at the selected address is output to the output buffer and latched, the time within the subsequent address cycle is controlled by the memory's internal circuits. is not necessarily required to remain in operation. That is, the memory is
Control is automatically performed inside the memory chip to keep the internal circuit in an operating state for a period slightly longer than the minimum cycle time after a change in the address signal input, and to deactivate the selected word line etc. after a series of read operations ( By implementing this function (referred to as auto power down), it is possible to reduce power consumption by reducing current consumption time.

An example of a memory having section division of the memory cell array and auto arm down function as described above is
l5SCC1984, Digest of Techni
cal Paper P, 214+215,340@
A46ns256k CMO8RAM" was announced by Isobe et al. This RAM (static type)
The memory cell array is divided into 16 pieces, 512 pieces.
Columns (=32 columns x 16 sections) x 5120-
The structure is as follows. FIG. 7 shows a part of one RAM in each section of this SRAM, and the memory cell M of the section selected by the Cefsilane word line pattern is shown in FIG.
C is now selected. However, this SRA
M also uses a bit line load of P-channel transistors Q and Q that are always on, so
A bit line through current as described above is generated within the selected section. In addition, the auto power down function in this SRAM detects changes in the address input during the read cycle, generates a basic clock inside the memory chip, and stretches this basic clock to a pulse longer than the minimum cycle time using a delay circuit inside the chip. , while the i4 pulse is occurring, the memory remains in an operating state, but after the pulse ends, the output data is latched, the word line, sense amplifier, etc. are inactivated, and the memory enters a low power consumption state. Therefore, in the read mode, the longer the cycle time, the greater the advantage of reducing the power consumption of the chip, which is shown in FIG. On the other hand, the auto power down function is not used in write mode. The reason for this is that in a write cycle, the data input signal input last in the same address cycle must be written to the memory cell at the input address. This is because it is not allowed to close the word line and make the memory cells unselected. Therefore, considering that during a write cycle, the bit line through current continues to flow from the always-on bit line load to one of the bit line pairs.
In the write cycle, unlike the above-mentioned read cycle, the advantage of reducing power consumption by extending the cycle time cannot be obtained.

[Problems with background technology]

As mentioned above, in order to reduce power consumption, conventional SRAMs adopt section division and an auto power-down function to limit the memory internal circuit operation time during the read cycle. A direct current through current is temporarily generated in the bit line of the section, and since the auto power down function does not work during the write cycle, the direct current through current continues to flow through the bit line of the selected section, causing consumption. It cannot be said that the power is necessarily reduced sufficiently.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and can significantly reduce power consumption associated with bit line driving, and achieves low power consumption in write mode as well as in read mode when cycle time is long. The purpose of the present invention is to provide a static memory that is capable of realizing high-speed read operations.

[Summary of the invention]

That is, in the present invention, a memory cell array is divided into a plurality of sections, and section selection control of the memory cell array is performed such that memory cells in a selected section are selected but memory cells in unselected sections are not selected. .

In a static memory that also has an auto power-down function, the bit line in the unselected section is always on during the unselected cycle time as a bit line drive system that reads the data stored in the memory cell through the memory cell transfer dart. The controlled bit line pull-up transistor performs a pull-up operation, and the bit line in the selected section is precharged and equalized by the precharge/equalization circuit before the section word line selection begins in the selection cycle. After the automatic power-down function operates and the section word line shifts to a non-selected state, a bit line pull-up transistor performs a pull-up operation similarly to the non-selected section. It is characterized by this.

Therefore, since no direct current flow through the bit line occurs in the bit line in either read mode or write mode, not only does the power consumption itself decrease significantly, but when the cycle time is lengthened, the cycle time Lower power consumption is realized in inverse proportion.

Further, since the bit line is driven only by the selected memory cell during reading, the potential change of the bit line on the low potential side is accelerated, and the access time in the read operation is accelerated.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows two adjacent sections 5E in an SRAM in which the memory cell array is divided into a plurality of sections.
For CJ and 5EC2, each typically includes a bit line precharge/equalization circuit 1 for one power ram, a two-man NAND circuit 2 for generating precharge/equalization signals, and bit line BL, BL, and bit line pull. an up transistor Q, a pit line pull-up transistor BP, an inverter circuit 3 for driving the BP star, and a memory cell MC.
a write control circuit 4, a bit line selection transistor Q,
, Qll and sense 19ss in each section
, SS, section sense amplifier SSA,
Sense line pull-up transistor Q, Q, sense line pull-up transistor sp The word line texture and bit line equalization signals ill BEL are shown.

That is, the bit lines BL, BL are not normally connected with on-off loads, and the bit line precharge/equalization circuit 1 is turned on in synchronization with the bit line precharge signal fan.
is connected. Each section has a section selection signal St defined by the output of a section decoder (not shown) and a predetermined timing signal, 82 VC.
The operation is controlled by being selectively selected, and the section selection signal 5led! is one input of the inverter circuit 3.5 and the NOR circuit 6 of the corresponding sector 1. The main word line 2 is connected as the other input of this NOR circuit 6, and the output of the inverter circuit 3 is one input of the NAND circuit 2, and the other input of this NAND circuit 2 is a bit. A line equalization signal line BEL is connected thereto. The bit line pull-up transistor Q! IP I QUIP consists of a P-channel transistor connected between the bit lines BL and BL and the vDDlrJL source, and the output of the inverter circuit 3 is connected to each dart. In addition, the sense line pull-up transistor Q8I
' IQ8F consists of a P-channel transistor connected between the sense lines ss, ss and the vDD power supply, and each dart is connected to the output of the inverter circuit 5.

Note that the memory is provided with an auto power down function in the read mode, although not shown.

The write control circuit 4 also includes a nine-channel transistor Q4 connected between the bit line BL and the write control signal line 41, and an N-channel transistor Q4 connected between the bit line BL and the write control signal line 41. It consists of a transistor Q4 and an inverter circuit 4 which inverts a column selection signal CD from a column decoder (not shown) and applies it to each of the transistors Q4 (ff-) of Q4.

Next, the bit line driving operation in the above memory will be explained with reference to FIG. In each column in the selection section, the bit line precharge/equalization circuit 1 is operated by the bit line precharge signal fan to precharge and precharge the bit lines BL and BL before the selection of the sexy word line starts in the address cycle. Equalization is performed. Next, after the section word line skin is selected and the memory cell is selected, the bit line precharge/equalize circuit 1 is in an off state. Therefore, in read mode, bit line B
L.

Since BL is driven only by the selected memory cell, the bit line on the low potential side (in this example, BL) goes from the precharge level (vDD potential) to finally the v3s level (
(ground potential). In this case, the bit line charge stored in the precharge is only discharged by the transfer gate transistor and drive transistor on the low potential side of the memory cell MC, so the potential change of the bit line BL on the low potential side is accelerated. Therefore, it is possible to achieve faster access times. During the read cycle, there is no direct current through current in the bit lines BL, BL, and the bit lines BL, BL maintain one of the different levels of the vDD potential and the ground potential. Then, after the word-down function operates and the selected section word line status shifts to a non-selected state, the bit line pull-up transistor QBPl'IP and the sense line pull-up transistors Q and Q are always on. Tepi SP
A pull-up operation is performed on the 8P lines BL, BL and the sense lines ss, ss. Similarly, the bit lines BL and sense lines ss of each column in the unselected section,
Regarding ss, bit line pull-up transistors Q and Q are always on during non-selection cycle time.
A pull-up operation is performed by the pull-up transistor Q8PIQ8F on the sense line BP BP .

FIG. 3 shows the signal waveforms of various parts in the read mode described above. That is, after the address input changes, the bit line equalize signal φ□9 goes to high level (H), and the section selection signal S1 goes to low level (L) in the selected section (and Eva 5EC7), and the output φPU of the inverter circuit 3 and the output φ of the inverter circuit 5
P118B becomes high level. As a result, the output of the NAND circuit 2 (bit line precharge signal φ1
．． ) becomes low level, and the bit line precharge/equalize circuit 1 is turned on. Next, when the bit line equalization signals φll and Q become low level and the main word line skin becomes low level, the output of the NAND circuit 2 becomes high level, and the output of the NOR circuit 6 (section word shift signal) becomes low level. The signal returns to high level, the pit line precharge/equalize operation is completed, and the memory cell MC is selected. As a result, in each column of the selection section 5ECI, the potential of the bit lines BL, BL is determined according to the data of the selected memory cell MC (in this case, the bit line on the low potential side goes from the vDD potential to the ground potential eventually). change). Then, the bit line data of the column selected by the column decoder output CD is set as
r, line ss, ss Sense anzo S for section
It is sense amplified by SA. During such a period from precharging to sensing, the bit line pull-up transistor QBp*+stone 5 is connected to the output φPU of the inverter circuit 3.
(high level), and the sense line pull-up transistor Q8F' is turned off by the output "PU811" (high level) of the inverter circuit 5.Then, the automatic four-power down function is activated in the selection section. After that, in the non-selected section, the section selection signal goes low, the outputs of the inverter circuits 3.5 are at low level, and the bit line pull-up transistor QBpe and the sense line pull-up transistor QIIP I QIIF are turned off. Each is on, and the bit lines BL, BL and sense lines ss, ss are each pulled up.

Note that in the read mode, the signals din*din of the write control signal lines 41 and 41 are respectively at high level, and the write control transistors Q<, -Q4
are in the off state.

Therefore, in read mode, bit line BL
, since no DC-like through current occurs through the BL, not only does the power consumption itself in the read operation decrease significantly, but when the cycle time in read mode is lengthened, the power consumption is inversely proportional to the cycle time. As a result, lower power consumption is achieved. Further, since the potential change of the bit line on the low potential side during reading is accelerated, the access time in the reading operation is accelerated.

On the other hand, FIG. 4 shows the signal waveforms of various parts in the write mode. That is, after a change in the address input, the bit line precharge signals φ and C are used in the selected section to perform recharging and equalization, and the process is the same as in the read mode until the sexy word line is selected. When writing data "1", for example, at the same time as memory selection, the write control signal line 41
,41. The signals din l din are respectively vDD
The potential is pulled up and pulled down to the vss potential. As a result, in the selected column, the output of the inverter circuit 4 (
The bit lines BL and BL are set to different one of the vDD potential and the ground potential. However, in non-selected columns, write control is performed by the output (low level) of the inverter circuit 42. transistor Q
4. Since Q4 is turned off, the bit lines BL and B
L will change according to the data of the selected memory cell. Note that in the write mode, the auto-no-knock-down function does not work, so the section selection signal continues in the selected section until the next address input. The selected state of the word line Gai, the off state of the bit mf pull-up transistor QBP I QBP, and the off state of the sense line pull-up transistor Q8P #qsp continue until the next address input.

On the other hand, in the unselected section, the bit lines BL, BL and the sense lines ss, s
s are each pulled up.

Therefore, in write mode, bit line BL
, since no DC-like through current occurs through the BL, not only the power consumption itself in the write operation is greatly reduced, but also the cycle time increases when the cycle time in the write mode is lengthened. As in the read mode, power consumption is reduced in inverse proportion.

〔Effect of the invention〕

As described above, according to the static memory of the present invention, power consumption associated with pit line driving can be significantly reduced, and power consumption can be reduced even when the cycle time is long in the write mode as well as in the read mode. This is possible, and moreover, it is possible to realize faster read operations.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a part of an embodiment of the static memory of the present invention, FIG. 2 is a signal waveform diagram showing pit line driving operation in each column of the selected section in the memory of FIG. 1, and FIG. Figures 3 and 4 are signal waveform diagrams showing the operation of each part in the read mode and write mode, respectively, in the memory of Figure 1, and Figure 5 is a diagram of the conventional SRAM.
6 is a circuit diagram showing a part of each column in FIG. 6, a signal waveform diagram showing a read operation in the column in FIG.
The figure is a circuit diagram showing a part of each column of a divided section in a conventional SRAM with an auto power-down function, and the whistle figure 8 shows the relationship between cycle time and power consumption in read mode in the SRAM of Figure 7. FIG. 5E (J, 5EC2... section, BL, BL
...Bit line, ss, ss...Sense line, BEQ・
・・Bit line equalization signal line, MM, ・・Main word line, 8WL ・・Section word line, MC・
...Memory cell, SSA...Sense amplifier for section, Q, Q-...Bit line +IP
! IP pull-up transistor, QBp + Qgp...'Sense line pull-up transistor, 1...Bit line precharge/equalization circuit, 2...NAND circuit, 3.
5...Inverter circuit. Applicant's agent Patent attorney Takehiko Suzue Ran figure 8

Claims (2)

[Claims] (1) The memory cell array is divided into a plurality of sections, and section selection control of the memory cell array is performed so that memory cells in a selected section are selected but memory cells in unselected sections are not selected, and automatic In a static memory with a power-down function, the bit line in the unselected section is controlled to be always on during the unselected cycle time, as a bit line drive system that reads data stored in the memory cell through the memory cell transfer gate. A bit line pull-up transistor performs a pull-up operation, and a pre-charge/equalize circuit performs a pre-charge/equalize operation on the bit line in the selected section before selection of the section word line begins in the selection cycle. After the auto power down function operates and the section word line shifts to a non-selected state, a bit line pull-up transistor performs a pull-up operation similarly to the non-selected section. Static memory characterized by (2) The sense line connecting between the section sense amplifier provided for each section and each column is also pulled up by a sense line pull-up transistor in the same way as the bit line. 2. A static memory according to claim 1, characterized in that: