JP2996400B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial application field Conventional technology (Fig. 5) Problems to be solved by the invention (Fig. 6) Means for solving the problems Actions Embodiment of the present invention Embodiment (FIGS. 1 to 4) Effects of the Invention [Summary] In a semiconductor memory device, an object of the present invention is to increase a read speed, and to provide a plurality of word lines and a plurality of bit line pairs, and a word line and a bit. A memory cell array having a plurality of memory cells provided at intersections of line pairs, a word decoder for selecting one of the plurality of word lines, and selectively selecting the plurality of bit line pairs and the data lines. A plurality of connecting means for connecting; a column decoder for selecting the plurality of connecting means;
Signal output means for detecting the occurrence of a predetermined potential difference in the bit line pair and outputting an operation start signal for starting the operation of the column decoder; and A transistor for shutting off a power supply path of the signal output means is provided while a signal output in response to the operation indicates inactive.

[Industrial applications]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device intended to increase a reading speed.

In recent years, with the advance of miniaturization technology, semiconductor devices have tended to be more highly integrated.
2. Description of the Related Art A semiconductor memory device such as an access memory has dramatically increased its storage capacity. On the other hand, the semiconductor memory device is required not only to reduce the bit cost accompanying the increase in capacity but also to achieve a higher operation speed (for example, a read speed).

[Conventional technology]

Generally, in a read operation in a semiconductor memory device such as a DRAM, one word line pair is first activated, and all memory cell information connected to this word line pair is taken out to a bit line pair. By specifying a line pair, information of one memory cell connected to the intersection of the bit line pair and the word line pair is read.

FIG. 5 is a diagram showing the timing of each part waveform at the time of reading. In FIG. 5, WD is a word select signal,
S / A is the sense amplifier drive signal, CL is the column select signal, BL
And XBL represent the potential of each line of the bit line pair.

Now, when one word line pair is selected and activated based on the word address signal, WD rises accordingly. Next, when S / A rises, the sense amplifier starts operating and amplifies the potential difference between BL and XBL. Then, when a certain time Td elapses from the rise of S / A, CL rises, and a potential difference between one BL and XBL specified by the column address signal is extracted and output as memory cell information.

[Problems to be solved by the invention]

However, in such a conventional semiconductor memory device, the rise time of CL is set to be a certain time Td after the rise of S / A, and when setting this Td, sufficient time for BL and XBL is required. Predicted time Tdff for applying potential difference
(Td = Tdff + α) by adding a predetermined margin time + α in consideration of the variation in the actual time Tdf in which a sufficient potential difference is applied to BL and XBL, for example.
Even if f ′ is earlier than the above Tdff, the rise of CL is uniquely determined by the above (Tdff + α).
There is a problem that the read speed is delayed by [(Tdff + α) −Tdff ′].

In particular, in a semiconductor memory device using a high-speed read memory cell that makes full use of a diffusion capacitance reduction technology or a 1/2 Vcc bit line preset charging method, etc., even when the above Tdff 'is performed at a sufficiently high speed. Regardless, the actual reading speed is regulated by Td (Td = Tdff + α), and a dead time Tx (Tx = Td−Tdff ′) occurs as shown in FIG. 6, so that there is a great problem in terms of performance improvement.

The present invention has been made in view of such a problem, and has been developed based on an actual potential difference applied to a bit line pair.
The purpose of this is to increase the read speed by determining the rise timing.

[Means for solving the problem]

A memory cell array having a plurality of word lines and a plurality of bit line pairs and a plurality of memory cells provided at intersections of the word lines and the bit line pairs,
A word decoder for selecting one of the plurality of word lines, a plurality of connection means for selectively connecting the plurality of bit line pairs and the data line, and a column decoder for selecting the plurality of connection means. Signal output means for detecting that a predetermined potential difference has occurred between the bit line pair and outputting an operation start signal for starting the operation of the column decoder, wherein the word decoder is provided in the signal output means. A transistor for shutting off a power supply path of the signal output means while a signal output in response to the above operation indicates inactive.

(Operation)

According to this, when the signal output means is activated by a signal output in response to the operation of the word decoder, the signal output means controls the operation of the column decoder in response to the actual potential difference of the bit line pair. An operation start signal to be started is output. Therefore, the operation of the column decoder, that is, the operation of selecting one of the plurality of connection means for selectively connecting the plurality of bit line pairs and the data line (that is, the read operation of the memory cell) is performed by the actual potential difference of the bit line pair. For example, a high-speed read operation can be achieved by arbitrarily exhibiting the high-speed operation even for a constrained memory cell, and the signal output unit is not activated, that is, the non-operation of the signal output unit. Since no operating current flows into the signal output means during the period, useless power consumption is suppressed.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

 1 to 4 are views showing one embodiment of the present invention.

First, the configuration will be described. In Figure 1, 1 is a semiconductor memory device, the semiconductor memory device 1, a plurality of word lines (in the figure to omit one of the pair of lines) in accordance with the word address signals W _AD from outside WL ₀ ~WLn And a word decoder 2 for outputting a word selection signal WD at the time of selection, and a plurality of word lines and a plurality of bit line pairs (one of the pairs is shown in the figure) BL and XBL A memory cell M (DM is a dummy cell) is connected to the intersection, and a memory cell array 3 in which the memory cells M are arranged in a matrix and a bit line pair BL and XBL are provided for each pair, and a sense amplifier driving signal S / A Operates according to BL, XBL
Sense amplifier 4 for amplifying the potential difference between
Connection means 6 provided for each pair of L and XBL, for connecting one BL and XBL to the data bus 5 in accordance with the column selection signal CL;
If, when a predetermined operation start signal ST is inputted, starts a column selection operation based on the column address signal C _AD, a column decoder 7 which outputs a column selection signal CL with respect to the corresponding connecting means 6, the word decoder While the WD from 2 is being input, the potential difference between the bit line pair BL and XBL is monitored,
When the potential difference reaches a predetermined value (Vdff), a signal output circuit (corresponding to signal output means described in the gist of the invention) 8 that outputs an operation start signal ST is provided.

FIG. 2 is a circuit diagram showing an example of the signal output circuit 8,
An example of an EE configuration is shown. 2, the signal output circuit 8 includes power supplies Vcc and Vss (the power supply line of Vcc corresponds to the first power supply line described in the gist of the invention, and the power supply line of Vss corresponds to the second power supply line described in the gist of the invention. (Corresponding to a line), the following four N-channel MOSFETs (T _{1 to} T ₄ ) are connected by totem pole connection. That, T ₁ is the load transistor, T ₂ is WD
There transistor conducting with rises to "H" (corresponding to the blocking means described in the Summary), T ₃ is a transistor that conducts a BL rises to "H", T ₄ the XBL is "H" It is a transistor that conducts when it rises. That is, in the signal output circuit 8, T ₃ and T ₄ are conducting before the read operation in which BL and XBL are precharged to Vcc. At this time, WD rises to “H” and T ₂ becomes conducting. also, the node between T ₂ and T ₃ are maintained substantially 0V (approximately Vss) without being charged. Then, BL, first BL sticks potential difference XBL, when one of XBL begins to fall to "L", the beginning changed to one of T ₃ or T ₄ is non-conducting, the potential rises toward the Vcc. T ₃
Or when one of the T ₄ is completely non-conductive, the potentials
Vcc−Vth ₁ (Vth ₁ : threshold voltage of T ₁ ), and this voltage is output as the operation start signal ST.
As described above, the signal output circuit 8 detects the potential difference applied to BL and XBL, and outputs the operation start signal ST in response to the detection.

FIG. 3 is a circuit diagram showing another example of the signal output circuit 8 and shows an example of a CMOS configuration. In the drawing, transistors with a circle represent P-channel MOSFETs, and transistors without a circle represent N-channel MOSFETs.

In FIG. 3, the signal output circuit 8 includes a transistor T ₅ which conducts the BL is "L", the transistor T ₅ 'which conducts when XBL is "L", the transistors that conduct when WD is "H" T ₆ and T ₆ ′ (corresponding to the blocking means described in the gist of the invention), a transistor T _{7 which} is turned on when BL is “H”,
Includes a transistor T ₈ which conducts when XBL is "H", the a, T
₅ , T ₆ , T ₇ , and T ₈ are connected by totem pole connection, and T ₅ and T ₆ are connected in parallel with T ₅ ′ and T ₆ ′ with a common node. Even in this case, BL, while the XBL are precharged to Vcc, almost = Vss becomes connected to Vss via the T ₇ and T _8, and, BL, when one of XBL becomes "L" (Ie, when the cell information is read), one of T ₇ and T ₈ changes to non-conducting, and T ₅ ,
One of T ₅ ′ becomes conductive, and T ₆ becomes conductive when WD = “H”.
Vcc is charged through T ₆ ′, and this potential is output as the operation start signal ST.

 Next, the operation will be described.

Word when the address signal W _AD is input, the word decoder 2 selects one word line pair decodes W _AD (hereinafter, referred to as the selected word line pair is selected word line pair). A plurality of memory cells are connected to the selected word line pair in the word direction, and a bit line pair is connected to each memory cell. Potential difference (BL = “H”, XBL = “L” or BL = “L”, XBL =
“H”).

On the other hand, from the word decoder 2, word selection signal WD in accordance with the decoding of the W _AD has been output (WD = "H"),
This WD and the potential difference between the bit line pair described above are input to the signal output circuit 8.

In the signal output circuit 8 shown in FIG.
= "H", BL, when the XBL = "H", all the T ₁ through T ₄ is turned on, is kept substantially Vss. In this case, BL, potential difference XBL (e.g., XBL is a change in "L") when the start regard, T ₄ is moving towards a non-conductive side. And BL, XBL
When the potential difference between them becomes relatively large (the potential difference at this time is
Vdff), T ₄ becomes completely non-conductive, and the potential of
increased to c-Vth _1, this enhanced potential is output as an operation start signal ST. That is, the operation start signal ST
Since the potential of () rises in response to the potential difference between BL and XBL, for example, the time from activation of the word line pair to the application of the potential difference between BL and XBL is relatively short. In such a case, the operation start signal ST can be output at a high speed following the rapid change of BL and XBL.

Referring again to FIG. 1, the operation start signal ST is applied to the column decoder 7, and the column decoder 7
The output operation of the column selection signal CL based on the column address signal _CAD is started by the input of ST. As a result, the predetermined connection means 6 is designated, and the bit line pair BL, XBL corresponding to the connection means 6 is connected to the data bus 5.
As a result, the cell information of the data bus 5 on the word address signals W _AD and column address within the signal C _AD 1 a memory cell selected by M is read.

As described above, in this embodiment, the operation start signal ST for starting the operation of the column decoder 7 in response to the actual potential difference between BL and XBL is output.

Accordingly, as shown in FIG. 4, the operation timing of this embodiment is such that the node (ie, ST) of the signal output circuit 8
Changes in response to the potential difference Vdff between BL and XBL. For example, when Vdff appears earlier than the illustrated position (left side from the illustrated position), ST also follows this Vdff and moves to the left in the figure. Moving. As a result, the CL moves in the same manner, and the read operation in response to Vdff is performed.For example, even for a high-speed memory cell, the high-speed readout can be achieved by fully exhibiting the high-speed operation. it can. Although WD, S / A, and CL in FIG. 4 indicate those boosted above Vcc, the present invention is also applied to those not boosted.

Further, BL and XBL input to the signal output circuit 8 may be extracted from a specific bit line pair, or may be extracted from a dummy bit line pair. This redundant bit line pair may be diverted. Even in this case, since the potential difference is input to the signal output circuit 8, the same operation and effect can be obtained.

〔The invention's effect〕

According to the present invention, a particularly advantageous effect is obtained in that the high-speed memory cell can exhibit its high-speed performance without fail and increase the read speed, and can also suppress unnecessary power consumption.

[Brief description of the drawings]

1 to 4 are diagrams showing an embodiment of the present invention. FIG. 1 is a block diagram of a main part thereof, FIG. 2 is a circuit diagram showing an example of a signal output circuit thereof, and FIG. FIG. 4 is a circuit diagram showing another example of the output circuit, FIG. 4 is a main signal waveform diagram for explaining the operation thereof, FIG. 5 is a main signal waveform diagram of a conventional semiconductor memory device, and FIG. FIG. 4 is a main signal waveform diagram of a semiconductor memory device including a memory cell. 2 Word decoder 3 Memory cell array 6 Connection means 7 Column decoder 8 Signal output circuit (signal output means) WL _{0 to} WLn Word lines BL and XBL Bit line pair, M: memory cell, T6, T6 ': transistor (cutoff means).

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuhiro Fujii 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Hiroshi Nagayama 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited ( 72) Inventor Masaaki Fujikawa 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Co., Ltd. (72) Inventor Kazuto Sato 2-1844-2 Kozoji-cho, Kasugai-shi Aichi Prefecture Inside Fujitsu VSI Inc. (56) References JP-A-61-22492 (JP, A) JP-A-60-247896 (JP, A)

Claims (1)

(57) [Claims] 1. A memory cell array having a plurality of word lines and a plurality of bit line pairs, and a plurality of memory cells provided at intersections of the word lines and the bit line pairs, and one of the plurality of word lines. A plurality of connection means for selectively connecting the plurality of bit line pairs and the data lines; a column decoder for selecting the plurality of connection means; and a predetermined potential difference between the bit line pairs. Signal output means for outputting an operation start signal to start the operation of the column decoder upon detecting the occurrence of the signal, and a signal output in response to the operation of the word decoder in the signal output means. A semiconductor memory device provided with a transistor for shutting off a power supply path of the signal output means while the signal is inactive.