JPS61174743A - Manufacture of electrode wiring of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce electric resistance of an Si gate electrode and a wiring by forming a metal film on a whole insulating film inclusive of a semiconductor layer having a pattern formed on it and forming an alloy layer composed of the metal film and the semiconductor layer. CONSTITUTION:A pattern of a semiconductor layer 3 made of a poly-crystal Si is formed on an Si substrate 2 on which an insulating film 1 is provided. Next, an impurity diffused layer 4 is formed using the layer 3 as a mask. Next, a layer 11 is oxidized to leave layers 12 and 13. If, in this time, Mo is used as the metal and the whole is heat-treated in an oxidizing atmosphere, a metal part except the layers 12 and 13 are oxidized and the produced oxide is blown off and removed simply.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a structure having an insulating film on a semiconductor substrate, and further forming a semiconductor layer thereon to form an electrode wiring.

[Conventional technology]

Silicon gate Mo8 transistors use conductive polycrystalline silicon instead of aluminum as the gate electrode. Similar technology is also used for multilayer wiring. In particular, Mo3 LSI has a silicon gate structure [7z].

This is because silicon is stable against high-temperature heat treatment, has self-regulating properties, allows transistor dimensions to be reduced, and is suitable for LS and I.

However, there are limits to the reduction in electrical resistance of silicon used for gate electrodes and wiring, and other methods are being adopted.

For example, in Mo8 transistors, instead of forming a silicon layer, an alloy layer with a relatively high melting point metal such as Vc, Mo, W, or Ta is formed uniformly, and then the alloy layer is partially removed to form the desired pattern shape. After that, there is a method of forming the entire required bonding area.

The above method is based on the heat treatment temperature of the diffusion process for forming the bond 8 using the gold W4 layer. It also requires significant changes to conventional processes, such as patterning the alloy layer. However, there was a disadvantage in that a completely separate line from the conventional production line had to be set up.

[Problems that understanding is trying to solve]

The purpose of the present invention is to improve the electrical resistance of the silicon layer used for the gate electrode or electrode wiring in order to further improve the performance of MOS transistors and ICs with silicon gate structures.
It is an object of the present invention to provide a manufacturing method that can be reduced to a large size without changing the conventional process.

[The tth way to solve the problem]

The manufacturing method of the present invention is to completely form one alloy layer on the semiconductor J- in a semiconductor substrate having an insulating film on the surface and a semiconductor layer partially formed on the insulating film,
The method includes a step of forming a metal film on the semiconductor substrate, a step of forming an alloy layer of the metal layer and a scissor semiconductor layer, and a step of oxidizing and removing the metal group after forming the alloy layer. .

In this semiconductor substrate, a junction region is formed under an insulating film in the VI region of the MOS transistor structure by diffusion like a normal silicon gate structure. In addition, in the case of multilayer wiring, internal wiring is wired by diffusion.

[For production]

In the manufacturing method of the present invention, the conventional silicon gate structure type 1 is completely the same, and there is no particular change in the process. In the wiring stage, a metal layer is uniformly formed on the insulating film, including the patterned semiconductor layer, and then an alloy layer is formed on the semiconductor layer using the method described above. The presence of this alloy layer can significantly reduce the electrical resistance of the silicon gate electrode and wiring.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a series of longitudinal cross-sectional views showing steps for a MOS transistor structure.

In FIG. 1(,), a pattern of a semiconductor layer 3 of polycrystalline silicon is partially formed on a silicon substrate 2 having an absolute radius 1. As shown in FIG. Next, as shown in FIG. 3B, an impurity diffusion layer 4 is formed by ion implantation or the like using the entire semiconductor layer 3 as a mask material. The process up to this point is a normal process. A metal layer 11 is uniformly formed on the semiconductor substrate 10 thus formed, as shown in FIG. . The alloy layer 12 does not need to be formed on the entire semiconductor layer 3, and as shown in FIG. 3(e), two layers, the alloy layer 12 and the semiconductor layer 13, are sufficient to reduce the electrical resistance. Next, as shown in FIG. 2D, the metal layer 11 is changed into an oxide in an oxidizing atmosphere, and the oxide is selectively removed.

Parts of the alloy layer 12 and semiconductor layer 13 remain.

For example, when MOTh is used as the metal used in the above process, when heat treatment is performed at several hundred degrees Celsius or higher in an oxidizing atmosphere, the metal parts other than the alloy layer 12 and semiconductor layer 13 are oxidized, and the oxide is Easily removed by blowing away.

〔Effect of the invention〕

As described above in detail, according to the IC manufacturing method of the present invention, the electrical resistance of the silicon layer used for the gate electrode or wiring on the insulating film of the conventional MOS transistor or IC is completely reduced by forming the entire alloy layer on the silicon layer. By doing so, it is possible to reduce the value to 11i by a fraction or less. To form this alloy layer, the silicon substrate FE3 is formed by using a silicon layer.
Since this step is carried out after forming a diffusion layer, this step 1 is no different from the conventional process. It is particularly advantageous to use a metallization layer instead of a silicon layer, as opposed to requiring complete process changes.

[Brief explanation of drawings]

FIG. 1 is a longitudinal cross-sectional view of a series of steps showing an embodiment of the present invention. 1... Insulating film, 2... Silicon substrate, 3.
13... Semiconductor layer, 10... Semiconductor substrate, 1
1... Metal layer, 12... Alloy layer.

Claims (1)

[Claims] In a semiconductor substrate having an insulating film on the surface and a semiconductor layer partially formed on the insulating film, a step of forming a metal film on the semiconductor substrate, and an alloy of the metal film and the semiconductor layer. 1. A method of manufacturing an electrode wiring for a semiconductor device, comprising a step of forming a layer, and a step of oxidizing and removing the metal film after forming the alloy layer.