JPS63220544A - Superconducting semiconductor device - Google Patents
Superconducting semiconductor deviceInfo
- Publication number
- JPS63220544A JPS63220544A JP62053724A JP5372487A JPS63220544A JP S63220544 A JPS63220544 A JP S63220544A JP 62053724 A JP62053724 A JP 62053724A JP 5372487 A JP5372487 A JP 5372487A JP S63220544 A JPS63220544 A JP S63220544A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor device
- superconducting
- ceramic
- zero
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 229910010293 ceramic material Inorganic materials 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 239000002887 superconductor Substances 0.000 claims description 3
- 229910052727 yttrium Inorganic materials 0.000 claims 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 14
- 239000000463 material Substances 0.000 abstract description 13
- 239000007788 liquid Substances 0.000 abstract description 7
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 7
- 239000000919 ceramic Substances 0.000 abstract description 5
- 239000004020 conductor Substances 0.000 abstract description 5
- 238000001816 cooling Methods 0.000 abstract description 3
- 239000010409 thin film Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Electrodes Of Semiconductors (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
「発明の利用分野」
本発明はセラミック系超伝導材料を用いた半導体装置に
関するもので、半導体装置における相互配線の一部また
は全部を超伝導材料で形成するとともに、この半導体装
置を７０〜１００ °に好ましくは７７°にの如き低温
で動作せしめんとするものである。Detailed Description of the Invention "Field of Application of the Invention" The present invention relates to a semiconductor device using a ceramic superconducting material. The semiconductor device is intended to be operated at a low temperature of 70 to 100 degrees, preferably 77 degrees.
「従来の技術」
従来、超伝導材料はＮｂ−Ｇｅ系（例えばＮｂ５Ｇｅ）
等の金属材料を線材として用い、超伝導マグネットとし
て用いられるに限られていた。"Conventional technology" Conventionally, superconducting materials are Nb-Ge (for example, Nb5Ge)
The use of metal materials such as wire rods was limited to superconducting magnets.
また最近はセラミック材料で超伝導を呈し得ることが知
られていた。しかしこれもインゴット構造であり、ｇＪ
膜の超伏ｇ３−祠料の形成はまったく提案されていない
。Furthermore, it has recently been known that ceramic materials can exhibit superconductivity. However, this is also an ingot structure, and gJ
No superabrasive G3-abrasive formation of films has been proposed.
いわんや、この薄膜をフォトリソグラフィ技術によりパ
ターニングする方法も、またこれをさらに半導体装置の
相互配線の一部に用いることもまったく知られていない
。Furthermore, there is no known method for patterning this thin film using photolithography, nor is there any known method for patterning this thin film using photolithography, nor is there any known method for using this thin film as part of the interconnections of a semiconductor device.
他方、半導体集積回路を含めた複数の素子を同一基板に
設けた半導体装置が知られている。しかしこの半導体装
置を液体窒素温度（７７°Ｋ）の如き低温で動作させる
試みはまった（知られてない。On the other hand, semiconductor devices are known in which a plurality of elements including a semiconductor integrated circuit are provided on the same substrate. However, no attempt has been made to operate this semiconductor device at a low temperature such as liquid nitrogen temperature (77°K).
「従来の問題点」
半導体集積回路は近年益々微細化するとともに高速動作
を要求されている。また微細化とともに半導体素子の発
熱による信頼性低下また発熱部の動作速度の低下が問題
となっていた。"Conventional Problems" In recent years, semiconductor integrated circuits have become increasingly finer and are required to operate at higher speeds. Further, with miniaturization, problems have arisen in that reliability is lowered due to heat generated by semiconductor elements and operating speed of the heat generating portion is lowered.
このため、もし半導体素子を液体窒素温度で動作させん
とすると、その素子での電子およびホールの移動度は室
温のそれに比べて３〜４倍も高めることができ、ひいて
は素子の周波数特性を向上できる。Therefore, if a semiconductor device is operated at liquid nitrogen temperature, the mobility of electrons and holes in the device can be increased 3 to 4 times compared to that at room temperature, which in turn improves the frequency characteristics of the device. can.
また加えて液体窒素で冷却しているため、局部的な発熱
も防くことができ、信頼性向上に優れたものであると推
定できる。In addition, since it is cooled with liquid nitrogen, local heat generation can be prevented, and it can be assumed that reliability is improved.
しかし、かかる極低温で動作をさせると、その金属リー
ド配線は逆にその電気抵抗が１桁も大きくなり、このリ
ードでの周波数特性の遅滞が問題となってしまった。However, when operated at such extremely low temperatures, the electrical resistance of the metal lead wires increased by an order of magnitude, and a delay in the frequency characteristics of these leads became a problem.
「問題を解決すべき手段」
本発明はかかる問題点を解決するため、半導体装置にお
ける相互配線を極低温（２０〜１００ °に好ましくは
７７°に以上の温度）で超伝導を呈するセラミック材料
により設けたものである。"Means to Solve the Problem" In order to solve the problem, the present invention uses a ceramic material that exhibits superconductivity at extremely low temperatures (temperatures of 20 to 100 degrees, preferably 77 degrees or higher) for interconnections in semiconductor devices. It was established.
本発明は半導体特に好ましくは耐熱性を有する半導体、
例えば単結晶シリコン半導体基板を用いて、この半導体
に複数の素子、例えば絶縁ゲイト型電界効果トランジス
タ、バイポーラ型トランジスタ、５ＩＴ（静電誘導型１
〜ランシスタ）、抵抗、キャパシタを設ける。そしてこ
の上に、またその上面の絶縁膜または導体上に電気抵抗
が零または零に近（する超伝導材料を形成する。これを
フォトリソグラフィ技術により選択エッチをしてパター
ニングをする。更にその工程の前または後に５００〜１
０００°Ｃで熱アニールを特に酸化性雰囲気で行うこと
により、超伝導現象を極低温で呈するようにセラミンク
材料の結晶構造を変成する。これらの工程を１回または
複数回繰り返すことにより、１層または各層の相互配線
を電気抵抗が零の材料により形成する。The present invention relates to semiconductors, particularly preferably heat-resistant semiconductors,
For example, a single-crystal silicon semiconductor substrate may be used, and multiple elements such as insulated gate field effect transistors, bipolar transistors, 5IT (static induction type 1
~ Runsistor), resistor, and capacitor are provided. Then, a superconducting material with an electrical resistance of zero or close to zero is formed on this and on the insulating film or conductor on the upper surface. This is selectively etched and patterned using photolithography technology. Further, the process 500-1 before or after
By carrying out thermal annealing at 000°C, particularly in an oxidizing atmosphere, the crystal structure of the ceramic material is modified so that it exhibits superconductivity phenomena at extremely low temperatures. By repeating these steps one or more times, one layer or each layer of interconnections is formed from a material with zero electrical resistance.
「作用」
かかる半導体素子を液体窒素温度とすると、その電子ま
たはホール移動度は３〜４倍に向上させることができる
。加えて、そのリード、電極の電気抵抗を零または零に
等しくすることが可能となる。そのためきわめて高速動
作をさせることが可能となる。"Operation" When such a semiconductor element is brought to liquid nitrogen temperature, its electron or hole mobility can be improved by three to four times. In addition, it becomes possible to make the electrical resistance of the leads and electrodes zero or equal to zero. Therefore, extremely high speed operation is possible.
また動作による発熱も液体窒素による冷却により高信頼
性化も可能となる。Furthermore, high reliability can be achieved by cooling the heat generated by operation with liquid nitrogen.
以下に本発明の実施例を図面に従って説明する。Embodiments of the present invention will be described below with reference to the drawings.
「実施例１」
第１図は本発明の超伝導半導体装置の製造工程の実施例
を示す。"Example 1" FIG. 1 shows an example of the manufacturing process of a superconducting semiconductor device of the present invention.
第１図（Ａ）において、シリコン半導体基板（１）上に
絶縁膜（２）を形成し、ここにフォトリソグラフィ技術
により開穴（８）を形成する。In FIG. 1(A), an insulating film (2) is formed on a silicon semiconductor substrate (1), and an opening (8) is formed therein by photolithography.
第１図（Ａ）における半導体基板（１）内にはＩＧＦＥ
Ｔ（絶縁ゲイト型半導体装置）、バイポーラトランジス
タの如きアクティブ型素子または抵抗、キャパシタの如
きパッシブ型素子が予め設けられている。そしてこれら
のアクティブ型またはパッシブ型の素子の電極用コンタ
クト部が前記した開穴に対応して設けられている。There is an IGFE in the semiconductor substrate (1) in FIG. 1(A).
T (insulated gate type semiconductor device), active type elements such as bipolar transistors, or passive type elements such as resistors and capacitors are provided in advance. Contact portions for electrodes of these active or passive elements are provided corresponding to the openings described above.
第１図（Ｂ）においてはこれらの上面に超伝導を呈すべ
き材料を薄膜状に形成する。この薄膜はスパッタ法で形
成した。スクリーン印刷法、真空蒸着法または気相法（
ＣＶＤ法）で行ってもよい。しかし、ここでは材料の形
成が量産効果を有し、また耐熱性のセラミック系薄膜を
作りやすいスパッタ法が好ましい。In FIG. 1(B), a thin film of material that should exhibit superconductivity is formed on the upper surfaces of these. This thin film was formed by sputtering. Screen printing method, vacuum evaporation method or vapor phase method (
(CVD method) may also be used. However, in this case, sputtering is preferable because it has a mass-production effect in forming the material and is easy to produce a heat-resistant ceramic thin film.
スパッタ装置はターゲットとして（Ｙ ｒ −ｘＢａｘ
） Ｃｕ０ｙｘ−０，０１〜０．３好ましくは０．０５
〜０．１ 、ｙ ＝２．５〜３．０を用いた。もしｙ＝
２．５の場合はブラウンミラーライ１〜構造を採りえる
。The sputtering device uses (Y r −xBax
) Cu0yx-0.01-0.3 preferably 0.05
~0.1, y = 2.5 to 3.0 was used. If y=
In the case of 2.5, Brown Miller Lie 1~ structure can be adopted.
Ｔｃ（臨界温度）をより７７°Ｋまたはそれ以上とする
ためにはＶ ＝２．５に近く、またＸは０．０５〜０．
１にターゲツトの作製の際合成すればよい。In order to make Tc (critical temperature) more than 77°K or more, V = close to 2.5, and X is 0.05 to 0.
1, it can be synthesized when preparing the target.
スパッタに際してはその実施例として、基板温度４５０
℃、アルゴン雰囲気、周波数５ Ｑ Ｈｚ、出力１００
Ｗで行った。かかる場合のセラミック材料の膜厚を０．
２〜２μｍ、例えば１μｍの厚さとして、この後酸素中
７００°Ｃ（１０時間）でアニールを行い、その後この
薄膜がより結晶を成長させやずくすべ（Ｔｃ−４ｉ０°
Ｋ （抵抗は８０°により下がりはじめ、実験的には３
２°にで抵抗は実質的に零になった）の超伝導薄膜を作
ることができた。In sputtering, as an example, the substrate temperature is 450°C.
°C, argon atmosphere, frequency 5 Q Hz, output 100
I went by W. In such a case, the film thickness of the ceramic material is set to 0.
A thickness of 2 to 2 μm, for example 1 μm, is then annealed at 700°C (10 hours) in oxygen, after which this thin film is allowed to grow more crystals and become more stable (Tc-4i0°).
K (resistance starts to decrease at 80°, experimentally 3
We were able to create a superconducting thin film whose resistance was virtually zero at 2°.
この後、この薄膜をフォトリソグラフィ技術で所定のバ
ターニングを行った。かくして素子の電極および入力、
出力端子との接続を含む相互配線用の電極およびリード
を構成すべ（フォトレジストコートし、酸例えば硫酸ま
たは硝酸で選択除去（エッチ）を行い第１図（Ｃ）を得
た。Thereafter, this thin film was subjected to predetermined patterning using photolithography technology. Thus the element's electrodes and input,
Electrodes and leads for mutual wiring including connections with output terminals were constructed (photoresist coated and selectively removed (etched) with an acid such as sulfuric acid or nitric acid to obtain FIG. 1(C).
このバターニングは前記した超伝導用薄膜を形成した後
に行い、さらにその後に熱アニールを行ってバターニン
グした相互作用部のみ選択的に結晶化を行うことは有効
である。It is effective to carry out this patterning after forming the above-mentioned superconducting thin film, and then to perform thermal annealing to selectively crystallize only the patterned interaction areas.
この場合は相互配線を初期状態において結晶粒径が小さ
いためより微細パターンが可能である。In this case, since the crystal grain size of the interconnections is small in the initial state, a finer pattern is possible.
第１図（Ｄ）はこの後多層配線を必要に応じて行った。In FIG. 1(D), multilayer wiring was then performed as necessary.
特に半導体装置との外部のリードの接合のためにはセラ
ミ・ツク超伝導体より金属が連結をしやすい。このため
層間絶縁物（６）を酸化珪素、ＰＩＱ（ポリイミド樹脂
）で形成し、アルミニュームで（７） 、 （７”）を
形成した。In particular, metals are easier to connect than ceramic superconductors for connecting external leads to semiconductor devices. For this purpose, the interlayer insulator (6) was formed of silicon oxide and PIQ (polyimide resin), and the interlayer insulators (7) and (7'') were formed of aluminum.
即ち、本発明は素子の相互配線の１層または多層配線を
超伝導材料で形成した。さらに外部引き出電極はその密
着性をよくするため金属パッドを設けこれを用いた。も
ちろんこの外部引き出し電極との密着性を向上できる場
合はこのパッド部も超伝導材料を用いてもよい。That is, in the present invention, one layer or multiple layers of interconnections of elements are formed of a superconducting material. Furthermore, a metal pad was provided for the external lead electrode in order to improve its adhesion. Of course, this pad portion may also be made of a superconducting material if the adhesion to the external extraction electrode can be improved.
「実施例２ｊ 第２図は本発明の他の実施例を示す。“Example 2j FIG. 2 shows another embodiment of the invention.
図面はＣ／ＭＯ５（相補型Ｔ Ｇ Ｆ ＩＥ Ｔ ）の
部分のみ拡大して示したものである。The drawing shows only the C/MO5 (complementary type T G F I E T ) part enlarged.
図面は熱アニールに十分耐え得るシリコン半導体基板（
１）を用いた。さらにＰ型井戸（１５）を埋置して酸化
珪素（１１）を設け、一方のＩＧＦＥＴ（２０）はゲイ
ト電極（１２）、ソース（１３）、ドレイン（１４）を
ＰチャネルＩＧＦＥＴとして設けた。他方のＩＧＦＥＴ
（２１）はゲイト電極（１２’） 、ソース（１３’）
、ドレイン（１４’）として設け、Ｎチャネル型ＩＧ
ＦＥＴとした。ゲイト電極（１２）、 （１２’）は多
結晶シリコンとし、これらの連絡その他の相互配線（５
） 、 （７）を実施例１と同様の超伝導材料で形成し
た。The drawing shows a silicon semiconductor substrate (
1) was used. Furthermore, a P-type well (15) was buried and silicon oxide (11) was provided, and one IGFET (20) was provided with a gate electrode (12), a source (13), and a drain (14) as a P-channel IGFET. the other IGFET
(21) is the gate electrode (12') and the source (13')
, provided as a drain (14'), N-channel type IG
It was set as FET. The gate electrodes (12) and (12') are made of polycrystalline silicon, and these interconnections and other interconnections (5) are made of polycrystalline silicon.
) and (7) were formed using the same superconducting material as in Example 1.
この超伝導材料を気相法で作り、下側基板に対し何らの
損傷を与えない場合はゲイト電極も超伝導材料で形成し
てもよい。If this superconducting material is produced by a vapor phase method and no damage is caused to the lower substrate, the gate electrode may also be formed of the superconducting material.
「効果」
本発明によりこれらを半導体装置を室温ではなく、冷却
して形成する場合においても実用化が初めて可能となっ
た。"Effects" According to the present invention, it has become possible for the first time to put these into practical use even when semiconductor devices are formed not at room temperature but after being cooled.
特に半導体は冷却することにより周波数特性を向上させ
ることができる。しかし他方金属導体は逆に抵抗が増し
てしまう。ごの欠点を除去し導体をセラミック系超伝導
材料を用いることにより半導体とともに低温にし、電気
伝導度を向上させることが可能となった。In particular, the frequency characteristics of semiconductors can be improved by cooling them. However, metal conductors, on the other hand, have an increased resistance. By eliminating the drawbacks of this and using a ceramic superconducting material for the conductor, it has become possible to lower the temperature together with the semiconductor and improve electrical conductivity.
そのため、本発明の技術思想を発展させることにより、
１６Ｍ〜ＩＧビット等の超々ＬＳＩに対する応用も可能
となった。Therefore, by developing the technical idea of the present invention,
Application to ultra-super LSIs such as 16M to IG bits has become possible.
本発明において、半導体はシリコンではな（ＧａＡｓ等
の化合物半導体であってもよい。またシリコン半導体上
にＧａＡｓ等の■−Ｖ化合物半導体をヘテロエピタキシ
ャル成長をせしめ、この半導体薄膜を用いてもよい。か
くすることにより超高速動作を指せることが可能となる
。しかしアニールの温度を下げ、アニール中に半導体基
板を劣化しないように工夫する必要がある。In the present invention, the semiconductor is not silicon (it may also be a compound semiconductor such as GaAs).Also, it is also possible to grow a -V compound semiconductor such as GaAs on a silicon semiconductor by heteroepitaxial growth and use this semiconductor thin film. This makes it possible to achieve ultra-high-speed operation. However, it is necessary to lower the annealing temperature and take measures to prevent deterioration of the semiconductor substrate during annealing.
第１図は本発明の製造工程を示す。 第２図は本発明の他の実施例を示す。 FIG. 1 shows the manufacturing process of the present invention. FIG. 2 shows another embodiment of the invention.
Claims (1)
前記半導体素子間または前記半導体素子と外部電気信号
の入力および出力端子との電気的連結を超伝導体を用い
て連結することを特徴とする超伝導半導体装置。 ２、特許請求の範囲第１項において、超伝導体はセラミ
ック材料よりなることを特徴とする超伝導半導体装置。 ３、特許請求の範囲第１項において、半導体基板はシリ
コン単結晶半導体よりなることを特徴とする超伝導半導
体装置。 ４、特許請求の範囲第１項において、半導体基板におけ
る複数の半導体素子の設けられた領域はIII―Ｖ化合物
半導体よりなることを特徴とする超伝導半導体装置。 ５、特許請求の範囲第２項において、セラミック材料は
イットリュームを含むことを特徴とする超伝導半導体装
置。[Claims] 1. A plurality of semiconductor elements are provided in a semiconductor substrate, and
A superconducting semiconductor device characterized in that electrical connections between the semiconductor elements or between the semiconductor elements and input and output terminals for external electrical signals are made using a superconductor. 2. A superconducting semiconductor device according to claim 1, wherein the superconductor is made of a ceramic material. 3. A superconducting semiconductor device according to claim 1, wherein the semiconductor substrate is made of a silicon single crystal semiconductor. 4. The superconducting semiconductor device according to claim 1, wherein the region of the semiconductor substrate where the plurality of semiconductor elements are provided is made of a III-V compound semiconductor. 5. The superconducting semiconductor device according to claim 2, wherein the ceramic material contains yttrium.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62053724A JPS63220544A (en) | 1987-03-09 | 1987-03-09 | Superconducting semiconductor device |
| EP88103643A EP0282012A3 (en) | 1987-03-09 | 1988-03-08 | Superconducting semiconductor device |
| KR1019880002376A KR950010206B1 (en) | 1987-03-09 | 1988-03-08 | Electronic device and manufacturing method thereof |
| CN88101268A CN1017951B (en) | 1987-03-09 | 1988-03-09 | Superconductive semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62053724A JPS63220544A (en) | 1987-03-09 | 1987-03-09 | Superconducting semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63220544A true JPS63220544A (en) | 1988-09-13 |
Family
ID=12950780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62053724A Pending JPS63220544A (en) | 1987-03-09 | 1987-03-09 | Superconducting semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63220544A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63244880A (en) * | 1987-03-31 | 1988-10-12 | Sumitomo Electric Ind Ltd | Extra-high speed semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57126182A (en) * | 1981-01-28 | 1982-08-05 | Nippon Telegr & Teleph Corp <Ntt> | Superconductor element |
| JPS60154613A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Semiconductor device for ultra-low temperature |
-
1987
- 1987-03-09 JP JP62053724A patent/JPS63220544A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57126182A (en) * | 1981-01-28 | 1982-08-05 | Nippon Telegr & Teleph Corp <Ntt> | Superconductor element |
| JPS60154613A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Semiconductor device for ultra-low temperature |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63244880A (en) * | 1987-03-31 | 1988-10-12 | Sumitomo Electric Ind Ltd | Extra-high speed semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0199242A (en) | Semiconductor device having mutual connection of superconductor | |
| JPH0456325A (en) | Manufacture of semiconductor device | |
| KR950010206B1 (en) | Electronic device and manufacturing method thereof | |
| US5212150A (en) | Oxide superconducting lead for interconnecting device component with a semiconductor substrate via at least one buffer layer | |
| JPS63220544A (en) | Superconducting semiconductor device | |
| JP3096050B2 (en) | Method for manufacturing semiconductor device | |
| JPS63220545A (en) | Manufacture of superconducting semiconductor device | |
| JPS63220546A (en) | Manufacture of superconducting device | |
| JPS63245975A (en) | Superconductor device | |
| JPS6047478A (en) | Josephson junction element | |
| US5227361A (en) | Oxide superconducting lead for interconnecting device component with a semiconductor substrate via at least one buffer layer | |
| JP2678232B2 (en) | Superconductor device | |
| JP2747557B2 (en) | Superconductor device | |
| JPH01101676A (en) | Superconducting transistor | |
| JPH01125957A (en) | Superconductor device | |
| JPS6211781B2 (en) | ||
| JPH0736404B2 (en) | Method for manufacturing superconductor device | |
| JP2614942B2 (en) | Superconducting integrated circuit device manufacturing method | |
| JP2691065B2 (en) | Superconducting element and fabrication method | |
| JPS63250882A (en) | Insulating method for superconducting material | |
| JP2597745B2 (en) | Superconducting element and fabrication method | |
| JPS61174743A (en) | Manufacture of electrode wiring of semiconductor device | |
| JPH01125958A (en) | Superconductor device | |
| JPH04326521A (en) | Semiconductor integrated circuit device and its manufacture | |
| JP2647251B2 (en) | Superconducting element and fabrication method |