JPS5921067A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS5921067A JPS5921067A JP13140782A JP13140782A JPS5921067A JP S5921067 A JPS5921067 A JP S5921067A JP 13140782 A JP13140782 A JP 13140782A JP 13140782 A JP13140782 A JP 13140782A JP S5921067 A JPS5921067 A JP S5921067A
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- insulating film
- gate electrode
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 239000013078 crystal Substances 0.000 claims abstract description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 9
- 239000011574 phosphorus Substances 0.000 claims abstract description 9
- 239000005368 silicate glass Substances 0.000 claims description 6
- 238000005224 laser annealing Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000002689 soil Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 6
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 229910052786 argon Inorganic materials 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 230000002040 relaxant effect Effects 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 101100081489 Drosophila melanogaster Obp83a gene Proteins 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- XOFYZVNMUHMLCC-ZPOLXVRWSA-N prednisone Chemical group O=C1C=C[C@]2(C)[C@H]3C(=O)C[C@](C)([C@@](CC4)(O)C(=O)CO)[C@@H]4[C@@H]3CCC2=C1 XOFYZVNMUHMLCC-ZPOLXVRWSA-N 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置とその製造方法、特にＭＯＳ Ｆ
ＥＴ（ＭＯ８電界効果トランジヌタ）の新規な構造とそ
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention The present invention relates to a semiconductor device and a method for manufacturing the same, particularly a MOS F
This invention relates to a novel structure of ET (MO8 field effect transistor) and its manufacturing method.
（旬 従来技術と問題点
周知のよ’５にＭＯＳ Ｆ’ＥＴｉｄ、ＬＳＩ、ＶＬ
ＳＩと高密度高集積化される半導体集積回路（工Ｃ）に
おいて主体となっているトランジスタ素子である。それ
はバイポーラ形素子などと比べて構造がｗＩ牢で、セル
フアブイン（自己整合）で製造が可能なため餓細化でき
ることが大きな利点となっている。(The conventional technology and problems are well known in 2005. MOS F'ETid, LSI, VL
It is a transistor element that is the main component in SI and semiconductor integrated circuits (engineering C), which are becoming increasingly dense and highly integrated. Compared to bipolar elements, etc., it has a WI structure and can be manufactured by self-abin (self-alignment), so it has the great advantage of being able to be made thinner.
第１図（ａ＋にコノような通常ｔｙ） Ｍ ＯＳ Ｆ
” Ｉ！ｆ Ｔ ４ｇ造断面をボしており、セルファラ
インとは半導体基板Ｉ Ｊ二にゲート絶縁膜２．ゲート
電極３を形成し、これケマスクとしてソー゛ヌ領域４と
ドレイン領域５とが形成されることを意味しており、こ
れは小ノｔＬ！化に極めて効果的な製法である。寸だ、
第１図（ｂ）にザファイヤ基板６七に形成した絶縁体分
離構造のＭＯＳ ＦＴＢＴ構造断面を示しており、こ
れも同様にセルファライン方式で形成することができる
。Figure 1 (Normal ty like Kono on a+) M OS F
"I!f T 4G fabrication cross section is exposed, and self-line is a process in which a gate insulating film 2 and a gate electrode 3 are formed on a semiconductor substrate IJ2, and a solenoid region 4 and a drain region 5 are formed as a mask. This means that it is formed, and this is an extremely effective manufacturing method for making it small.
FIG. 1(b) shows a cross section of a MOS FTBT structure having an insulator isolation structure formed on a Zaphire substrate 67, which can also be formed by the self-line method in the same manner.
ところが、このようなＭＯＳ ＦＥＴを余り小型に形
成すると、例えばゲート長りを１〜２μｍ又はそれ以下
とすると、短チャネ／ｌ／（ショートチャネル
（ Ｖｔｈ ）の変！ｌｔ／１などの好ましからざる問
題がおこることが知られており、その面からの制約が大
きな障害となっている。However, if such a MOS FET is made too small, for example, if the gate length is set to 1 to 2 μm or less, undesirable problems such as short channel /l/(short channel (Vth) change!lt/1) may occur. It is known that this phenomenon occurs, and restrictions in this respect are a major obstacle.
（Ｃ）＠明の目的
本発明はかような短チャネル効果が緩和され、且つセル
ファライン方式で製造される絶縁体分離構造の新規なＭ
Ｏ ＥＥ １１’ ］、ｕ Ｔを提供するものであ
る。(C)@Ming's purpose The present invention is a novel M with an insulator isolation structure in which such short channel effects are alleviated and which is manufactured by a self-line method.
O EE 11'], u T.
（ｄ）発明の構成
本発明の特徴は、絶縁膜上にゲー［電極，その表面にゲ
ート絶縁膜が設けられ、そのゲート電極の、１一部にゲ
ート絶縁膜を介して−４電型チャネル領域が設けられ、
且つゲート屯瘤の両側に絶縁膜を介１〜で反えｊ４’Ｕ
Ｆ゛νのソース・ドレイン両領域が設けられた半導体装
置であり、徒だその製造方法として、ソーヌ響ドレイン
両領域全セルファライン方式で形成することにあるもの
である。(d) Structure of the Invention The feature of the present invention is that a gate electrode is provided on the insulating film, a gate insulating film is provided on the surface of the gate electrode, and a -4 voltage type channel is formed in one part of the gate electrode through the gate insulating film. An area is set up,
In addition, an insulating film is provided on both sides of the gate bulge at 1~j4'U.
This is a semiconductor device in which both the source and drain regions of F゛ν are provided, and its manufacturing method consists in forming both the Saone sound drain and both regions using an all-self-line method.
ｔｅ＋ 発明の実施例
以下、本発明を図面を参照して一実施例によって詳細に
説明する。第２図は本発明にか−るＭＯＳ ＦＦＡＴ
の断面構造図を示し、図示のように絶縁板ｌＯ上の燐シ
リケートガラス（ＰＳＧ）膜１１の−に面に多結晶シリ
コンからなるゲート電極１２を形成し、その外部表面に
二酸化シリコンＱ’Ｅｊ−０２）膜からなるゲート絶縁
膜ＩＢを形成し、このゲート絶縁膜１８上にＰ型チＡ１
ネル領域１４，またゲート絶縁膜１Ｂの両側面にｎ型ソ
ーヌ領域１５およびトレイン領域１６が設けられた構造
で、従来のＭＯＳ Ｆ”）ｕＴとは■下逆のゲート電
極が最下面に形成された構造である。このような構造に
すると、絶縁体分離のため、寄生容量が小さくなる長所
があると共に、チャネル領域に対してソース・ドレイン
両領域を浅く接合することができるから、短チャネル効
果が緩和される利点がある。且つ、セルファライン方式
によってソース・ドレイン両領域を形成して、高密度化
ができる製造方法を採ることができる。尚、図中、１７
は第２のＳｉＯ２ 膜、１８はＰＳＧ膜、１９はアル
ミニウム（Ａｌ）電極である。te+ Embodiment of the Invention The present invention will now be described in detail by way of an embodiment with reference to the drawings. Figure 2 shows a MOS FFAT according to the present invention.
As shown in the figure, a gate electrode 12 made of polycrystalline silicon is formed on the negative side of a phosphorus silicate glass (PSG) film 11 on an insulating plate lO, and silicon dioxide Q'Ej is formed on the outer surface of the gate electrode 12. -02) A gate insulating film IB consisting of a film is formed, and a P-type film A1 is formed on this gate insulating film 18.
It has a structure in which an n-type Sone region 15 and a train region 16 are provided on both sides of the channel region 14 and the gate insulating film 1B, and unlike the conventional MOS F'') uT, the gate electrode is formed on the bottom surface. This structure has the advantage of reducing parasitic capacitance due to insulator isolation, and also reduces the short channel effect because both the source and drain regions can be shallowly connected to the channel region. This has the advantage of alleviating the problem.Furthermore, it is possible to form both the source and drain regions using the self-line method and adopt a manufacturing method that can achieve high density.
18 is a PSG film, and 19 is an aluminum (Al) electrode.
次に、第８図ないし第７図は本発明にか＼る半導体装置
の製造工程順断面図を示す。先づ、第８図に示すように
絶縁板１０１，に化学気相成長（ＣＶＤ）法で厚さ１〜
２μｍのＰＳＧ膜１１を被着し、その上面に同じ（ Ｃ
ＶＤ法で膜厚０．４μｍの多結晶シリコン膜を被着し、
リソグラフィ技術によつしだ後、熱酸化処理によって膜
厚４００ ＡのＳｉＯ２膜１Ｂ全１Ｂする。このＳｉ．
０ ２膜１Ｂがゲート絶縁膜である。−また、旧制の基
板は絶縁板ｌＯに限るものでなく、シリコン基板などで
もよい。Next, FIGS. 8 to 7 show cross-sectional views in the order of manufacturing steps of a semiconductor device according to the present invention. First, as shown in FIG.
A 2 μm thick PSG film 11 is deposited, and the same (C
A polycrystalline silicon film with a thickness of 0.4 μm was deposited using the VD method,
After applying the lithography technique, a thermal oxidation treatment is performed to form a SiO2 film 1B with a thickness of 400 Å. This Si.
02 film 1B is a gate insulating film. -Also, the old system substrate is not limited to the insulating plate IO, but may also be a silicon substrate or the like.
次いで、第４図に示すようにその上面にＣＶＤ法にて再
び膜厚０，４μ〃ｊの第２の多結晶シリコン膜２０を被
着し、リソグラフィ技術によってパターンニングし，更
に熱酸化処理によってその表面に膜厚８８０人の第２の
ＳｉＯＩｊＩＩ！ｔｉ［ １ ７を生成する。Next, as shown in FIG. 4, a second polycrystalline silicon film 20 with a thickness of 0.4 μm is deposited on the top surface again by CVD, patterned by lithography, and then thermally oxidized. The second SiOIjII with a film thickness of 880 people on its surface! Generate ti[ 1 7.
次いで、第６図に示すようにアルゴンレーザヲ照ＪＩ＝
Ｉ’ してレーザアニールによって第２の多結晶シリコ
ン膜２０をシリコン結晶膜２０にしだ後、更に加速電圧
１４０ＫｅＶにて硼素をイオン注入して、濃度Ｉ Ｘ
Ｉ Ｏ１６／ａｌ のＰ型−にする。この場合、第２の
Ｓｉ０８膜１７の膜厚はアルゴンレーザの吸収がよくな
るよう考慮して，’／４（λ； ＳｉＯ，、中のレーザ
波長）の厚さ即ち８８０Ａとする方法が望ましい。Next, as shown in FIG. 6, the argon laser is illuminated.
After I', the second polycrystalline silicon film 20 is turned into a silicon crystal film 20 by laser annealing, and then boron ions are implanted at an acceleration voltage of 140 KeV to increase the concentration I
Make it P-type of I O16/al. In this case, the thickness of the second Si08 film 17 is desirably set to a thickness of '/4 (λ; laser wavelength in SiO, .), that is, 880A, in order to improve absorption of the argon laser.
次いで、第６図に示すようにＳｊ−ＯＩｌｌ膜１７に２
の第２のＰＳＧ膜１８を全面に被着する。この２つの窓
はソースおよびドレインの奄蕩コンタクト部となるもの
である。次いで、第７図に不すように窒素ガス気流中に
て１０５０′Ｃ，１５分間熱処理して、」ユ下のＰＳＧ
膜１１，１８より燐をＰ型シリコン結晶膜２０に拡散し
、ｎａのソース領域１５およびドレイン領＠１６を形成
する。住つ、Ｐ型シリコン結晶膜２０はチャネル領域１
４と７ｚる。Next, as shown in FIG.
A second PSG film 18 is deposited over the entire surface. These two windows serve as source and drain contact areas. Next, as shown in Fig. 7, heat treatment was performed at 1050'C for 15 minutes in a nitrogen gas flow to obtain the PSG under the
Phosphorus is diffused into the P-type silicon crystal film 20 from the films 11 and 18 to form a source region 15 and a drain region @16 of na. The P-type silicon crystal film 20 is located in the channel region 1.
4 and 7zru.
この場合、ゲーｉ・電極１２にも燐は拡散されて、これ
らのｎ型濃度はｌ Ｘ １．０”／ｃｙｘａ 程度とな
る。このようにすればＰ型シリコン結晶とこれらのｎ型
領域との接合は浅く形成される。以降は、ＰＳＧ膜１８
を窓あけして、Ａββ他極１９形成し、第２図に示すＭ
ＯＳ Ｆｌｉ：Ｔが完成される。In this case, phosphorus is also diffused into the gate i-electrode 12, and the n-type concentration therein becomes approximately l x 1.0"/cyxa. In this way, the p-type silicon crystal and these n-type regions are The junction of the PSG film 18 is formed shallowly.
A window is opened to form the Aββ other pole 19, and the M shown in FIG.
OS Fli:T is completed.
（ｆ）＠明の効果
以上が一実施例の説明であるが、このように本発明によ
る半導体装置は浅い接合をもったソース・ドレインが設
けられた構造となるためアバランシェがおこりにくくて
、短チヤネル効果が緩和され、■シｈなどが安定する。(f) Effects of @Akira The above is an explanation of one embodiment, but since the semiconductor device according to the present invention has a structure in which the source and drain are provided with shallow junctions, avalanche is difficult to occur and short The channel effect is alleviated, and ■shih etc. are stabilized.
しかも、上下のＰＳＧ膜からソース・ドレイン両領域が
セルファラインで形成されるため小型化しやすくて、集
積度の向上に極めて好適な構造である。Moreover, since both the source and drain regions are formed by self-line from the upper and lower PSG films, miniaturization is easy and the structure is extremely suitable for improving the degree of integration.
尚、ＰＳＧ膜の代りに硼素シリケートガラス（ＰＳＧ
）膜を用いれば、Ｐチャネ／ｌ／ｌφＯ８Ｅ”Ｅ１゛を
も形成できることはざう１でもない。Note that boron silicate glass (PSG) is used instead of the PSG film.
) film, it is very possible to form a P channel/l/lφO8E"E1".
第１図（ａｌおよび（′ｂ）は従来の半導体装置の断面
構造図、第２図は本発明にか象る半導体装置の断面構造
図、第８図ないし第７図は本発明にか−る製造方法の工
程順断面図である。
図中、ｌは半導体基板、２．１８はゲート絶縁膜、Ｂ、
１．２はゲート１凱４．１５はソース領域、５．１６は
ドレイン領域、６．１０は絶縁板（サファイヤ基板）、
１１はＰＳＧ膜、１４はチャネル領域、１７は第２のＳ
ｉＯ、膜、１８は第２０ＰＳＧ＃、１９はアルミニウム
電極、２０は第２の多結晶シリコン膜、２０はシリコン
結晶膜を示す。
リ ＤFIG. 1 (al and 'b) is a cross-sectional structural diagram of a conventional semiconductor device, FIG. 2 is a cross-sectional structural diagram of a semiconductor device according to the present invention, and FIGS. 8 to 7 are cross-sectional structural diagrams of a conventional semiconductor device. 1 is a step-by-step cross-sectional view of a manufacturing method. In the figure, l is a semiconductor substrate, 2.18 is a gate insulating film, B,
1.2 is the gate 1, 4.15 is the source region, 5.16 is the drain region, 6.10 is the insulating plate (sapphire substrate),
11 is a PSG film, 14 is a channel region, and 17 is a second S
18 is the 20th PSG#, 19 is the aluminum electrode, 20 is the second polycrystalline silicon film, and 20 is the silicon crystal film. Ri D
Claims (2)
縁膜が設けられ、該ゲート電極の上部にゲート絶縁膜を
介して−４電型チャネル領域が設けられ、且つ該ゲート
電極の両側に絶縁膜を介して反対４紙型のソース領域お
よびトレイン領域が設けられてなることを特徴とする半
導体装置。(1) A gate electrode is provided on the insulating film, a gate insulating film is provided on the surface of the gate electrode, a -4 voltage type channel region is provided above the gate electrode via the gate insulating film, and a -4 voltage type channel region is provided on both sides of the gate electrode. A semiconductor device characterized in that a source region and a train region are provided in an opposite four-paper shape with an insulating film interposed therebetween.
着し、パターンニングした後、該多結晶シリコン膜の外
表面を酸化してゲート絶縁膜とする工程１次いでその上
面に第２の多結晶シリコン膜を被着し、これをパターン
ニングした後、該第２の多結晶シリコン膜の外表面を酸
化して、第２の絶縁膜を形成する工程１次いで該第２の
絶縁膜上からレーザアニールをおこなっテ、上記第２の
多結晶シリコン膜を単結晶化し、更にその上面からアク
セプタ不純物を導入してＰｉ領領域する工程１次いでゲ
ート電極の両側の第２の絶縁膜に所望の窓を形成した後
、その上面に第２の燐ンリケートガラス膜ｋｍ着し熱処
理して、ゲート電極両１１１１１の単結晶領域に土面お
よび下面の燐シリケートガラス膜から燐を熱拡散させて
ｎ型結晶領域とする工程が含まれてなることを特徴とす
る半導体装置の製造方法。(2) After depositing and patterning a polycrystalline silicon film on the phosphorus silicate glass film, the outer surface of the polycrystalline silicon film is oxidized to form a gate insulating film. Step 1 of depositing a crystalline silicon film and patterning it, and then oxidizing the outer surface of the second polycrystalline silicon film to form a second insulating film. Laser annealing is performed to make the second polycrystalline silicon film into a single crystal, and acceptor impurities are introduced from the top surface of the second polycrystalline silicon film to create a Pi region. Step 1: Next, desired windows are formed in the second insulating film on both sides of the gate electrode. After forming a second phosphorus silicate glass film, a second phosphorus silicate glass film is deposited on the top surface and heat treated to thermally diffuse phosphorus from the phosphorus silicate glass film on the soil surface and the bottom surface into the single crystal region of both gate electrodes 11111, thereby forming an n-type A method of manufacturing a semiconductor device, comprising a step of forming a crystal region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13140782A JPS5921067A (en) | 1982-07-27 | 1982-07-27 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13140782A JPS5921067A (en) | 1982-07-27 | 1982-07-27 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5921067A true JPS5921067A (en) | 1984-02-02 |
Family
ID=15057246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13140782A Pending JPS5921067A (en) | 1982-07-27 | 1982-07-27 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5921067A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521794A (en) * | 1991-02-04 | 1993-01-29 | Semiconductor Energy Lab Co Ltd | Dieleciric gate type field effect semiconductor device and fabrication thereof |
| JPH05160153A (en) * | 1991-12-03 | 1993-06-25 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
| JPH05267667A (en) * | 1991-08-23 | 1993-10-15 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| JPH05283694A (en) * | 1991-08-23 | 1993-10-29 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacture thereof |
| JPH0653509A (en) * | 1991-05-11 | 1994-02-25 | Semiconductor Energy Lab Co Ltd | Insulated gate field effect semiconductor device and fabrication thereof |
| JPH06196500A (en) * | 1991-05-16 | 1994-07-15 | Semiconductor Energy Lab Co Ltd | Insulated gate field effect semiconductor device and manufacture thereof |
| JPH06244200A (en) * | 1991-03-06 | 1994-09-02 | Semiconductor Energy Lab Co Ltd | Insulating gate type field effect semiconductor device and its manufacture |
| JPH08248445A (en) * | 1995-12-22 | 1996-09-27 | Semiconductor Energy Lab Co Ltd | Insulated gate type field effect semiconductor device |
| US5681760A (en) * | 1995-01-03 | 1997-10-28 | Goldstar Electron Co., Ltd. | Method for manufacturing thin film transistor |
| US5962870A (en) * | 1991-08-26 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect semiconductor devices |
| US6013928A (en) * | 1991-08-23 | 2000-01-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having interlayer insulating film and method for forming the same |
| US6130120A (en) * | 1995-01-03 | 2000-10-10 | Goldstar Electron Co., Ltd. | Method and structure for crystallizing a film |
| US6147375A (en) * | 1992-02-05 | 2000-11-14 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device |
| US6624450B1 (en) | 1992-03-27 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126971A (en) * | 1980-03-10 | 1981-10-05 | Fujitsu Ltd | Thin film field effect element |
| JPS57128957A (en) * | 1981-02-04 | 1982-08-10 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
-
1982
- 1982-07-27 JP JP13140782A patent/JPS5921067A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126971A (en) * | 1980-03-10 | 1981-10-05 | Fujitsu Ltd | Thin film field effect element |
| JPS57128957A (en) * | 1981-02-04 | 1982-08-10 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521794A (en) * | 1991-02-04 | 1993-01-29 | Semiconductor Energy Lab Co Ltd | Dieleciric gate type field effect semiconductor device and fabrication thereof |
| JPH06244200A (en) * | 1991-03-06 | 1994-09-02 | Semiconductor Energy Lab Co Ltd | Insulating gate type field effect semiconductor device and its manufacture |
| JPH0653509A (en) * | 1991-05-11 | 1994-02-25 | Semiconductor Energy Lab Co Ltd | Insulated gate field effect semiconductor device and fabrication thereof |
| US6555843B1 (en) | 1991-05-16 | 2003-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6017783A (en) * | 1991-05-16 | 2000-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device using an insulated gate electrode as a mask |
| JPH06196500A (en) * | 1991-05-16 | 1994-07-15 | Semiconductor Energy Lab Co Ltd | Insulated gate field effect semiconductor device and manufacture thereof |
| US6013928A (en) * | 1991-08-23 | 2000-01-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having interlayer insulating film and method for forming the same |
| JPH05283694A (en) * | 1991-08-23 | 1993-10-29 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacture thereof |
| JPH05267667A (en) * | 1991-08-23 | 1993-10-15 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| US6331723B1 (en) | 1991-08-26 | 2001-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device having at least two transistors having LDD region in one pixel |
| US7821011B2 (en) | 1991-08-26 | 2010-10-26 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect semiconductor devices and method of manufacturing the same |
| US5962870A (en) * | 1991-08-26 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect semiconductor devices |
| US6803600B2 (en) | 1991-08-26 | 2004-10-12 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect semiconductor devices and method of manufacturing the same |
| JPH05160153A (en) * | 1991-12-03 | 1993-06-25 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
| US6147375A (en) * | 1992-02-05 | 2000-11-14 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device |
| US6476447B1 (en) | 1992-02-05 | 2002-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device including a transistor |
| US6624450B1 (en) | 1992-03-27 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6610998B1 (en) | 1995-01-03 | 2003-08-26 | Goldstar Electron Co., Ltd. | Method and structure for crystallizing a film |
| US6130120A (en) * | 1995-01-03 | 2000-10-10 | Goldstar Electron Co., Ltd. | Method and structure for crystallizing a film |
| US5681760A (en) * | 1995-01-03 | 1997-10-28 | Goldstar Electron Co., Ltd. | Method for manufacturing thin film transistor |
| JPH08248445A (en) * | 1995-12-22 | 1996-09-27 | Semiconductor Energy Lab Co Ltd | Insulated gate type field effect semiconductor device |
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