JPH06275839A - Manufacture of vertical semiconductor element - Google Patents

Abstract

PURPOSE:To reduce the area of a transistor and to achieve a high integration by forming a source layer, a gate layer, and a drain layer with epitaxial growth at an opening part formed by partially eliminating a first insulation layer, a gate electrode, and a second insulation layer. CONSTITUTION:Silicon oxide film 16, polysilicon layer 15, and silicon oxide film 14 are removed from any area, P<+> epitaxial layer 13 is exposed for forming an opening part 17, and an insulation layer 18 used as a gate oxide film and an insulation layer 19 consisting of silicon oxide film are formed on the side surface of the opening part 17. Then, only the insulation layer 19 exposed on the bottom surface of the opening part 17 is removed and is allowed to grow to a position matching the lower part of the insulation layer 18 while adding B to the P<+> epitaxial layer 13. Then, an N<+>-type epitaxial layer 20 is formed to a position matching the upper part of the insulation layer 18 of an N<+> type epitaxial layer 20 while adding B and then a P<+> type epitaxial layer 21 is allowed to grow to the surface of the silicon oxide film 16 while adding P, thus reducing the area of a transistor and achieving a high integration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a vertical semiconductor device, particularly a vertical MOSFET.

[0002]

2. Description of the Related Art A conventional method of manufacturing a lateral MOSFET is shown below. First, as shown in FIG.
An N-type well diffusion layer 202 and a P-type well diffusion layer 203 are formed thereon, and a thick field oxide film 204 is selectively grown only in an element isolation region by using, for example, the LOCOS method or the like to perform element isolation. . Next, as shown in FIG.
A gate oxide film and a gate electrode 205 are formed by photolithography and etching techniques to complete the gate,
Further, the source and drain are completed by forming the N ⁺ diffusion layer 206 and the P ⁺ diffusion layer 207 by ion implantation. Next, as shown in FIG. 10, an insulating layer 208 is formed on the entire surface. Next, as shown in FIG. 11, the wiring 209 is formed.

However, since the conventional photolithography technique for forming the gate of the MOSFET uses the i-line, the limit is 0.2 μm in the gate length.
Since the ET is laterally formed on the LSI, it is difficult to achieve high integration unless the gate length can be reduced. Therefore, it has been considered to form the MOSFET vertically. For example, JP-A-2-54539 and JP-A-2-1003.
The manufacturing method described in Japanese Patent Publication No. 70 is known as a method for manufacturing a vertical MOSFET.

[0004]

However, in the method of manufacturing the vertical MOSFET transistor in which the gate is formed by using the conventional photolithography and etching techniques, the channel region is formed obliquely and the vertical type is not formed. There is a problem that the area of the MOSFET transistor cannot be made smaller than a certain value.

Therefore, it is an object of the present invention to provide a method of manufacturing a vertical MOSFET capable of reducing the area of a transistor.

[0006]

According to the present invention, there is provided a method of manufacturing a vertical semiconductor device having a vertical MOSFET structure, wherein a source is formed in a region on a semiconductor substrate where the device is to be formed. Forming an epitaxial layer, a step of forming a first insulating layer on the epitaxial layer, a step of forming a gate electrode layer on the first insulating layer, and a second step on the gate electrode layer. Forming an insulating layer, forming a opening by partially removing the first insulating layer, the gate electrode layer, and the second insulating layer in the region, and forming a side wall of the opening. A process of forming a gate insulating film, a process of forming a source layer, a gate layer, and a drain layer in the opening by epitaxial growth, and a process for exposing the gate electrode layer and the epitaxial layer serving as a source. A process of removing the first and second insulating layers by a lithography technique and an etching technique, a process of forming a conductive type material to be a source electrode, a gate electrode and a drain electrode on the surface of the region, and photolithography of each electrode. And a step of forming using an etching technique, the present invention provides a method for manufacturing a vertical semiconductor device.

Further, the gate insulating film may be a film obtained by oxidizing the gate electrode layer by heat treatment, or the gate insulating film may be a silicon nitride film. Further, the source layer and the drain layer may be P ⁺ type diffusion layers, and the gate layer may be an N ⁺ type diffusion layer, or alternatively, the source layer and the drain layer may be N ⁺ type diffusion layers. And the gate layer may be a P ⁺ type diffusion layer.

[0008]

According to the above method of manufacturing the vertical MOSFET,
Since photolithography and etching techniques are not used to form the gate, the gate can be miniaturized.
Since the MOSFET has a completely vertical structure, the area of the transistor can be reduced and high integration can be achieved.

[0009]

Embodiments of the present invention will be described below with reference to FIGS.

First, as shown in FIG. 1, unevenness is selectively formed on a P-type silicon substrate 11 by photolithography and etching techniques, and an insulating material such as a silicon oxide film is formed on the entire surface of the substrate 11 to have a thickness of 100 nm, for example. After the deposition, the insulator formed in the concave portion of the substrate 11 is left, and the insulator formed in the convex portion is removed to form the silicon oxide layers 12a and 12b as the separated insulating layers.

Next, as shown in FIG. 2, for example, while selectively adding P to the entire exposed surface of the P-type silicon substrate 11, the P ⁺ -type epitaxial layer 13 may be formed into, for example, 1 layer.
After the growth of 00 nm, the source extraction layer is formed by partially removing the epitaxial layer 13 by, for example, 50 nm by photolithography and etching techniques, and further, the entire surface of the P ⁺ type epitaxial layer 13 and the silicon oxide layers 12a and 12b. For example, a silicon oxide film 14 is formed on the entire surface of
Is deposited to a thickness of 100 nm, for example.

Next, as shown in FIG. 3, after removing an arbitrary region of the silicon oxide film 14 by, for example, 50 nm by a photolithography technique, a polysilicon layer 15 to be a gate electrode is formed on the entire surface of the silicon oxide film 14, for example. 20nm formation,
Further, an insulator 16 made of, for example, a silicon oxide film is deposited on the entire surface of the polysilicon layer 15 by 100 nm, for example.

Next, as shown in FIG. 4, a silicon oxide film 16, a polysilicon layer 15 and a silicon oxide film 14 in arbitrary regions are formed.
Are removed by photolithography and etching techniques to expose the P ⁺ epitaxial layer 13 and an opening 17 is formed.

Next, as shown in FIG. 5, the polysilicon layer 1 to be the gate electrode exposed on the side surface of the opening 17 is formed.
5 and the P ⁺ epitaxial layer 13 exposed on the bottom surface of the opening 17 respectively, the insulating layer 18 as a gate oxide film and the insulating layer 19 made of a silicon oxide film by, for example, a thermal oxidation method.
To form.

Next, as shown in FIG. 6, only the insulating layer 19 made of a silicon oxide film exposed on the bottom surface of the opening 17 is removed by anisotropic etching, so that the P ⁺ epitaxial layer 13 is opened again. is exposed at the bottom of 17, further with the addition of the P ⁺ epitaxial layer 13, for example a P simultaneously grown to a position which coincides with the lower portion of the insulating layer 18 as a gate oxide film, then grown P ⁺ epitaxial For example, while simultaneously adding B to the layer 13, N
^{The +} type epitaxial layer 20 is formed up to a position corresponding to the upper portion of the insulating layer 18, for example, 20 nm, and further, P is added simultaneously to the formed N ⁺ type epitaxial layer 20 to form the P ⁺ type epitaxial layer 21. The surface of the silicon oxide film 16 is grown.

Next, the amorphous silicon on the entire surface is removed.

Next, as shown in FIG. 7, an arbitrary region of the silicon oxide film 16 is removed by photolithography and etching techniques in order to lead out the gate and the source, and then the added impurity ions are activated. for,
For example, 900 ° C. and 30 minutes annealing are performed in a nitrogen atmosphere, and the drain wiring 2 made of aluminum or the like is further used.
2. A vertical MOSFET can be formed by forming the gate wiring 23 and the source wiring 24 and completing each electrode.

[0018]

As described above, according to the method of manufacturing the vertical MOSFET of the present invention, the gate is formed by the epitaxial growth method without using the photolithography and the etching technique, so that the gate length is more than 10 nm. Since the transistor can be formed and the vertical structure is achieved, the area of the transistor can be reduced and higher integration can be achieved.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing an embodiment of a method of manufacturing a semiconductor device according to the present invention together with FIGS. 2 to 7.

FIG. 2 is a vertical cross-sectional view showing an embodiment of a method of manufacturing a semiconductor device according to the present invention, together with FIGS. 1 and 3 to 7.

FIG. 3 is a vertical cross-sectional view showing an embodiment of a method of manufacturing a semiconductor capacitor according to the present invention, together with FIGS. 1, 2, and 4 to 7.

FIG. 4 is a vertical cross-sectional view showing an embodiment of a method of manufacturing a semiconductor capacitor according to the present invention, together with FIGS. 1 to 3 and FIGS. 5 to 7.

FIG. 5 is a vertical cross-sectional view showing an embodiment of a method of manufacturing a semiconductor capacitor according to the present invention, together with FIGS. 1 to 4, 6 and 7.

FIG. 6 is a vertical cross-sectional view showing an embodiment of a method of manufacturing a semiconductor capacitor according to the present invention, together with FIGS. 1 to 5 and 7.

FIG. 7 is a vertical cross-sectional view showing an embodiment of a method of manufacturing a semiconductor device according to the present invention together with FIGS. 1 to 6.

FIG. 8 is a vertical cross-sectional view for explaining the related art with FIGS. 9 to 11.

FIG. 9 is a vertical cross-sectional view for explaining the related art together with FIGS. 8, 10 and 11.

FIG. 10 is a vertical cross-sectional view for explaining the conventional technique together with FIGS. 8, 9 and 11.

FIG. 11 is a vertical cross-sectional view for explaining the related art with FIGS. 8 to 10.

[Explanation of symbols]

11, 201 P-type silicon substrate 12a, 12b Silicon oxide layer 14, 16 Silicon oxide film 13, 20 P ⁺ type epitaxial layer 15 Polysilicon layer 17 Opening 18 Gate oxide film 21 N ⁺ type epitaxial layer 22 Drain wiring 23 Gate wiring 24 Source Wiring 202 N Well Diffusion Layer 203 P Well Diffusion Layer 204 Field Oxide Film 205 Gate Electrode 206 N ⁺ Diffusion Layer 207 P ⁺ Diffusion Layer 208 Insulation Layer 209 Wiring

Claims (6)

[Claims] 1. A method of manufacturing a vertical semiconductor device having a vertical MOSFET structure, comprising a step of forming an epitaxial layer serving as a source in a region on a semiconductor substrate where an element is to be formed, and a step of forming the epitaxial layer on the epitaxial layer. Forming a first insulating layer; forming a gate electrode layer on the first insulating layer; forming a second insulating layer on the gate electrode layer; First insulating layer, the gate electrode layer and the second insulating layer are partially removed to form an opening, a step of forming a gate insulating film on a side surface of the opening, a source layer, a gate layer And a process of forming a drain layer in the opening by epitaxial growth, and a photolithography and etching technique for exposing the gate electrode layer and the epitaxial layer serving as a source. The process of removing the first and second insulating layers, the process of forming a conductive type material for the source, gate, and drain electrodes on the surface of the region, and the photolithography and etching techniques for each electrode. A method of manufacturing a vertical semiconductor device, the method comprising: forming. 2. The method for manufacturing a vertical semiconductor device according to claim 1, wherein the gate insulating film is a film obtained by oxidizing the gate electrode layer by heat treatment. 3. The method for manufacturing a vertical semiconductor device according to claim 1, wherein the gate insulating film is a silicon nitride film. 4. The source layer and the drain layer are P
^The method of manufacturing a vertical semiconductor device according to claim 1, wherein the vertical semiconductor element is a ⁺ type diffusion layer, and the gate layer is an N ⁺ type diffusion layer. 5. The source layer and the drain layer are N
^The method for manufacturing a vertical semiconductor device according to claim 1, wherein the vertical semiconductor element is a ⁺ type diffusion layer, and the gate layer is a P ⁺ type diffusion layer. 6. The method for manufacturing a vertical semiconductor device according to claim 1, further comprising a vertical N-channel MOSFET and a vertical P-channel MOSFET on the same semiconductor substrate.