JPH0521794A - Dieleciric gate type field effect semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE:To improve the characteristics and reliability of an active type liquid crystal display device, or the like, using a dielectric gate type FET transistor as a drive element for a pixel by forming a dielectric film around a gate electrode, and by using a non-photosensitive semiconductor. CONSTITUTION:A dielectric gate type FET transistor in which the distance between a feeding point of the source regions 5 and 5' and drain regions 6 and 6' and the end of a channel is shortened. In such an FET transistor, semiconductor films 2 and 2' designated for the formation of a source region, a drain region, and a channel region of the dielectric gate type FET transistor contain oxygen, carbon and nitrogen 1X10<20>cm<-3> or more and 20 atomic % or less.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating gate type field effect transistor (hereinafter referred to as TFT) having a thin film structure used for an active type liquid crystal display device or an image sensor.
And a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, active type liquid crystal display devices using TFTs have been known. In this case, a polycrystalline semiconductor having an amorphous or crystal grain boundary is used for the TFT, and a P-type or N-type conductivity type TFT is used for one pixel. That is, in general, N-channel type T
An FT (referred to as NTFT) is connected to the pixel in series.

[0003]

However, the semiconductor having an amorphous structure has a low carrier mobility, and in particular, the carrier mobility of a hole is as small as 0.1 cm ² / Vsec or less. Further, the semiconductor having a polycrystalline structure has drawbacks such that the drain breakdown voltage cannot be sufficiently increased due to impurities such as oxygen segregated at the crystal grain boundaries and dangling bonds, and it is difficult to form a P-channel TFT. Further, these have photosensitivity (called photosensitivity PS) and have a drawback that Vg- _ID (gate voltage-drain current) characteristics and the like are largely changed by light irradiation. Therefore, it is an important step to form a light shielding layer so that the channel formation region is not irradiated with light.

In FIG. 2, a liquid crystal (12) is provided, and an NTFT (11) is provided in series with the liquid crystal (12) and arranged in a matrix. Generally 640x
Although it is often 480 or 1260 × 960, in this drawing, a 2 × 2 matrix arrangement is simply used with the same meaning. Peripheral circuits (1
Voltages were applied from 6) and (17) to selectively turn on predetermined pixels and turn off other pixels. Then, when the on / off characteristics of the TFT are generally good, a liquid crystal display device having a large contrast ratio can be manufactured. However, when actually manufacturing such a liquid crystal display device,
The voltage V _LC (10) of the output of the TFT, that is, the input to the liquid crystal (referred to as liquid crystal potential) does not become "1" (High) when it should be "1" (High), and conversely "0". When it should be (Low), it may not be "0" (Low). The liquid crystal (12) is inherently insulating in its operation, and when the TFT is off, the liquid crystal potential (V
_LC ) is in a floating state. Since this liquid crystal (12) is a capacitor in terms of an equivalent circuit, V _LC is determined by the charges accumulated therein. This charge is the conventional TF
T is photo-sensitive, so when the light is not sufficiently shielded, the TFT
The current leaks (15) through the channel of
As a result, the level of V _LC fluctuates. Furthermore, when the liquid crystal has a relatively small resistance at R _LC and a leak (14) occurs, V _LC becomes a halfway state. Therefore, in a liquid crystal display device having 200,000 to 5 million pixels in one panel, a high yield cannot be achieved.

Further, as in the conventional case, when the gate electrode is covered with a silicon nitride film, a silicon oxide film or the like, a contact hole is formed by a photolithography method, and then a power supply point to the source or the drain is provided, each power supply is performed. Since the distance between the point and the end of the channel becomes long, a resistance component is generated there in the TFT manufactured by the thin film low temperature process, resulting in deterioration of frequency characteristics and increase of ON resistance.

Therefore, the present invention is an improvement of the conventional TFT in order to shorten the distance between the feed point to the source or drain region adjacent to the channel region and the channel end portion of the insulated gate field effect semiconductor device. .

[0007]

According to the present invention, aluminum is used as a gate electrode material to provide aluminum oxide by anodizing method of aluminum on the surface thereof, and three-dimensional wiring having three-dimensional intersections thereon. It is characterized by that. Further, by providing the source / drain contact holes with the gate electrode and the aluminum oxide around the electrodes to bring the feeding point closer to the channel, it was possible to prevent the frequency characteristics of the device from decreasing and the ON resistance to increase.

According to the present invention, the semiconductor material of the channel forming region of the TFT is made non-photosensitive to light, and for that reason, hydrogen having an amorphous structure in which oxygen, carbon or nitrogen is added is added to the channel forming region of the TFT. By using a semiconductor film containing a silicon semiconductor as a main component, and heat-treating that region, the photosensitivity is lost while having crystallinity. Especially as a material, SiO
_{As shown by 1-X} (0 <X <1) and SiN _1-X (0 <X <1), a so-called silicon semiconductor is modified. The total amount of O, C and N is 1 × 10 ²⁰ cm ^{-3 to} 20
Atomic%, preferably 3 × 10 ²⁰ cm ^{-3 to} 5 atomic% makes it non-photosensitive, and this silicon semiconductor is heat-treated at 500 to 750 ° C. to be crystallized to have a carrier mobility of 5 cm. ^{Since it is 2} / Vsec or more, the crystal grain boundary is substantially eliminated and the semiconductor material has crystallinity.

As the heat treatment method, a heating method using a general heating furnace and a method of irradiating laser energy represented by excimer laser light, that is, light energy are used.

This material is non-photosensitive, that is, the current change in the ON state is 10% or less, and the dark current value in the OFF state (sub-threshold state) is on the order of 10 ^-9 A. It was achieved under the irradiation of visible light of 2000 candela that the increase of 10 ^-7 A or less, that is, the change of less than 2 digits was achieved.

When the present invention is applied to a liquid crystal display device, each pixel (transparent conductive film and T
The output terminal of the complementary TFT was connected to the electrode of one transparent conductive film (pixel) of the FT). That is, P-channel type T
FT (hereinafter referred to as PTFT) and NTFT are connected as a complementary type (hereinafter referred to as C / TFT) to form one pixel.

A typical example thereof is shown as a circuit in FIG. An example of an actual pattern layout (arrangement diagram) is shown in FIG.

That is, in the example of the 2 × 2 matrix shown in FIG. 3, the gates of PTFT and NTFT are connected to each other, and the line V _GG (22) in the Y-axis direction or V
_It was ligated to _{GG '} (23). The common output of the C / TFT is connected to the liquid crystal (12). Input of PTFT (V
_DD side) is the line in the X-axis direction V _DD (18), V _{DD '} (18')
The input of the NTFT (V _SS side) is connected to V _SS (19). Then, when V _DD (18) and V _GG (22) are “1”, the liquid crystal potential (10) becomes “0”, and V
_{When DD} (18) is “1” and V _GG (22) is “0”, the liquid crystal potential (10) is “1”. That is, V _GG and V _LC are in “reverse phase”.

The liquid crystal potential (10) is V _DD (18),
Alternatively, since it is fixed to either ground or V _SS (19), it does not cause floating. In FIG. 3, if the NTFT and the PTFT are arranged in reverse, V _GG and V _LC can be “in phase”. The present invention will be described below based on Examples.

[0015]

EXAMPLES Example 1 In this example, the present invention will be described with reference to FIG. The manufacturing process when a C / TFT is not manufactured on a glass substrate is shown based on FIG.

In FIG. 1, glass (1) that can withstand heat treatment at about 600 ° C., such as AN glass and Pyrex glass.
A silicon oxide film, which is a blocking layer (38), is formed on the upper surface of the substrate by using a magnetron RF (radio frequency) sputtering method at a thickness of 1000 to 3
It was made to a thickness of 000Å.

The process conditions are an oxygen 100% atmosphere, a film forming temperature of 150 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa.
And The deposition rate using quartz or single crystal silicon for the target was 30Å / min.

A silicon film to which oxygen, carbon or nitrogen was added was formed thereon by LPCVD (Low Pressure Vapor Phase) method, sputtering method or plasma CVD method.

The main component of this semiconductor film is silicon, and SiO _{1 -X} (0 <X <1), SiC _1-X (0 <X <
1) or SiN _1-X (0 <X <1), which is actually a mixture of O (oxygen), C (carbon), and N (nitrogen). Here, a small amount of oxygen that is particularly easy to mix is intentionally added. And the amount of oxygen is 1 × 10 ²⁰ cm ^-3
.About.20 atomic%, preferably 3 × 10 ²⁰ cm ^{-3 to} 5 atomic%.

When formed by the reduced pressure vapor phase method, it is 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature, for example, 5
Disilane (Si ₂ H ₆ ) or trisilane (S
i ₃ H ₈ ) with an oxide gas such as nitrous oxide (N ₂ O) N ₂ O / (Si ₂ H ₆ or Si ₃ H ₈ ) = 0.001
Films were formed by supplying them to the CVD apparatus at a mixing ratio of 0.1 vol%. The pressure in the reaction furnace was 30 to 300 Pa. The film forming rate was 30 to 100Å / min. In order to control the threshold voltage (Vth) of the NTFT and the PTFT to be substantially the same, boron is used in an amount of 1 × 10 ^{15 to} 5 × 1 by using diborane.
A concentration of 0 ¹⁷ cm ^-3 may be added during film formation.

When the sputtering method is used, the back pressure before sputtering is set to 1 × 10 ^-5 Pa or less, single crystal silicon is used as a target, and argon is mixed with hydrogen in an amount of 50 to 80% by volume. For example, argon 20% by volume, N ₂ O
0.001% to 0.1% by volume, remaining hydrogen about 80% by volume
And Deposition temperature is 150 ℃, frequency is 13.56MH
z, and the sputtering output was 400 to 800 W. The pressure was 0.5 Pa. When a silicon film is formed by the plasma CVD method, the temperature is set to, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (SiH ₆ ) is added to the N film.
₂ O / SiH ₄ = 0.001-0.1% by volume of oxide,
A mixture of nitride gas was used as the reactive gas.
These were introduced into a PCVD apparatus, and high-frequency power of 13.56 MHz was applied to form a film.

The coating formed by these methods is
Oxygen is 1 × 10 ²⁰ cm ^{−3 to} 20 atom%, preferably 3 ×
The concentration is preferably 10 ²⁰ cm ^{-3 to} 5 atom%.

That is, in order to have non-photosensitivity, C, O, N
Should be added, but if it is too large, it will be difficult to crystallize even in the subsequent heat treatment, and as a result, the carrier mobility will be 5 cm ²
/ Vsec or more, preferably 10 to 100 cm ² / Vsec cannot be obtained.

Thus, the amorphous silicon film 1
After being manufactured to a thickness of 000 to 10,000 Å (1 μm), for example, 3,000 Å, it was heat-treated in a non-oxide atmosphere for 12 to 70 hours at a medium temperature of 500 to 750 ° C. which does not cause crystal growth. For example, it was maintained at a temperature of 600 ° C. in a nitrogen or hydrogen atmosphere. Further, by using an excimer laser other than the above heating method to instantaneously melt the semiconductor surface, it is possible to obtain the same effect as the heat annealing, or the same or more effects. In this case, an excimer laser with an intensity of 100 to 300 mJ / cm ² is used for 10 to 100 sh.
Crystallization can be performed by irradiation with oto.

Since a silicon oxide film having an amorphous structure is formed on the surface of the substrate below the semiconductor film, no specific nuclei are present in this heat treatment and the whole is uniformly annealed. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

By this annealing, the semiconductor film shifts from the amorphous structure to the highly ordered state, and a part thereof exhibits the crystalline state. In particular, a region having a relatively high degree of order during the film formation of silicon is particularly crystallized and tends to be in a crystalline state.
However, since silicon existing between these regions forms a bond with each other, the silicon members pull each other. As a crystal, when measured by laser Raman spectroscopy, a (111) crystal peak having a lattice strain shifted to a low frequency side from a peak 522 cm ^-1 of a silicon (111) crystal orientation of a single crystal.
Ku is observed. The apparent grain size is 50 to 500 Å, which is similar to that of microcrystals, calculated from the half-width. However, in reality, there are many regions with high crystallinity and they have a cluster structure. It was possible to form a film having a semi-amorphous structure in which silicon was bonded to each other (anchoring).

For example, when distribution measurement in the depth direction is performed by SIMS (secondary ion mass spectrometry), oxygen is 3. in the lowest region (surface or a position apart from the surface (inside)) as an additive (impurity). 4 × 10 ²⁰ cm ⁻³ and nitrogen 4 × 10 ¹⁷ cm ⁻³ were obtained. Also, hydrogen is 4 × 10 ²⁰ cm ^-3
When compared with silicon 4 × 10 ²² cm ⁻³ , it was 1 atom%.

This crystallization has an oxygen concentration of, for example, 1.5 × 1.
At 0 ²⁰ cm ^-3 , 600 ℃ (4
It is possible to perform heat treatment for 8 hours. This is 5 × 10 ²⁰ cm
^If it is set to ^-3 , the film thickness becomes 0.3 to 0.5 μm and it becomes 6
Crystallization by annealing at 00 ° C was possible,
A heat treatment at 650 ° C. was necessary for crystallization at a thickness of 0.1 μm. That is, the thicker the film thickness and the lower the concentration of impurities such as oxygen, the easier the crystallization was.

As a result, this coating exhibits a state in which it may be said that it is substantially free of grain boundaries (referred to as GB). Carriers can easily move from one cluster to another through anchored points, so
The carrier mobility is higher than that of polycrystalline silicon that clearly exists. That is, hole mobility (μh) = 10 to 50 cm ² / Vs
ec, electron mobility (μe) = 15 to 100 cm ² / Vsec is obtained.

Further photosensitizer capability is, I is irradiated with light of 2000 lux from the glass side while obtaining Vg (gate voltage) -I _D (drain current) characteristic of a TFT
_The condition that _D does not move more than 10% in the on-state region (no drift condition) or the condition that I _D increases (drift) by less than 2 digits in the sub-threshold voltage region (the off current is sufficiently small). The condition) was measured. Then, if the oxygen concentration is a low concentration such as 8 × 10 ¹⁹ cm ⁻³ , there is a drift, but if the oxygen concentration is 1 × 10 ²⁰ cm ⁻³ or more, preferably 3 × 10 ²⁰ cm ⁻³ or more, the drift is almost PT.
Neither was found in FT or NTFT.

On the other hand, when the film is polycrystallized by a high temperature anneal of 900 to 1200 ° C. instead of the anneal at a medium temperature as described above, segregation of impurities such as oxygen in the film by solid phase growth from nuclei. As a result, GB has a large amount of impurities such as oxygen, carbon, and nitrogen, and the mobility in the crystal is large.
Creates a barrier in the and prevents the movement of carriers there. And, as a result, the reality is that only mobility of 5 cm ² / Vsec or less can be obtained.

That is, in the embodiment of the present invention, as described above, a silicon semiconductor having a semi-amorphous or semi-crystalline structure having no photosensitivity and having crystallinity is used.

In FIG. 1A, this silicon film is photoetched using a first photomask, and PT
A region (21) for FT was formed on the right side of the drawing, and a region (11) for NTFT was formed on the left side.

Further, a silicon oxide film (38) is used as a gate insulating film and the thickness is 500 to 2000Å, for example, 100.
Formed to 0Å. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. A small amount of fluorine may be added during this film formation.

In order to improve the interface characteristics between the silicon oxide and the underlying semiconductor film and remove the interface level, it is preferable to add ultraviolet light at the same time to perform ozone oxidation. That is, the sputtering method and the photo-CVD under the same conditions as the formation of the blocking layer (38).
When combined with the method, the interfacial height could be reduced.

After that, an aluminum film having a thickness of 0.3 μm was formed on the upper side. This was patterned with a second photomask. Then, a gate electrode (4) for PTFT and a gate electrode (4 ') for NTFT were formed. For example, the channel length is 10 μm.

In FIG. 1C, the photoresist (3
1 ') is formed using a photomask, and boron (1 × 10 ¹⁵ cm ^-2 ) is formed on the source (5) and drain (6) for the PTFT by using the gate electrode (4) as a mask.
The amount of impurities was added by the ion implantation method.

Next, as shown in FIG. 1D, a photoresist (31) was formed using a photomask. And N
The gate electrode (4 ′) is used as a mask to form phosphorus (1 ×) for forming a source (5 ′) and a drain (6 ′) for the TFT.
An amount of 10 ¹⁵ cm ^-2 was added by the ion implantation method.

These are performed through the gate insulating film (3). However, in FIG. 1B, the gate electrode (4),
The silicon oxide on the silicon film may be removed using (4 ′) as a mask, and then boron and phosphorus may be directly ion-implanted into the silicon film.

Next, after removing these photoresists (31), heating and annealing is performed again at 650 ° C. for 10 to 50 hours.
I went to Le. The source (5) and drain (6) of PTFT, the source (5 ') and drain (6') of NTFT
Were activated as impurities to prepare p ⁺ and n ⁺ .

Channel forming regions (7) and (7 ') are formed as semi-amorphous semiconductors under the gate electrodes (4) and (4').

In this way, the C / TFT can be manufactured without applying a temperature of 700 ° C. or higher in all steps even though the self-alignment method is used. Therefore, it is not necessary to use an expensive substrate such as quartz as the substrate material, and the process is extremely suitable for the large-pixel liquid crystal display device of the present invention.

Thermal annealing was performed twice in FIGS. 1 (A) and 1 (D). However, the anneal of FIG. 1 (A) may be omitted depending on the desired characteristics, and both may be served by the thermal anneal of FIG. 1 (D) to reduce the manufacturing time.

In FIG. 1E, the gate electrode (4),
(4 ') was anodized to form an aluminum oxide (40) around it. The thickness of aluminum oxide is 0.2 to 1 μm, for example, 0.5 μm, and the aluminum oxide is formed in this embodiment.

In FIG. 1F, a silicon oxide film was formed as the interlayer insulator (8) by the above-mentioned sputtering method.
The silicon oxide film may be formed by the LPCVD method or the photo-CVD method, and the film thickness is, for example, 0.2 to 1.0 μm. After that, as shown in FIG. 1F, a window (32) for an electrode was formed using a photomask. At that time, RIE
Using the (anisotropic etching) method, the gate electrode (4),
The feature of the present invention is that the contact hole (32) is located as close as possible to the vicinity of the channel by utilizing the self-alignment property of (4 ′).

Further, these are entirely aluminum (35)
Was formed by sputtering to a thickness of 0.5 to 1 .mu.m, and leads (9) and (9 ') were formed using this aluminum film. Then, an organic resin (34) such as polyimide was formed.

Further, the interlayer insulator (8), aluminum (35), and organic resin (34) were removed using a photomask on the portions to be the contacts (29) and (29 ').
Got a window for the contact. Further, an ITO film (33) which is a transparent conductive film to be a pixel electrode was formed to obtain the shape shown in FIG.

The characteristics of such a TFT are abbreviated as Table 1 below. Mobility (μ), threshold voltage, drain breakdown voltage (V _BDV ), photosensitivity (PS)
Was as follows:

[0049]

[Table 1]

The characteristics shown in Table 1 above have a channel length of 10 μm.
m and a channel width of 30 μm. By using such a semiconductor, it is possible to obtain a large mobility in the TFT, which is generally considered impossible, and in addition, there is no photosensitivity,
Moreover, the drain breakdown voltage was obtained at a large level. Therefore, the NTFT or C / TFT for the liquid crystal display device shown in FIGS. 2 and 3 could be constructed for the first time.

This embodiment is an example of a liquid crystal display device, and in order to connect the output of this C / TFT to a pixel, an organic resin (34) such as polyimide is further formed in FIG. To open the window again and connect the output ends of the two TFTs to one transparent electrode of the liquid crystal device.
A tin oxide film) was formed. It was further etched with a photomask to form a transparent electrode (33). This ITO film is formed at room temperature to 150 ° C.
Fulfilled by oxygen at 0-300 ° C or anneal in air.

In this way, the PTFT (21) and NT
The FT (11) and the transparent conductive film electrode (33) were formed on the same glass substrate (1).

[Embodiment 2] FIG. 4 shows an embodiment corresponding to FIG. V _DD (18), V _SS (19) in the X-axis direction,
_{Wirings in the} X-axis direction (hereinafter also referred to as X-rays) having V _DD '(18') and V _SS (19 ') were formed. In the Y-axis direction, V _GG (22) and V _GG ′ (23) and wiring in the Y-axis direction (hereinafter also referred to as Y line) were formed.

In this example, the C / TFT whose manufacturing process was described in Example 1 was used. In this embodiment, the PTFT (21) is provided at the intersection of the X-ray V _DD (18) and the Y-line V _GG (22), and V _DD (18) and V _GG '
At the intersection with (23), the PTFT (21 'for another pixel is also provided.
) Is similarly provided. The NTFT (11) is provided at the intersection of V _SS (19) and V _GG (22). An NTFT (11 ') for another pixel is provided below the intersection of V _SS (19) and V _GG ' (23).
It has a matrix structure using C / TFT. In these PTFTs, the source (5) is connected to the X-ray V _DD (18) through the contact (32), and the gate (4) is connected to the Y-line V _GG (22) having a multilayer structure. . The drain (6) is connected to the electrode (33) of the transparent conductive film via the contact (29).

On the other hand, in the NTFT, the source (5 ') is connected to the X-ray V _SS (19) via the contact (32'),
Gate (4 ') is on the Y line V _GG (22) and drain (6')
) Is a transparent conductive film (3) via a contact (29 ').
It is linked to 3). Thus two X-rays (18),
One pixel was constituted by the transparent conductive film (33) and the C / TFTs (21) and (11) while being sandwiched between (19) (inside). One example of a 2 × 2 matrix or an enlarged version of 640 × 480, 1280 × 9 is obtained by repeating such a structure horizontally and vertically.
It became possible to make a large-screen LCD such as 60.

The feature here is that two TFs are provided for one pixel.
T is provided in a complementary configuration, and the electrodes (3
3) constitutes the liquid crystal potential V _LC , which is fixed at either level of PTFT on and NTFT off, or PTFT off and NTFT on.

Even if light is radiated from the glass substrate side, the C / TFT is non-photosensitive to light, so that not only the reflective type but also the transmissive type liquid crystal display device has a shielding means. It was possible to operate without providing.

As is apparent from FIG. 4, even if Vss of the control element is newly increased, the aperture ratio (total area (3
Regarding 5), the liquid crystal display effective area (33) actually displayed is not different from the conventional case where a TFT having only one conductivity type is connected to each pixel in FIG.
Not at a disadvantage.

In FIG. 4, an alignment film and an alignment treatment are applied to the transparent conductive films, and a constant gap is provided between this substrate and the other liquid crystal electrode (corresponding to (13) in FIG. 3). , And they were arranged by a known method. Then, liquid crystal was injected in the meantime to complete a liquid crystal display device.

If TN liquid crystal is used as the liquid crystal material, it is necessary to form the alignment film on both of the transparent conductive films by rubbing treatment with a gap of about 10 μm. When FLC (ferroelectric) liquid crystal is used as the liquid crystal material, the operating voltage is set to ± 20 V, and the cell interval is 1.5 to 3.5 μm.
For example, the thickness is 2.3 μm, and although not shown in FIG. 4, an alignment film may be provided only on the opposite electrode existing on the counter electrode of the substrate shown in FIG. .

When the dispersion type liquid crystal or polymer liquid crystal is used, the alignment film is unnecessary, and the operating voltage is ± 10 ± 15 V and the cell interval is thinned to 1-10 μm in order to increase the switching speed. . In particular, when a dispersion type liquid crystal or a polymer type liquid crystal is used, since a polarizing plate is not necessary, it is possible to increase the amount of light both as a reflection type and a transmission type. Since the liquid crystal has no threshold hold,
As shown in the C / TFT of the present invention, a clear threshold
By adopting the C / TFT type in which the threshold voltage is regulated, a large contrast and crosstalk (bad interference with the adjacent pixel) can be eliminated.

In this embodiment, V _DD (1
PTFT (21) on the 8) side and NTF on the Vss (19) side
T (11) was formed. Then its output is V _DD or V
You can determine a definite level to make ss. But V
_{For GG} (22), V _LC becomes an inverter (reverse phase). Further, in FIG. 3, the positional relationship between the PTFT and the NTFT may be replaced with a target.

[Embodiment 3] In this embodiment, each pixel shown in FIG. 2 is of a 1Tr / cell type in which only NTFT is connected to each pixel or the like. Then, the level of V _LC varies due to floating, but since the TFT shown in the present invention is non-photosensitive, it cannot be used in actual use.
It was not necessary to provide a light-shielding means for preventing the light from being emitted to the active liquid crystal display device, which was easier than in the past. Others are the same as in the first and third embodiments.

[0064]

INDUSTRIAL APPLICABILITY According to the present invention, by using aluminum as a gate electrode material, aluminum oxide by anodizing method of aluminum is provided on the surface, and three-dimensional wiring having a three-dimensional intersection is provided thereon. It has a feature. Further, by providing the source / drain contact holes with the gate electrode and the aluminum oxide around the electrodes to bring the feeding point closer to the channel, it was possible to prevent the frequency characteristics of the device from decreasing and the ON resistance to increase.

The present invention makes the non-photosensitive semi-amorphous semiconductor by adding impurities such as oxygen to the channel formation region by making it non-photosensitive with respect to the NTFT and PTFT, thereby making the light shielding means unnecessary. became. Further, the effects shown in Table 2 below were able to be obtained by connecting to such each pixel, which was matrixed as a TFT, particularly C / TFT.

[0066]

[Table 2]

The present invention shows an example in which a non-photosensitive TFT is manufactured and used for a liquid crystal display device as its application. However, it can also be used as a load or a three-dimensional element in other semiconductor devices, for example, an image sensor, a monolithic integrated circuit.

For the C / TFT according to the present invention,
As the semiconductor, a non-photosensitive material having a semi-amorphous or semi-crystalline structure as a main component was used.
However, other crystalline semiconductors may be used if possible for the same purpose. Self-aligned C /
High-speed processing was performed by using a TFT. However, the TFT is not self-aligned without using the ion implantation method.
Needless to say, you can make

[Brief description of drawings]

FIG. 1 shows a method for manufacturing a P-channel type TFT and an N-channel type TFT of the present invention.

FIG. 2 shows a liquid crystal display device using 1Tr / cell active TFTs.

FIG. 3 is a circuit diagram of a 2Tr / cell type active liquid crystal device using a complementary TFT of the present invention.

FIG. 4 is a plan view of one substrate of the liquid crystal display device corresponding to FIG.

[Explanation of symbols]

(1) ・ ・ ・ ・ Glass substrate (2), (2 ') ・ ・ Semiconductor thin film (3) ・ ・ ・ ・ Gate insulating film (4), (4') ・ ・ Gate electrode (5), (5 ') ) ・ Source (6), (6 ') ・ ・ Drain (7), (7') ・ ・ Channel formation region (10) ・ ・ ・ ・ Liquid crystal potential (V _LC ) (11) ・ ・ ・ ・N-channel thin film transistor (N
(TFT) (21) ... P-channel thin film transistor (P
TFT) (12) ··· Liquid crystal (40) ··· Aluminum oxide

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[Procedure amendment]

[Submission date] July 9, 1992

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 3]

[Figure 4]

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9056-4M H01L 29/78 311 R

Claims (4)

[Claims] 1. An insulating gate type field effect semiconductor device having a thin film structure provided on a substrate, wherein aluminum is used for a gate electrode and at least a part of the periphery of the gate electrode is covered with an oxide of aluminum. The semiconductor forming the channel formation region is sandwiched between insulators, oxygen,
The main component is a silicon semiconductor containing carbon or nitrogen of 1 × 10 ²⁰ cm ⁻³ or more and 20 atomic% or less,
An insulating gate type field effect semiconductor device characterized by having crystallinity. 2. The pair of insulating films according to claim 1, wherein the insulating film has a gate electrode on a film forming a gate insulating film, and has one conductivity type of N type or P type separated from each other by a channel formation region. An insulated gate field effect semiconductor device comprising an N channel type, P channel type or complementary type thin film insulating gate type field effect semiconductor device having a region. 3. A hydrogen-added silicon semiconductor as a main component having an amorphous structure in which oxygen, carbon or nitrogen is added in an amount of 1 × 10 ²⁰ cm ⁻³ or more and 20 atomic% or less on a substrate having an insulating surface. Forming a coating film using a sputtering method, a plasma vapor phase reaction method, or a vapor phase reaction method, and subjecting the coating film to a heat treatment at a temperature in the range of 500 to 750 ° C. to transform it into a crystalline structure. A step of oxidizing at least a part of the periphery of the gate electrode by an anodic oxidation method, and a step of forming a contact hole with a source / drain by using the gate and the insulating film around the gate as a cell line. A method for manufacturing a characteristic insulating gate type field effect semiconductor device. 4. A hydrogen-added silicon semiconductor as a main component, which has an amorphous structure in which oxygen, carbon or nitrogen is added in an amount of 1 × 10 ²⁰ cm ⁻³ or more and 20 atomic% or less on a substrate having an insulating surface. Forming a coating film using a sputtering method, a plasma vapor phase reaction method, or a vapor phase reaction method, a step of transforming the coating film into a crystalline structure by heat treatment with an excimer laser beam, and a gate electrode An insulating gate, comprising: a step of oxidizing at least a part of a periphery of the gate by an anodic oxidation method; and a step of forming a contact hole with a source / drain by using the gate and the insulating film around the gate as a cell line. Method of manufacturing a field effect semiconductor device of the semiconductor type.