JPS58224489A - Device for specifying address of memory - Google Patents

Abstract

PURPOSE:To execute interleaving and deinterleaving at the memory capacity close to really required memory capacity, by folding the address specfying method of a memory in the memory. CONSTITUTION:The gate circuit 21 of a writing address specifying circuit 20 for deinterleaving is controlled by a control circuit 23 and an up/down counter 22 counts up writing clocks and outputs the counted result to a selector 14 as a line address of a memory 40. When the counted value of the counter 22 reaches a prescribed number, the circuit 21 is actuated by a control signal A from the circuit 23 and the counter 22 starts to count down. A subtractor 27 to output a saw address signal is also actuated by the signal A and subtracts a prescribed number through a counter 26, etc. to change the saw address with is fixed during the up-counting of the counter 22. The reading of deinterleaving and the address specification of interleaving are executed in the same manner. Thus, the interleaving and deinterleaving enabled to prevent burst errors are executed by using a memory having capacity close to the really required memory capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory addressing device, and more particularly to a memory addressing device used when interleaving or gain interleaving is performed in blocks of one frame data.

Recently, PCM recorders and PCM audio discs have
Error correction codes are used to obtain high quality reproduced sound. This error correction coding method divides a sampled signal word sequence obtained by zumbling an analog signal into blocks of multiple words or frames, adds an error correction word to each block to form one error correction block, and then transmits the data. This method corrects incorrect words on the road during playback. However, such an error correction code system has a limit, and when most of the words in one error correction block are erroneous due to burst errors occurring on the transmission path, correction becomes impossible.

Conventionally, as a countermeasure against burst errors, a correction block [
performing interleaving to disperse each word in the cock, recording each word on a recording medium at intervals;
Error correction was performed by performing dinterleaving to restore the original arrangement during playback.

FIG. 1 is an illustrative diagram of a data format for explaining interleave and dinterleave processing, which is the background of this invention. In the figure, when one frame is one block, one block consists of eight words Do to D7, and the data of the Nth block (frame) is used as an error correction block. In this case, 1
is DO~D with an error correction code added to the sampled signal word.
8 shows the Nth error correction block consisting of 8 words. However, N is an integer. , 2 are each word Do, D1 . Delay amount of D2 to D7 0, d, 2d~
7d. However, d indicates an integer unit delay amount, and is selected, for example, as the data transmission time of one word. During interleaving, each word Do-D7 of the sampled signal word string is delayed by a delay amount corresponding to each word. 3 shows the word structure of one block after interleaving. After the interleaving process, each word is composed of words of different error correction blocks and is recorded on the recording medium. 4 indicates the amount of delay for each word when interleaved data is dinterleaved as described above. The amount of delay in dinterleaving is selected to be inversely proportional to the amount of delay in interleaving. For example, the interleaving process is for words Do, Di to D7.
The delay amount is 0. If d to 7d is selected, the dinterleave delay amount is selected to be 76.68 to 0. 5 is 1 after the dinterleaving process is performed.
This shows the format of the correction block.

As is clear from the illustration, each word DO-07 is all equal to the word of the N-7dth error correction block, and has returned to the combination U before interleaving, except for the delay 117d.

When performing interleave processing and dinterleave processing as shown in Figure 1, even if a burst error occurs on the transmission path and an error occurs in 8 words of the block indicated by 3, the dinterleave processing is performed. By doing this, erroneous words are dispersed, so in the block obtained by the dinterleaving process, D7. Only I'm-d is an error, and correction is not possible. 5 to realize such delay processing of interleave and dinterleave
- To do this, a method is used in which one block of word data is temporarily stored in a memory and the desired word is read out. Memory address control when performing dinterleaving in the case of the delay amount d-16 in FIG. 1 will be explained below.

FIG. 2 is a block diagram of a conventional memory addressing device when performing interleave and dinterleave processing. In the figure, addressing device 10
includes write addressing circuitry and read addressing circuitry. The specific configuration of the addressing device 10 will be described below.

A write sample clock (hereinafter referred to as clock WS) is applied to the input terminal 11a. This clock WS is applied to the addition input terminal of the counter 12.

The counter 12 has a 3-pit output, performs an addition operation every time the clock WS is applied, and derives the counted value as write address data of one block of words. A write block change clock (hereinafter referred to as clock WB) is applied to the input terminal 11b. This clock WB is applied to the reset input terminal of the counter 12 and also to the addition input terminal of the counter 13. The output of this counter 12 is given to a selector 14 as write address data for the lower 3 bits of a memory (not shown). The output of the counter 13 is given to the selector 14 as write address data specifying the upper address of the memory.

A continuous sample clock (hereinafter referred to as clock R8) is applied to the input terminal 110. This clock R8 corresponds to 8 words in one correction block. The clock R8 is applied to the addition input terminal of the counter 15 and also to the counter 16. The counter 15 has an output to the 3-bit 1, performs an addition operation every time the clock R8 is applied, and is reset by the clock RB input to the input terminal 11d. The clock RB is a read block change clock, and is applied one clock at a time as the correction block advances.The clock RB is applied to the addition input terminal of the counter 17.

Counter 17 has a 4-bit output and provides a carry output to the addition input terminal of counter 18. Counter 18 provides its count value as a parallel input to counter 16.

A load signal (LD) applied to the input terminal 11e is input to the counter 16. These counters 15-1
The read address of the memory is determined by the output of 7.

That is, the output of the counter 15 is derived as read address data specifying the address of the lower 3 bits.

The outputs of counters 16 and 17 are derived as successive address data specifying an upper address in the memory. These read address data are given to the selector 14.

The selector 14 switches and derives a write address or a read address in response to a select signal applied to an input terminal 11f. The write address data or read address data selected by the selector 14 is derived from the output terminal 11'g and applied to the memory as memory address data.

The outputs of counters 17 and 18 are input to initial setting circuit 19 . This initial setting circuit 19 has a counter 17
When the value determined by the outputs of and 18 (ie, the count value of successive upper bits) is O, an output is generated to set the counter 13 to delay 7d.

FIG. 3 is a time chart for explaining the operation of the write address designation circuit.

FIG. 4 is a time chart for explaining the operation of the successive addressing circuit.

FIG. 5 is a diagram schematically showing a memory map per 1 bit for storing 1 word data. In the figure, the horizontal axis shows the address value of the lower three bits, and the vertical axis shows the upper address value. A memory address is specified by a combination of addresses on the vertical and horizontal axes. In addition, the circles in Figure 5 indicate successive data,
Triangular marks indicate written data.

Next, with reference to FIGS. 2, 3, and 5, the operation of the write address designation circuit will be described along the time chart of FIG. 3. In the illustrated example, 8 words in the 9-1 transmission block (3 in Figure 1) are written with the upper address constant and the lower address changed from 0 to 7, and the next block is written by the clock WB. This shows the case where the upper address is incremented by 1 and written.

At time t1, counter 12 is reset by clock WB. Therefore, the output of the counter 12 is O
At the same time, the output of the counter 13 changes from 7d-1 to 7d.

At time t2, the counter 12 increments its count value by 1 and outputs 1 in response to being supplied with the clock WS. At this time, the data of the Nth leading word Do,N is calculated by multiplying the upper address value by n and the lower address value by n during the period between time t1 and time t2 (m,
n) is written to the area specified by the address.

In this case, the output (7d) of the counter 13 becomes the upper address value (+n), and the output (0) of the counter 12 becomes the n address value, so the data of the first word is written to the address (7d, O). It turns out. Next 10- Word D1. The data of N-d is the address (7d.

1). Thereafter, in the same manner, the address to the lower three bits 1 is incremented by 1 for each word, and the data of words D2 to D7 is written to the write address determined by the output of the counter 13 and the output of the counter 12. It will be done.

Then, at time [3], when writing of 8 words of data is completed, the clock WB is applied. For this reason,
The count value of the counter 13 is incremented by 1, the upper address (m) becomes (7d+1>), and the next block (N+
The data of each word of 1) is sequentially written.

Next, with reference to FIGS. 2, 4, and 5, the operation of the successive addressing circuit will be described along the time chain foot of FIG. 4.

At time t1, the clock RB is input, so the count value of the counter 15 becomes O. At this point, counter 1
3 is initialized by the initial setting circuit 19, and the m-bit upper address is set so that the read system lags the write system by 7d. For this reason, the count value of the higher rankings becomes O.

At time t4, the load clock is applied to the input terminal 11e, so O is loaded into the counter 16. Therefore, the calling address becomes (0°0). The output of the memory at this time is, as shown in FIG.
7d is output.

At time t5, when clock R3 is applied, the output of counter 15 becomes 1. At the same time, counter 1
6 is incremented by 1, and the upper read address value is incremented by d. Therefore, the memory read address is (d, 1)
So, DI, N-d-66 (=D1.11-76)
data is read from memory.

Thereafter, in the same way, the 81 values of counters 15 and 16 are incremented by 1, and the data stored in the address specified by the numerical values of both hands is read out, finally reaching 5 in Figure 1. The word arrangement of the N-7dth correction block can be obtained as shown in FIG.

The above operations can be performed continuously by synchronizing the write system and the read system, and by sequentially addressing the memory by matching the clock phase so that the data of word D7 is written and then read. In the example shown in Figure 1, after writing the data of the block shown in 3 to the upper address value 7 (1), the data of the next block is written to the address whose upper address value is O. After reading the data (D7.N-76) whose read address is (7d, 7), read the data (DO, N-76) of the first word of the next correction block I cock.
-7d+1) starting from address (1,0), 8x(7d+-l) per 1 bit of word
Dinterleaving can be performed by cycling through the memory of pin 1-.

However, while the conventional addressing device shown in Fig. 2 has a simple circuit configuration, the memory capacity required for gain interleaving is 28 d per bit of a word, whereas it is 8 x (7 d + 1) bits. The disadvantage is that the memory capacity increases due to the use of

13- Therefore, this invention was made to eliminate the above-mentioned drawbacks of the conventional method, and it is possible to perform dinterleaving with about half the memory capacity of the conventional method,
The purpose is to provide an inexpensive addressing device.

To summarize, this invention is such that the address corresponding to the sample is turned back midway, and the upper address is also changed.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

FIG. 6 is a block diagram of a memory addressing device according to an embodiment of the present invention. In the figure, the device for specifying the memory address for dinterleaving is a write addressing circuit 20. It is configured to include a successive addressing circuit 30 and a selector 14. Write address specification device @
20 is a gate circuit 21. Counter 22. Control circuit 23
．． Counters 24-26. It is configured to include a subtracter 27 and an initial setting circuit 28. This gate circuit 21 and -
The control circuit 23 constitutes a barb means 14-. The jy counter 22 functions as a first address data generating means for generating an m-bit address.

The counters 24 to 26 and the subtracter 27 constitute a second address data generating means for generating address data of n pips 1 to 1.

Next, a specific configuration of the -include address designation circuit 20 will be explained. Goo 1 to circuit 21 are clocks WS.

Outputs a and b of the control circuit 23 are input. This gate circuit 21 connects two OR games 1 to 21 as shown in FIG.
1.212. The counter 22 is an up/down counter having a 2-bit output, and one output C of the gate circuit 11 is applied to an addition input terminal, and the other output d is applied to a subtraction input terminal. A clock WB is input to the reset terminal of the counter 22.

The counter 24 is a 4-bit counter, is incremented by the clock WS, and is initialized by the initial setting circuit 28. The counter 25 receives the carry output of the counter 24 as an input, and is preset by the output of the initial setting circuit 28. In the counter 26, the output d of the gate circuit 21 is applied to an addition input terminal, and the output λ of the counter 25 is applied as a parallel load input. The counter 26 loads the output of the counter 25 every time a write load clock (hereinafter referred to as clock WL) is applied via the input terminal 11f. When the output a of the control circuit 23 is 1 (high level), the subtracter 27 outputs O1 or its output a.
(low level) 4+1 is subtracted from the output 42↓ of the counter 226. The output of the counter 22 is applied to the selector 14 as an n-bit write address, and the output of the subtracter 27 is applied to the selector 14 as m-bit write address data. Therefore, in a memory (not shown), the lower two bits of the write address are specified by the count value of the counter 22, and the upper write address is specified by the output of the subtracter 27.

Next, the specific configuration of the read address designation circuit 30 is the same as that of the subsequent read address designation circuit 20 except that the initial setting circuit 28 is not provided. Therefore, in the illustration, reference numbers in the tens digit are shown in the 30s. When the output a of the control circuit 33 is 1, the subtracter 37 included in the read address designation circuit 30 outputs 3+1 when the output a of the control circuit 33 is 0.
It works to subtract from the direct shown by 36. Is the other configuration a continuous addressing circuit? Since it is the same as 0,
Detailed explanation will be omitted.

Figure 7 shows the goo 1 circuit 21 and control circuit 23 in Figure 6.
FIG. 2 is a detailed circuit diagram of FIG. To explain the specific configuration of the control circuit 23, the Nant gate 231 receives the output a of the counter 22 as an input (when it detects -1 and 3, it outputs 0 and 1).
novel).

The outputs of the NAND games 1 to 231 and the clock WS are input to the OR gate 232, and the output is sent to the D-type flip 70.
The clock input terminal (hereinafter DFF>233) is supplied to the clock input terminal of DFF233.
B is panned. The D input terminal of 0FF233 is 'pl
connected to the power source (V). The output O of the DFF 233 and the output of the Nantes gate 231 are given to the Nantes gate 234.

=17- FIG. 8 shows a time chart of the gate circuit 21 and the control circuit 23. Next, write at [nos designation circuit 20
Prior to explaining the operations of the control circuit 23 and read addressing circuit 30, the operations of the control circuit 23 and the gate circuit 21 will be explained with reference to FIGS. 7 and 8.

At time t1, when the clock WB goes low and becomes novel, the counter 22 and 0FF 233 are reset. Therefore, the output e of the Nant gate 231 and the DFF
The inverted outputs a of both become high level, and the output of the Nantes gate 234 becomes low level. From then on, RI0TSUKW
S is the addition input of the counter 22 via the OR gate 211)
] given to the terminal.

At time t6, the output C of the OR game i-211 falls, the count value of the counter 22 becomes 3, and the output e of the Nant gate 231 becomes low level.

At time t7, the inverted output a of the DFF changes from high level to low level due to the output f of A-1-232. Therefore, the output of the Nantes gate 18-234 becomes high level during the period from time t6 to time t3 when the next clock WB changes, and the output a becomes low level during the period from time t7 to time t3. As a result, ORGAME)-211 outputs the clock WS input during the period from time t1 to time t6. or gate 2
12 is input between time [7 and t3]
Output S.

Therefore, the output of the counter 22 repeatedly counts up from 0 to 3, maintains the count value 3 for two clocks, and then counts down to 0.

FIG. 9 is a time chart for explaining the operation of the write address designating circuit 20.

FIG. 10 is a diagram schematically showing a memory map to which a write address is designated by the write address designation circuit 20 or a read address is designated by the successive address designation circuit 30 of the present invention. In the figure, the horizontal axis shows the address of the lower bit, and the vertical axis shows the upper address.

Circle marks in the figure indicate read address data, and triangular marks indicate write address data.

Next, with reference to FIGS. 6, 9, and 10,
Write address designation circuit 20 according to the time chart in the figure.
Explain the operation.

At time t1, clock WB becomes low level,
The output of the counter 22 becomes low level.

At the same time, the count value for designating the upper address made up of counters 24 and 25 increases by 1, and becomes 7d+1.

At time t8, when the low level clock WS is applied, the value of the counter 25 is loaded into the counter 26. At this time, the subtracted number of the subtracter 28 is O, so -
The included address will be (7d-11°0). Therefore, the data of word Do of the Nth block is from time 18 to t.
In period 2, it is written to address (7d+1.O).

At time t2, the count value of the counter 22 becomes 1 at the rising edge of the clock WS. Therefore, the data of the next word D1 is written to the address (V d→-1,1).

Thereafter, in the same manner, each time the clock WS is applied, the count value of the counter 22 increments by 1, and the addresses of the lower two bits I~ change.

Then, at time +7, the output ah< of the control circuit 23
The address is (
36,3). Therefore, D4. ,ll-4
The data of d is written to address (3d, 3).

At time t9, the clock WS is given as the output d of the circuit 21 and as the subtraction input of the counter 22 and the counter 26. Therefore, when the clock WS changes from low level to high level, the lower address The count value of the counter 26 decreases by 1 and the count value of the counter 26 decreases by 1.
(that is, the upper address is down by d). With this, D5. N-56 data goes to address (2d, 2), D6. If-66 data goes to address (d, 1), D7. The data of N-7d is the address (0
, O) sequentially. In this manner, writing of one block of data is completed during the period from time [1 to time [3]. Note that after time t3 at 21-, the high-order h runt is incremented by 1 (ie, 7d→-2) in the same way as in the above-described operation, and the data of each of the next 10 words is written.

FIG. 11 is a time chart for explaining the operation of the read addressing circuit 30. Next, with reference to FIGS. 6, 10, and 11, the operation of the read address designating circuit 30 will be described along the time chart of FIG.

At time t1, when the clock RB becomes low level, the argument value of the counter 32 becomes O, and the upper read count value constituted by the counters 34 and 35 increases by 1, changing from 0 to 1. Here, if we compare the read-related and write-related addresses, the upper read count value is 0.
At this time, the upper write count value is set to 7d by the initial setting circuit 28. Further, since the clock WB and the clock RB are selected to have the same frequency, when the upper write count i value is between 7d and 11, the upper successive count value becomes 1.

At time t4, the load clock reaches counter 22- 36, counter 36 loads O.

The address specified at this time is (1, O
). Data (jl) when address is (1,0)
Since the data is in a block 7d earlier than the data (Do, N) whose address is <76+1.1), the data DO, N-76 is read from the memory.

At time t5, the 81 value of the counter 32 becomes 1 due to the output d of the goo 1-circuit 31, and the g1 value of the counter 36 increases by 1. The specified address is (d+l, 1).

The data read from the memory is Dl, N-d -6d
(-DI, I"17d). Such operations are repeated until data 03.N-7d is read out.

After time t10, the subtracted number of the subtracter 37 becomes 3d+1 due to the output 'jJa of the control circuit 33. Therefore, the address becomes (0, button and □), and the data of D4.N-7d is read from the memory.

At time [5], only the counter 32 goes down by 1, and the address becomes (0, 2>.
) 05. N-7d data are read from memory. Thereafter, in the same manner, each time the clock R8 is applied, the value of the counter 32 decreases by 1 until D6.
Data of N-7d and data of 07.11-7d are read out sequentially.

At time t12, reading of 8 words of the N-di-th error correction block is completed.

FIG. 12 is a time chart for explaining the operation of the selector 14. FIG. 12 shows a case where the selector 14 selectively switches between the successive address and the write address and supplies the selected address to the memory in response to the select signal applied to the input terminal 11f.

For example, for a platform whose select signal is at a high level, a write address is selected and applied to the memory via the output terminal 11o. On the other hand, when the select signal is low level,
The read address is selected and output terminal 11 (χ
given to memory. In this way, the clock WB and the clock RB have a cycle of 1iYJ-, and the upper count is calculated by those who talk about the block modification history that requires 1 degree of writing or reading by time division within one block. By incrementing the value and cycling through the 7 addresses (memory specification),
Dinterleaving can be performed continuously.

Note that the specified memory address value when write at 1 no. is selected and when read address is selected is as follows.
Since the beating can be easily carried out by referring to FIG. 12, detailed explanation thereof will be omitted.

By the way, in the above embodiment, the counters 22 and 32
We have explained the case where you want to avoid starting from 0 or 1, but if you want to start from 3, you can configure it as follows. That is, firstly, by replacing the up input and down input of the counters 22 and 32, and secondly, by using an OR gate that detects 0 in place of the NAND game 1 that detects 3 included in the control circuit 23.32. , dinterleave can be performed. In the case of interleaving, the counter 26 is replaced with an up counter, the counter 36 is replaced with a down counter, the initial settings are set to 0 and 25-, the number of subtractions of the subtracter 27 is set to 15d+1, and the subtracter 37 is set to 0 and 25-.
This can be realized by setting the number of subtractions to 166.

As described above, according to the present invention, interleaving can be performed with a memory capacity of 4 (7d + 2) bits per word (about half of the conventional one) compared to the conventional one, and the device can be manufactured at a lower cost. There are effects such as being able to. The effects of the present invention become even more remarkable in the case of a configuration in which the signal processing section is implemented as an LSI and the memory is externally attached.

[Brief explanation of the drawing]

FIG. 1 is an illustrative diagram of a data format for explaining interleaving and gain interleaving, which are the background of this invention. FIG. 2 is a block diagram of a conventional memory addressing circuit. FIG. 3 is a time chart for explaining the write operation of the circuit of FIG. 2. Figure 4 is the second
3 is a time chart for explaining a read operation of the circuit shown in the figure. FIG. 5 is a diagram schematically showing a memory map of a conventional memory addressing circuit. FIG. 6 is a circuit diagram of a memory addressing device according to an embodiment of the 26-1 invention. FIG. 7 is a detailed circuit diagram of the Goo 1 circuit and control circuit. FIG. 8 is a time chart starting from t1-1 for explaining the operation of FIG. 7. FIG. 9 is a time chart 1 to explain the write operation of the circuit of FIG. 6. FIG. 10 is a diagram schematically showing a memory map applied to the present invention. FIG. 11 is a time chart for explaining the read operation of the circuit of FIG. 6. FIG. 12 is a time chart for explaining the operation of the selector. In the figure, 10 is a conventional memory addressing device;
0 is a read address designation circuit, 30 is a write address designation circuit, 21.31 is a gate circuit, 22.24 to 26, 32
．． 34 to 36 are counters, 23.33 is a control circuit, 27
．． 37 is a subtracter, 28 is an initial setting circuit, and 14 is a selector. Agent Nobu Kuzuno - (1 other person) 27- Jyo-626- VnC (Ko- ≧ ≧ Showa year month/day Mr. Commissioner of the Japan Patent Office 1, Indication of case Patent application No. 108207/1989 2
, Name of the invention Memory addressing method and apparatus 3, Person making the amendment (1) 6. Full text of the specification to be amended and drawings 7, Contents of the amendment (1) Memory addressability of the name of the invention in the specification
``Souch-less specified device'' is set to ``Memory Address City''.
How to specify the method and its method! ! I will correct it to @J. (2) The entire statement will be corrected as shown in the attached document. (3) Figures 1 to 12 of the drawings will be corrected as shown in the attached sheet. (4) Figures 13 to 22 of the drawings will be added as attached. Above 2 - Full text corrected specification 1, Title of invention Memory addressing method and device 2, Claims method, including the step of inputting LLI'i'-B by LLI'i'-B, and the method for determining. 5-- Method. Yes, 3- Many fixed methods. 4- I'm sure it's only 1.
L knee and designated device. (14) The predetermined integer values B, E, and F are positive values, and constant! fil! . (15) The predetermined integer values B, D and G are positive values, and 11I! ! ! − is at the end of , is , and is the designated device. 3. Detailed Description of the Invention The present invention relates to a memory addressing method and device, and particularly to a memory addressing method and device when data is interleaved or dinterleaved in blocks using a memory. Regarding. Recently, PCM recorders and PCM audio discs have
Error correction codes are used to obtain high quality reproduced sound. The error correction method using this error correction code divides the word string of the sampled signal obtained by sampling the analog signal into blocks of multiple words or multiple frames, and adds an error correction word to each block to correct one error. This is a method in which correction blocks are configured to correct words that are erroneous on the transmission path during reproduction. However, such an error correction method has a limit, and when most of the words in one error correction block are erroneous due to burst errors occurring on the transmission path, correction becomes impossible. Conventionally, as a countermeasure against burst errors, an interleaving method is used to disperse each word in an error correction block during recording, and each word is recorded at a certain interval on the recording medium, and when reproduced, it is returned to the original arrangement 8-. Error correction was performed by performing dinterleaving. FIG. 1 is an illustrative diagram of a data format for explaining interleave and dinterleave processing that is the basis of the present invention. In the illustration, one frame is one block, and one block is divided. An error correction block consisting of 8 words of ~D7 is shown. In this case, group 1 is the Nth word consisting of 8 words Do to D7, which are sampled signal words and error correction codes added.
Indicates the th error correction block. For example, the word Do
-D5 is data and words D6 and D7 are error correction codes. However, N is an integer. Group 2 is 1
It shows the amount of delay of each word Do, DI, D2-D7 in the block, which is defined as Q, d, 2d-7d. However, d indicates an integer unit delay amount, and is selected, for example, as the data transmission time of one word. In the following explanation,
- As an example, it is d-16. During interleaving, each word Do-D7 in the coblock is delayed by a delay amount corresponding to each word. Group 3 shows the word structure of one block after interleaving. After the interleaving process, each block consists of the words that were in different numbered error correction blocks and is recorded on a recording medium such as a vinyl record. Group 4 shows the amount of delay for each word when interleaved data is dinterleaved as described above. The amount of delay during dinterleaving is selected to be inversely proportional to the amount of delay during interleaving. For example, if the amount of delay during interleaving is selected to be O, d to 7d for words Do and D1 to D7, respectively, the amount of delay during dinterleaving is selected to be 7d and 6d -0, respectively. Group 5 shows the format of one error correction block after gain interleaving processing is performed. As is clear from the diagram, each word Do to D7 is all equal to the word of the N, -7d-th error correction 1° block, and the combinations before interleaving are returned to, except that there is a delay amount of 7d. Become. When interleaving processing and dinterleaving processing as shown in Fig. 1 are performed, a burst error occurs on the transmission path, and an error of the length of 8 words of the block shown in group 3 occurs. However, since the erroneous words are dispersed by performing the dinterleaving process, there is only one error in one word within one block obtained by the dinterleaving process, and correction is possible. In order to realize such interleave and gain interleave processing (second), a method is used in which one block of word data is temporarily stored in a memory and each word is read out in a predetermined order. Memory address control when performing interleaving will be explained. First, the case of performing dinterleaving will be explained. Figure 2 is a block diagram of a conventional memory addressing device when performing dinterleaving processing. In the figure, the addressing device w110 includes a write address designating circuit 101 and a read address designating circuit 102.The specific configuration of the addressing device 10 will be described below.Input terminal 11a is given a write sample clock WS (hereinafter referred to as I-k WS). This clock WS is
2 is applied to the addition input terminal UP. The counter 12 is
It has a 3-bit output, performs an addition operation every time the clock WS is applied, and derives the value of the digits of A as write address data corresponding to a word within one block. Input terminal 1
1b is given a write block change clock WB (hereinafter referred to as "cock WB"). This clock WB is applied to the reset terminal R of the counter 12 and also to the addition input terminal UP of the counter 13. The outputs of these counters 12 and 13 cause memory 40
The write address of is determined. Zunawara, counter 12
The output is given to the selector 14 by a write address control bit ( ) that specifies the lower 3 bits of the memory 40. The output of the counter 13 is given to the selector 1412- as write address data specifying the upper address of the memory 40. A continuous sample clock R8 (hereinafter referred to as clock R8) is applied to the input terminal 11G. This clock R8 corresponds to 8 words within one error correction block. The lock R8 is applied to the addition input terminal UP of the counter 15 and also to the addition input terminal UP of the counter 16. The counter 15 has a 3-bit output, performs an addition operation every time the clock R8 is applied, and is reset by the clock RB input to the input terminal 11d. Clock RB is a successive block change clock, and is applied one clock at a time as the error correction block number advances. This clock RB is applied to the addition input terminal UP of the counter 17. counter 1
7 has a 4-bit output, and provides a carry output from the carry output terminal OA to the addition input terminal UP of the counter 18. Counter 18 provides its count value as a parallel load input to counter 16. The counter 16 receives the load clock LD applied to the input terminal 11e. The next address in the memory 40 is determined by the outputs of these counters 15-17. That is, the output of the counter 15 is derived as read address data specifying the address of the lower 3 bits. counters 16 and 1
The output of 7 is derived as successive address data specifying an upper address in the memory. These read address data are given to the selector 14. The selector 14 switches and derives a write address or a subsequent address in response to a select signal SL applied to an input terminal 111'. The write address data or read address data selected by the selector 14 is derived from the output terminal 11g as memory address data and is applied to the memory 40. The outputs of counters 17 and 18 are input to initial setting circuit 19 . This initial setting circuit 19 has a counter 17
And when the value determined by the output of 1゛8 is O, the counter 1
It generates an output that sets the count value of 3 to 7d. Before explaining in detail the operation of the addressing device shown in FIG. 2, its general operation will be explained using FIG. Figure 3 shows 1 in 1 word when performing dinterleaving.
FIG. 2 is a diagram schematically showing a memory map per bit. The upper address value is selected as the row address, and the lower 3 bit address value is selected as the column address. Triangular marks indicate write data, and circles indicate read data. Data is written while keeping the row address at a predetermined value.
This is done by changing the column address from 0 to 7 in increments of 1. The same thing is done while updating the row addresses one by one. In the figure, data (D
o, N), (Dl, N-d), (D2.N-2d)
, (03,N-3d), (D4.N-46), (D5
．． N-56). The case where (D6.N-66) and (D7.N-76) are written in order is shown. Data is read by changing the column address from 0 to 7 by 1 each time d is added to the row address obtained by subtracting 7d from the address at the time of writing. The same procedure as in step 15 is performed while updating the row addresses one by one. In the figure, addresses (0,1), (6,1). (2d, 2), (36, 3), (46, 4). Data of (5d, 5), (6d, 6), 15 and (76,7) (Do, 7-76), (Dl, N-7d),
(D2.N-7d), (D3.N-7d). (D4.N-76), (D5.N-76), (D6,N
-76) and (D7.N-7d) are read out in sequence. This read data has been dinterleaved. Now, the operation of the addressing device shown in FIG. 2 will be explained in detail with reference to FIGS. 3 to 5. FIG. 4 is a time chart for explaining the operation of the -include address designation circuit 101. FIG. 5 shows the read address designation circuit 10.
2 is a time chart for explaining the operation of No. 2. First, the operation of the write address designation circuit 101 will be explained mainly along the time chart of FIG. In the illustrated example, 8 out of 1 transmission block (group 3 shown in FIG. 1)
A case is shown in which a word is written with the upper address constant at -16 and the lower address changed from O to 7, and the next block is written with the upper address advanced by 1 by the clock WB. At time t1, the counter 12 is activated by the clock WB.
is reset and the counter 13 is incremented by one. Therefore, as soon as the output 0UT12 of the counter 12 becomes 0, the output 0LIT13 of the counter 13 changes from the previous value, for example, 7d-1 to 7d. At time t2, the counter 12 increments its count value by 1 and outputs 1 when the clock WS is applied. At this time, among the write data WDATA, data of the first word (Do, N) in the N1-th block is written to the memory during the period from time t1 to time t2. The address is (m, n) where the upper address value is m and the lower address value is n, and if 1 is 1, then
Since 1a7d of the output 0UT13 of the counter 13 becomes the upper address value m, and the output O of the counter 12 becomes the lower address value n, the address is (7d, O). The data of the next word <Dl, If-d) is stored at the address (
7d, 1). Thereafter, in the same way, the address of the lower 3 bits is incremented by 1 for each word, and the output of counter 13 is 0UT13 and the output of counter 12 is 0UT.
The data of words D2 to D7 are written to the write address determined by 12 and 12. Then, at time t3, when writing of 8 words of data is completed, a clock WB is applied. Therefore, the count value of the counter 13 is incremented by 1,
The upper address m becomes 7d+1, and the data of each word in the next N111th block is sequentially written. In addition,
Actually, in this case, the count value of the counter 13 reaches the upper limit, the callan 1 to value circulates to O, and the upper address I also goes to 0.
touring. Next, the operation of the read address designation circuit 102 will be explained mainly along the time chart of FIG. When clock RB is input at time &1Jt1,
Counter 15 is reset and its output 0U15 becomes O. As a result, the lower succeeding address becomes 0. On the other hand, at this time, the counter 13 is set to 7 by the initial setting circuit 19.
The value d is initialized and the read address designation circuit 10
The upper address of 1 is set to lag behind that of the write address designation circuit 102 by 7d. Therefore, when the upper address of the write address designation circuit 101 is 7d, the count value of the counter 17 and the counter 18
The upper read count value URCV is composed of the count value of
is 0. That is, the initial setting circuit 19 is provided to prevent the write address and read address of the memory from colliding. If there is no initial setting circuit 19, both write and successive addresses will start from random addresses when the power is turned on.
The combination of read data is not legal. Once the initial value 7d is set in the initial setting circuit 19, if the frame frequencies of writing and successive writing are the same, both the writing and successive writing addresses circulate through the memory while maintaining a constant relationship. At time t4, when the load clock LD is applied to the input=19-terminal 11e, O is loaded into the counter 16. As a result, the upper address m becomes O, and as a result, the subsequent address becomes (0, 0). At this time, data (Do, N) is output from the memory 40 as shown in FIG.
The data (D
o, N-7d) are read out. At time t5, when the clock R8 is applied, the output 0UT15 of the counter 15 becomes 1. At the same time, the counter 16 is incremented by one. This corresponds to the higher succeeding address m being incremented by d. Therefore, the memory read address is (6,
1) Roar, Data (Dl, N-d-66) ” (D
1, N-7d) is read from the grid 40.
゜Thereafter, in the same manner, the C1 values of counters 15 and 16 are incremented by 1 by clock R8, and the data stored in the address specified by the two-hand value is read out, and finally the data shown in Fig. 1 is obtained. No. N-7d shown in group 5 of
It is possible to obtain a word array for the th error correction block 20-. Gain interleaving can be performed continuously by synchronizing the write system and the continuous output system and synchronizing the clock phases so that the data of word D7 is written and then read. It will be done. In the example of FIG. 1, the data of the block shown in group 3 is sent to the upper address 7.
After writing to D, write the data of the next block to the upper address 0, and after reading the data (D7.N-76) of the read address (76, 7), write the data of the next block to the first word of the next error correction block. By starting to read the data (Do, N-76+1) from address (1,0), it is possible to perform dinterleaving by cycling through the memory to 8x (7d 11) pins per 1 bit in the word. I can (8
corresponds to the number of lower addresses, and 7d+1 corresponds to the number of upper addresses. See Figure 3. ). The memory address control when performing dinterleave has been described above. Memory address control when performing interleaving will also be easily understood from the above explanation, but for clarity, it will be briefly explained below. Figure 6 shows 1 in the 19th code when performing interleaving.
FIG. 2 is a diagram schematically showing a memory map per bit. The differences from FIG. 3 will be mainly explained. Writing data is
While keeping the row address at a predetermined value, change the column address from O to 7.
This is done by changing the value by 1. The same thing is done while updating the row addresses one by one. They are similar to those of dinterleaves. In the figure, data (Do, N), (DI.N), (02,N), (D3.N), (D4.N), (
D5. The case where N>, (D6.N) and (D7.N) are written in order is not shown. Data is read by changing the column address from 0 to 7 by 1 each time d is subtracted from the row address at the time of writing. The same thing is done while updating the row addresses one by one. In the figure, addresses (7d, O)', (6d, 1), (5d
, 2>, (4d, 3). (36,4), (2d,5), (d,6) and (0,
7), the data (Do
, N), (01,N-d), (D2゜N-2d>,
(D3.N-36), (D4.N-46), (05,N
-56), (D6.N-66) and (D7.N-76
) are read out in order. As described above, the delay amounts shown in group 2 in FIG. 1 are obtained, and interleaving is performed. In order to perform the above interleaving using the addressing device shown in FIG. 2, it is only necessary to change the counter 16 to a down counter. Accordingly, for details of the operation of the addressing device of FIG. 2 when interleaving, taking into account the above changes, reference is again made to FIGS. 4 and 5 and their associated descriptions. However, when performing interleaving or dinterleaving as shown in FIG.
28d bits, whereas when using the conventional addressing device shown in FIG. 2, -23 = 8x (7d +1 > A memory capacity of bits was required.In other words, it required a memory capacity that was approximately twice the memory capacity that was truly required, which was uneconomical.Therefore, the memory capacity was close to the memory capacity that was truly required. There is a need for a method and apparatus for addressing a memory that can perform interleaving and gain interleaving with a An object of the present invention is to provide a memory addressing method and device capable of performing interleaving and dinterleaving with a memory capacity close to that of a memory capacity. The method is folded back in the memory, so to speak. An embodiment of the present invention will be described below with reference to the drawings. Fig. 7 is a block 24 diagram showing an embodiment of the present invention. Briefly speaking, this embodiment consists of a write address designation circuit 20 that designates an address when writing data to the memory 40, and an initialization circuit that is connected to the write address designation circuit 20 and provides an initial read row address. 50
．． The memory 40 is connected to the initial setting circuit 50 .
a selector 14 which is connected to a read address designation circuit 30, an input address designation circuit 20, and a subsequent address designation circuit 30, which designates an address when data is not read from the memory 40; Equipped with The write address designating circuit 20 uses a first addressing means for adding a column address by a predetermined integer value B while keeping the row address at a predetermined positive integer value A. When the first column address reaches a predetermined positive integer value C, a second addressing means for subtracting the row address by a predetermined integer value in response to the subtracting the row address by a predetermined integer value (1);
A third addressing means for subtracting by illB is provided. The successive address specifying means 30 adds the predetermined integer WiE to the initial read row address, and in step with this, also adds the column address to the predetermined integer 1ilI.
A fourth addressing means for adding up the row address by a predetermined integer value G in response to the one column address reaching the predetermined integer value C; A sixth addressing means is provided for subtracting the column address by the predetermined integer value B while maintaining the integer value H. Next, the detailed configuration and operation of the addressing device shown in FIG. 7 will be explained. FIG. 7 is a block diagram when dinterleaving is performed, as in the case of FIG. 2 (the case where interleaving is performed will be explained later). The write address designation circuit 20 includes a gate circuit 21.degree. counter 22. Control circuit 23. It includes counters 24 to 26 and a subtracter 27. The gate circuit 21 receives the clock WS and the outputs A and B of the control circuit 23 as input. This gate circuit 21 is composed of two OR gates 211 and 212 as shown later in FIG. The counter 22 is an up/down counter having a 2-bit output, and one output C of the gate circuit 21 is applied to an addition input terminal UP, and the other output is applied to a subtraction input terminal ON. A clock WB is input to the reset terminal R of the counter 22. The counter 24 is a 4-bit counter,
It is stepped by the clock WB and initialized by the initial setting circuit 50. The counter 25 receives the carry output of the counter 24 as an input, and is preset by the output j of the initial setting circuit 50. In the counter 26, the output of the gate circuit 21 is given to the subtraction input terminal DN, and the counter 26 receives the output from the gate circuit 21 as a parallel load input.
5 outputs are given. The counter 26 loads the output of the counter 25 every time a write load clock (hereinafter referred to as clock WL) input via the input terminal 11 is given. is 1' (high level)
Notogi O or its output A is 'O' (low level)
When 4d+1 is output from counter 24 and counter 2
6 and the output 27-. The output of this counter 22 is given to the selector 14 as an n-bit write address, and the output of the subtracter 27 is given to the selector 14 as m-bit write address data. Therefore, in the memory 40, the lower two bits of the write address are specified by the count value of the counter 22, and the upper write address is specified by the output of the subtracter 27. The read address designation circuit 30 is the write address designation circuit 2.
It has the same configuration as 0, and the circuit 31° counter 3
2. Control circuit 33. Counters 34-36 and subtractor 3
Equipped with 7. The subtracter 37 is configured so that the output A of the control circuit 33 is 1.
When the output A is O'', O is subtracted, and when the output A is O'', 3d+1 is subtracted from the value composed of the output of the counter 34 and the output of the counter 36.Other than that, the configuration is the same as the successive addressing circuit 20. Therefore, a detailed explanation will be omitted. Before giving a detailed explanation of the operations of the write address designation circuit 20 and the successive address designation circuit 30, the following will be explained. 8 is a detailed circuit diagram of the gate circuit 21 and control circuit 23 shown in FIG. 7.The specific structure of the control circuit 23 will be explained below. The Nant gate 231 receives the output 0UT22 of the counter 22 as an input, and outputs II O11 (low level) when 3 (that is, 11 in binary) is input. The output of F and the clock WS are input, and the output F
is a D-type flip-flop (hereinafter referred to as OFF) 233
Give it below the clock input terminal. The clock WB is input to the reset input terminal R of the DFF 233. 0FF
The input terminal of 233 is connected to the power supply V. DFF23
The inverted output A from the inverted output terminal 0 of No. 3 and the output E from the Nantes gate 231 are given to the Nantes gate 234. The operations of the gate circuit 21 and the control circuit 23 will be explained with reference to FIGS. 8 and 9. Figure 9 shows the gate circuit 21
and a time chart for explaining the operation of the control circuit 23. At time t1, when the clock WB becomes low level, the counter 22 and the DFF 233 are reset. For this reason, the output E and DFF of Nando games 1 to 231
Both the inverted outputs A of the NAND game h 233 become high level, and the output B of the NAND game h 234 becomes low level. Thereafter, the clock WS is applied to the addition input terminal UP of the counter 22 via the ORG-i-211. At time t6, the output C of the OR gate 211 falls, the output 0UT22 of the counter 22 becomes 3, and the output F of the Nant gate 231 becomes low level. At time t7, the output F of the OR gate 232 causes the inverted output A of the DFF 233 to change from high level to low level. Therefore, the output B of the Nant gate 234
is the time t3 when the next clock WB changes from time t6
The output A of DFF233 remains high during the period up to
is at a low level during the period from time t7 to time t3. As a result, the OR gate 211 operates from time t1 to t.
The clock WS input during period 6 is output. OR gate 212 outputs clock WS input between times t7 and t3. Therefore, the counter 22 does not repeat the operation of counting up the output 0UT22 from 0 to 3, maintaining the count value 3 for two clocks, and then counting down to 0. FIG. 10 is a block diagram showing the subtracter 27. The subtracter 27 includes a 4-bit adder 271, a 4-bit adder 272, and a complement setter 273. The output 0UT24 of the counter 24 is input to the adder 271, and the output 0UT26 of the counter 26 is input to the adder 272. Output 0UT2 of counters 271 and 272
7 is given to the selector 14 as m-bit address data. The complement setter 273 sets the complement [4d+11] of 1II4d+1 to be subtracted in the subtracter 27, outputs O when the output A of the control circuit 23 is 1'', and outputs the complement [4d+11] when the output A of the control circuit 23 is O''. →-1] is output. Adders 271 and 272 add O or the complement [4d+1] to the value formed by the output 0UT24 of the counter 24 and the output 0UT26 of the counter 26. However, since memory addresses are circulated, if the result of addition is a carry, the carry is ignored. Therefore, the subtracter 27 outputs O when the output A of the control circuit 23 is 1p,
When the output A is O'', the output of the counter 24 is 0.
It is subtracted from the value formed by UT24 and the output 0UT26 of counter 26. Note that the subtracter 33 is similar to the subtracter 27 except that the value to be subtracted is 3d+1. FIG. 11 is a block diagram showing the initial setting circuit 50. The initial setting circuit 50 includes a 0 detection circuit 51, an AND gate 52, and an inverter 53. The 0 detection circuit 51 is composed of, for example, a Nant gate having an m-bit input terminal. The O detection circuit 51 includes
The spear of 32-pi1- consisting of the output 0UT34 of the counter 34 and the output 0UT35 of the counter 35 is input. The O detection circuit 51 outputs 1'' to the AND gate 52 when the human power is O.The clock RB (negative logic) is input to the inverter 53, and the clock RB whose polarity is inverted is input to the AND gate 52. 1 to 52. Therefore, counter 3
4 output 0LIT34 and counter 35 output 0UT
When the clock RB is inputted when the value consisting of 35 is 0, the AND gate 52 outputs 1''. A value consisting of the output of the counter 24 and the output of the counter 25 is forcibly initialized to 7d.Before explaining the operation of the addressing device shown in FIG. Figure 12 is a diagram schematically showing a memory map per bit in one word when performing dinterleaving.The upper address is selected as the row address. ,
The lower two bits of the address are selected as the column address. The major difference from FIG. 3 is that the column address is 2 bits. The square mark indicates the written data, and the round mark indicates the read data. Data writing is performed in the next step. First, while keeping the row address at a predetermined value, for example 7d+1, the column address is changed from 0 to 3 by 1. In the figure, data (
DO, N). (Di, N-d), (02, N-2d) and (D
a, N-36) are written in order. Next, when the column address reaches 3, change the row address to 4d.
Subtract +1. Thereafter, the row address is subtracted by d, and in keeping with this, the column address is also subtracted from 3 to O by 1. In the figure, address (3d, 3)
, (2d. 2), (6,1) and (0,0) with data (D4,N
-4d >, (D5.N-5d), (06°N-66
) and (D7.N-7d) are respectively written in order. The same thing as above is performed while updating the row addresses one by one. Data reading is performed in the next step. First, each time d is added to the row address obtained by subtracting 7d from the row address at the time of writing, the column address is changed by 1 from 0 to 3. In the figure, addresses (1,0), (d+1.1
), (2d+1.2) and (3d +1.3) data (Do, N-7d ), (Dl, N-76), (D2
．． The case where N-7d) and (Da, N-76) are read out in sequence is shown. Next, when the column address reaches 3, the row address is subtracted by 3d+1. Thereafter, while keeping the row address at O, the column address is subtracted from 3 to O by 1. In the figure, addresses (0,3), (0°2), (0,1)
and (0,0) data (D4, N-76),
(D5.N-76>, (Da.N-7d) and (D7.N-76) are read out in order. The same thing as above is done while updating the row address one by one. As a result, the delay amount shown in group 4 in FIG. 1 is obtained, and dinterleaving is performed. Now, the operation of the addressing device shown in FIG.
This will be explained in detail with reference to FIGS. 15 to 15. 35- FIG. 13 is a time chart for explaining the operation of the write address designation circuit 20. FIG. 14 is a time chart for explaining the operation of the read addressing circuit 30. FIG. 15 is a time chart for explaining the operation of the selector 14. First, the operation of the write address designation circuit 20 will be explained mainly along the time chart of FIG. At time t1, when the clock WB becomes low level, the output 0UT22 of the counter 22 becomes O. At the same time, a high-order count muw that specifies the high-order address l consisting of the output of the counter 24 and the output of the counter 25 is used.
cv is increased by 1. As a result, the upper count value uwcv changes from the previous value, for example 7d to 7d+
Changes to 1. At time t8, when the low level clock WL is applied, the value of the counter 25 is loaded into the counter 26. At this time, the output A of the control circuit 23 is 1'' (
9), the number of subtractions by the subtractor 236-7 is O, so the write address is (7d do 1).
,0) yell. Therefore, among the write data WDAT, the data of the word (Do, N) in the N1-th block is transferred to the address (7d+1) during the period from time t8 to E2.
．． 0). At time t2, when the clock WS rises, the count value of the C counter 22 becomes 1. Therefore, the next word (D
I, N-d) data is written to address (7d+1.1). Thereafter, in the same manner, each time the clock WS is applied, the count value of the counter 22 increments by 1, and the address of the lower two bits changes. Then, at time t7, the output of the counter 22 is 0LI.
T22 becomes 3. Then, as explained with reference to FIG. 9, the output of the control circuit 23 becomes "0" and the subtraction number of the subtracter 27 becomes 4d+1, so the address changes to (3d, 3). Therefore, the data of word (D4.N-/ld) is written to address (3d, 3). At time t9, the clock WS is activated by the gate circuit 210.
The output signal is applied to the subtraction input terminals DN of the counters 22 and 26. Therefore, when the clock WS changes from low level to high level, the counter 22
The output 0tJT22 goes down by 1, the lower address goes down by 1, and the count value of the counter 26 also goes down by 1.
(i.e., the upper address... is down by d)
do. As a result, data of word (D5.N-5d) is written to address (2d, 2). From then on, word <I)6. N-6 (1> data is address (
The data of the word (D7.If-7d) is sequentially written to the address (0,0). In this way, one block of data writing is completed during the period from time t1 to time t3. Note that after time t3, the upper count value uwcv increases by 1 in the same manner as in the above-mentioned operation, and the data of each word of the next block is written. , in this case, the values of the counters 24 and 25 reach their upper limits, and the upper curns 1 to uwcv cycle to 0. Next, the operation of the read address designating circuit 30 is performed mainly along the time chart of FIG. At time t1, when the clock RB becomes low level, the counter 32 is reset and its output 0LJT32 becomes O. At the same time, the counter 34
The upper read count value IJRcV, which is composed of the output of
Changes to Here, when comparing the upper address m of the successive address designation circuit 20 and the write address designation circuit 30,
When the upper successive count value URCV is O, the upper write count value tJWCV is set to 7d by the initial setting circuit 50.
(see FIG. 11 and its explanation). In addition, since the clock WB and the clock RB are distributed at the same frequency, the upper write count value LI
When WCV is 7d+1, upper read count (iltJ
RcV becomes 1. That is, the initial setting circuit 50 is for preventing the write address of the memory from colliding with the subsequent address 39-. If the initial setting circuit 50 were not present, both write and read addresses would start from random addresses when the power is turned on, and the subsequent data combinations would not be normal. Once the initial value 7d is set in the initial setting circuit 50, if the writing and subsequent frame frequencies are the same,
Both write and read addresses circulate through the memory while maintaining a constant relationship. At time t4, the load clock LD reaches counter 3.
6, counter 36 loads the output of counter 35 with 0. At this time, the output A of the control circuit 33 is 1'', and the subtraction of the subtracter 37 is O, so the specified address is (1, 0).
, 0), the address is (7d+1.0)
Since the data is from a block 7d U before the data ([)O,N), the output data RDA from the memory 40
TA becomes data of word (Do, N-76). At time t5, the output 0UT32 of the counter 32 becomes 1 due to the output C of the gate circuit 31, and the count value of the counter 36 increases by 1. That is, the upper address m is increased by d. The address specified at this time is (d+1.1). Therefore, the data read from memory 40 is word (D 1 , N - d - 6d ) - (Dl,
N-76) data. This kind of behavior is the word (
D3. This process is repeated until 1-76) is read out. After time t10, the output A of the control circuit 33 becomes "O11," so that the subtractor of the subtracter 37 becomes 3d+1. Therefore, the address becomes (0, 3) and the word (D
4. N-76) data is read from the memory. At time t11, only the counter 32 decrements by 1, and the address becomes 4 (0, 2>).
The data of the word (D5°N-76) specified by 2) is read out to the memory. Thereafter, in the same manner, the clock R3
is given, the value of the counter 32 is incremented by 1, and the data of word (D6.N-7d> and the data of word (D7.N-7d>) are sequentially read out. At time t12, Reading of 8 words of the N-7d-th error correction block is completed. Fig. 15 is a time chart 1 to explain the operation of the selector 14. The select signal S L applied to the input terminal 11f causes the selector to 14 is the write address W
AD and the subsequent address RAD are selectively switched and provided to the memory 40. For example, when the select signal SL is at a high level, the write address WAD is selected and provided to the memory 40 via the output terminal 11fll as the memory designated address SAD. On the other hand, the deflector signal S
When L is at a low level, the read address RAD is selected and output from the output terminal 11 as the designated address SAD of the memory.
(Given to the memory 40 via +.Write address W
The designated address SAD of the memory when AD is selected and when the subsequent address RAD is selected can be easily understood by referring to FIG. 15, so a detailed explanation thereof will be omitted. As shown in FIG. 15, clock WB and clock RB have the same period, clock WS and clock R3 have the same period, and write address WAD and read address RAD are sent to select 1 by signal SL.
By switching, dinterleaving can be performed continuously. Note that when performing dinterleaving, the memory addressing method is not limited to the one described above. Other methods of specifying Atoshinos will be explained below. FIGS. 16 to 18 are diagrams schematically showing memory maps when other addressing methods are used when performing dinterleaving. Triangular marks indicate in-store data, and circles indicate read data. In the case of FIG. 16, data writing is performed in the next step. First, while keeping the row address at a predetermined value, for example 7d+1, the column address is changed from 3 to O one by one. next,
When the column address reaches O, the row address is decreased by 46+1]. After that, the row address is subtracted by d, and the step=43- is added to it, and the column address is added from O to 3 by 1. The same thing as above is performed while updating the row addresses one by one. Successive output of data is performed in the next step. First, d is added to the row address obtained by subtracting 7d from the row address at the time of writing, and in step with this, the column At 1 No is changed from 33 to O by 1. Next, when the column address reaches O, the row address is subtracted by 3d+1. Thereafter, while keeping the row address at O, the column addresses are added from 0 to 3 one by one. The same thing as above is performed while updating the row addresses one by one. In order to carry out the addressing method described above using the addressing device shown in FIG. 7, the following minor changes may be made to it. (1) Addition input terminal LIP of counters 22 and 32
and subtraction input terminal ON. (2) Reset terminals R of counters 22 and 32 are not required, and both counters are connected to clock WBIB.
and set 3 by R8. (3) An A agate that detects O is used in place of the Nant gate that detects 3 included in the i control circuits 23 and 33. In the case of FIG. 17, data writing is performed in the next step. First, the row address is decreased by d from 7d to 11 (and at the same time, the column address is added from O to 3 by 1. Next, when the column address reaches 3, 3d+1 is added to the row address. .Then the row address is 7d+
While keeping it at 1, change the column address from 3 to O by 1. The same thing as above is performed while updating the row addresses one by one. Data reading is performed in the next step. First, while keeping the row address at O, the column address is changed from O to 3 by one. Next, when the column address reaches 3, 4d+1 is added to the row address. Thereafter, the row address is added by d, and in step with this, the column address is subtracted from 3 to O by 1. The same thing as above is performed while updating the row addresses one by one. In order to carry out the addressing method described above using the addressing device shown in FIG. 7, the following minor changes may be made to it. (4) Input the output C of the gate circuit 21 to the subtraction input terminal DN of the counter 26. (5) Input the output of the gate circuit 31 to the addition input terminal UP of the counter 36. In the case of FIG. 18, data writing is performed in the next step. First, the row address is subtracted by d from 7d, and at the same time, the column address is decreased from 3 to O by 1 fiI!1'.Next, when the column address reaches 0, the row address is decreased by 3d+1. Then, while keeping the row address at 7d+1, change the column address from 0 to 3 by 1. Do the same thing as above while updating the row address by 1. Reading data is the next step. First, while keeping the row address at O, change the column address from 3 to 0 by 1. Next, when the column address reaches O, add 4d+1 to the row address. After that, change the row address to At the same time as adding d!r, the column address is added from 0 to 3 by 1 at the same pace.The same thing as above is done while updating the row address by 1.The above addressing method is used. In order to perform this using the addressing device shown in FIG.
Just make the change in (5). The memory address control when performing dinterleaving has been described above in detail. Memory address control when performing interleaving will be easily understood from the explanation below, but for clarity, it will be briefly explained below. FIGS. 19 to 22 are diagrams schematically showing memory maps when interleaving is performed. Triangular marks indicate write data, and circles indicate read data. In the case of FIG. 19, data writing is performed in the next step. First, while keeping the row address at 7d+1, the column address is changed from O to 3 by 1. Then, when the column address reaches 3, change the row address to 3d+
Subtract 1. After that, the row address is added by d, and the column address is increased from 3 to 0 at the same time.
Subtract one by one. The same 47= as above is performed while updating the row addresses one by one. Data reading is performed in the next step. First, each time d is subtracted from the row address 7d+1 during writing, the column address is changed by 1 from 0 to 3 in step with it. Next, when the column at 1 nos reaches 3, change the row address to 4d
Subtract +1. Thereafter, while keeping the row address at O, the column address is subtracted from 3 to 0 by 1. The same thing as above is performed while updating the row addresses one by one. As a result of the above, the spread amount shown in group 2 in FIG. 1 is obtained, and interleaving is performed. In order to carry out the above addressing method using the addressing device shown in FIG. 7, the following minor changes may be made to it. For details of its operation, please refer back to the above description, taking into account the changes. (1) Change the subtraction input terminal DN of the counter 26 to the addition input terminal UP. (2) Change the addition input terminal UP of the counter 32 to the subtraction input terminal DN. 48- In the case of FIG. 20, data writing is performed in the next step. First, while keeping the row address at 76+1, the column address is changed from 3 to O by 1. Next, when the column address reaches O, change the row address to 3d→
-1 is subtracted. Thereafter, the row address is added by d, and in step with this, the column address is added from O to 3 by 1. The same thing as above is performed while updating the row addresses one by one. Data reading is performed in the next step. First, every time d is subtracted from the row address 7d+1 at the time of writing, the column address is also changed from 3 to 0 at the same pace.
change by 1. Next, when the column address reaches O, the row address is subtracted by 4d+1. Thereafter, while keeping the row address at O, the column address is incremented by 1 from O to 3. The same thing as above is performed while updating the row addresses one by one. In order to carry out the addressing method described above using the addressing device shown in FIG. 7, the following minor changes may be made to it. (3) Changes in (1) and (2) above and changes in (1) to (3) in the case of dinterleave. In the case of FIG. 21, data writing is performed in the next step. First, add the row address by d from O, and
At the same time, the column address is also incremented by 1 from 0 to 3. Next, when the column address reaches 3, 4d+1 is added to the row address. Then change the row address to 7d+
While keeping it at 1, change the column address from 3 to O by 1. The same thing as above is performed while updating the row addresses one by one. Successive output of data is performed in the next step. First, while keeping the row address at O, the column address is changed from O to 3 by one. Next, when the column address reaches 3, 3d+1 is added to the row address. Thereafter, the row address is subtracted by d, and in step with this, the column address is subtracted from 3 to O by 1. The same thing as above is performed while updating the row addresses one by one. In order to carry out the addressing method described above using the addressing device shown in FIG. 7, it is only necessary to make the following small changes to it. (4) Changes in <1) and (2) above and changes in (4) and (5) in the case of dinterleave. In the case of FIG. 22, data writing is performed in the next step. First, add the row address from 0 to d, and
In step with this, the column address is subtracted from 3 to O by 1. Next, when the column address reaches 0, 4d+1 is added to the row address. Thereafter, the column address is changed from O to 3 by 1 while keeping the row address at 7d+1. The same thing as above is performed while updating the row addresses one by one. Successive output of data is performed in the next step. First, while keeping the row address at 0, the column address is changed from 3 to 0 by 1. next,
When the column address reaches O, 3d+1 is added to the row address. Thereafter, the row address is subtracted by d, and in step with this, the column address is added from O to 3 by 1. The same thing as above is performed while updating the row addresses one by one. In order to carry out the addressing method described above using the addressing device shown in FIG. 7, the following small changes 51- may be made to it. (5) Changes to (3) and (4) above. As described above, as is clear from comparing, for example, FIG. 3 and FIG. can be done. That is, when using a conventional addressing device, sx (
A memory capacity of 7d + 1) bits was required. However, according to the present invention, a memory capacity of 4X (7d + 2) bits per bit in a word is sufficient (4
corresponds to the number of lower addresses, and 7d+2 corresponds to the number of upper addresses. See Figure 12. ). In this case, when performing interleaving or dinterleaving, the memory capacity truly required per 1 bit in a word is
Since the total of .about.7d is 28d bits, according to the present invention, interleaving and dinterleaving can be performed with a memory capacity close to the truly required memory capacity. Further, according to the present invention, the memory capacity is only about half that of the conventional device, which is economical, and furthermore, the device can be made smaller and consume less power. In particular, the effect of this invention is that the addressing device part is integrated into an LSI, and the memory is externally connected.
This is even more noticeable when the configuration is such that the 4. Brief Description of the Drawings FIG. 1 is an illustrative diagram of a data format for explaining the interleaving and gain interleaving processes that form the background of the present invention. FIG. 2 is a block diagram of a conventional memory addressing device when performing dinterleave processing. FIG. 3 is a diagram schematically showing a memory map per one bit in one word when dinterleaving is performed. FIG. 4 is a time chart for explaining the operation of write address designation circuit 101. FIG. 5 is a time chart for explaining the operation of the successive addressing circuit 102. Figure 6 shows 1 when performing interleaving.
FIG. 2 is a diagram schematically showing a memory map per bit in a word. FIG. 7 is a block diagram showing one embodiment of the present invention. FIG. 8 is a detailed circuit diagram of the gate circuit 21 and control circuit 23 of FIG. 7. FIG. 9 is a time chart for explaining the operation of the gate circuit 21 and control circuit 23. FIG. 10 is a block diagram showing the subtracter 27. FIG. 11 is a block diagram showing the initial setting circuit 50. FIG. 12 is a diagram schematically showing a memory map for each bit in one word when dinterleaving is performed. FIG. 13 is a time chart for explaining the operation of the write address designation circuit 20. Figure 14 shows
3 is a time chart for explaining the operation of the successive address designation circuit 30. FIG. FIG. 15 is a time chart for explaining the operation of the selector 14. FIGS. 16 to 18 are diagrams schematically showing memory maps when other addressing methods are used when performing dinterleaving. FIGS. 19 to 22 are diagrams schematically showing memory maps when interleaving is performed. In the figure, 14 is a selector, 20 is a write address designation circuit, 21 is a gate circuit, 22 is a counter, 23 is a control circuit, 24 to 26 are counters, 27 is a subtracter, 30
31 is a gate circuit, 32 is a counter, 33 is a control circuit, 34 to 36 are counters,
37 is a subtracter, 40 is a memory, and 50 is an initial setting circuit. Agent Shin Kuzuno - (1 other person) 55- °0 v mouth 0 ℃ ℃ 0 ℃ (N CQ J Ln (D
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Claims (1)

[Scope of Claim] A device for specifying a memory address by dividing it into one bit and n bits, comprising a clock signal generating means for generating a clock signal for incrementing the memory address, the clock signal being a first address data generating means that includes a first counting means that adds an n-bit address by a first number each time the clock is given, and generates a count value of the first counting means as n-bit address data; a second address data generating means that generates m-bit address data, including a second counting means that adds the m-bit address by a second number each time a signal is applied; and the first address data generating means and a control means for controlling the second address data generation means, the control means detecting that the n-bit address has reached a predetermined address based on the output of the first counting means. predetermined address detection means; means for causing the first counting means to subtract a first number each time the clock signal is applied after the predetermined address detection means; and means responsive to the output of the predetermined address detection means. and disabling means for disabling the second counting means, the second address data generating means responding to the output of the predetermined address detecting means 'C1 before lk!' A memory addressing device further comprising means for changing the m-bit address data to a value that is the sum of the current m-bit address and a third number.