JPH0145153B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory address circuit for block interleaving or deinterleaving of data.

For PCM recorders and PCM audio disks,
Error correction codes are used to obtain high quality reproduced sound. Generally, a sampled signal word sequence obtained by sampling an analog signal is divided into blocks of multiple words, and an error correction word is added to each block to form one error correction block. On the other hand, corrections are made during playback. However, error correction codes have limitations, and when burst errors occur on the transmission path and most of the words in one error correction block are erroneous, correction becomes impossible. Conventionally, as a countermeasure against burst errors, when recording, interleaving is performed to disperse each word in a correction block, and each word is recorded at a certain interval on the recording medium, and when playing back, deinterleaving is performed to restore the original arrangement. Error correction is then performed.

FIG. 1 is a block diagram showing interleaving and deinterleaving. In Figure 1, 10
1 adds an error correction code to the sampled signal word
This shows the n-th (n is an integer) error correction block consisting of 8 words _D0 to _D7 , 102 shows the delay amount of each word within one block, and d shows an integer. Reference numeral 103 indicates the word structure of one transmission block after interleaving, and each word is composed of words of different error correction blocks and is recorded on the recording medium. 104 indicates the amount of delay in deinterleaving, 105 indicates the configuration of one correction block after deinterleaving, and _D0 to _D7 become the words of the n- _7d -th error correction block, indicating that the combination has returned to the one before interleaving. It shows. By using the interleaving and deinterleaving described above, even if a burst error occurs on the transmission path and 8 words in the block shown at 103 are mixed up, the erroneous words are dispersed by performing deinterleaving, and the block shown at 105 is In this case, only D ₇ and n-7d are errors, which can be corrected.

In order to realize this delay in interleaving and deinterleaving, a method is used in which words are stored in a memory and a desired word is read out. Memory address control when performing deinterleaving in the case of d=16 in FIG. 1 will be explained below as an example.

FIG. 2 shows a conventional memory address control circuit in which 1 is input to the input terminal of counter 2 having a 3-bit output, and 1 is input to the input terminal of counter 2 having a 3-bit output.
3 indicates a write sample clock (hereinafter referred to as WSCK) that determines the addresses of 8 words in the counter, and 3 indicates a write block change clock (hereinafter referred to as WBCK) that is input to the input of counter 4 and the reset terminal of counter 2. 2,
The output of the counter 4 determines the write address of the memory, and the output of the counter 2 designates the lower 3-bit address, and the output of the counter 4 designates the upper address of the memory, which are input to one input of the selector 5, respectively. 82 indicates a select signal. Reference numeral 6 indicates a read sample clock (hereinafter referred to as RSCK) corresponding to the 8 words in the 1 correction block 105 that are input to the counter 7 and counter 11 having 3-bit outputs, and 8 indicates the input of the counter 9 and the reset terminal of the counter 7. The read block change clock (hereinafter referred to as RBCK) input to
As the correction block progresses, one clock is output. 10 indicates a counter that inputs the carry output of counter 9 and outputs it to the parallel input of counter 11; 12 indicates a load clock input to counter 11;
The read address of the memory is determined by 9 and 11, and the output of counter 7 is the lower 3 of the address.
The outputs of counters 9 and 11 specify the upper address, and the outputs of counters 9 and 11 specify the upper address.
A write address and a read address are selected by the selector 5 and added to the memory as a memory address signal 14. 1
Reference numeral 3 designates an initial setting circuit which takes the outputs of counters 9 and 10 as input and generates an output to set counter 4 to 7d when the read upper counter value (value determined by counters 9 and 10) is 0.

Figure 3 shows the time chart of the write address system, Figure 4 shows the time chart of the read address system, and Figure 5 shows the memory map per 1 bit of a word. The address is determined using a 3-bit address value, with the upper address value taken on the vertical axis and the horizontal axis. Further, circles in FIG. 5 indicate read data, and triangle marks indicate write data.

First, the operation of the write address circuit will be explained using FIGS. 2, 3, and 5. Eight words in one transmission block 103 are written with the upper address fixed and the lower address changed from 0 to 7, and the next block is written with the upper address incremented by 1 by WBCK3. FIG. 3 is a time chart when writing the transmission block shown at 103 in FIG. Counter 2 is reset at time _t1 by WBCK3, output 2a of counter 2 becomes 0, and output 4a of counter 4 becomes 7d.
Changes from -1 to 7d. At time _t2 , counter 2 is incremented by 1 and becomes 1 by WSCK1. The first data D ₀ , n is the address (7d, 0) {(m, n) between time t ₁ and t ₂ where m is the upper address value and n
indicates the lower 3-bit address value}, write to
The next data D ₁ , n-d is written to (7d, 1).
By sequentially incrementing the lower address by 1 and writing data, writing of 8 words shown at 103 is completed at time _t3 , counter 4 is incremented by 1 by WBCK3, and the upper address becomes 7d.
+1 and the next block data is written.

Next, the operation of the read-related address circuit is
This will be explained using FIG. 4, FIG. 5, and FIG.

In FIG. 4, counter 7 becomes 0 due to RBCK at time t ₁ , and the read system is initially set to be 7d behind the write system, so
The read upper counter value 41 output from the counter 10 becomes 0. At time _t4 , 0 is loaded into the counter 11 by the load clock 12,
The address becomes (0, 0), and as shown in FIG. 5, the memory output at this time is D ₀ , n-7d, which is data 7d blocks ago, for D ₀ , n. Next, at time _t5 , the output 7a of the counter 7 is output by RSCK12.
becomes 1 and the counter 11 goes up by 1, that is, the read upper address value 42 goes up by d, and the memory address becomes (d, 1) and D ₁ , n
−d−6d=D ₁ , n−7d is output from the memory.
Thereafter, by incrementing counter 7 and counter 11 by 1 and reading them, the n-7d shown in 105 is obtained.
We can obtain the word array of the th correction block. Deinterleaving can be performed continuously by synchronizing the above operations with the write system and the read system, and by circulating the memory by matching the clock phase so that the data in _D7 is written and then read. In the above example, after writing the data of the block shown at 103 to the upper address value 7d, the data of the next block is written to the address whose upper address value is 0, and the reading is the data D ₇ of (7d, 7),
After reading n-7d, by starting to read the first data D ₀ of the next correction block, n-7d+1 from address (1, 0), per 1 bit of the word,
Deinterleaving can be performed by cycling through 8×(7d+1) bits of memory.

The conventional address circuit is configured as described above, so the circuit configuration is simple, but the amount of memory required for deinterleaving is 28d per bit of a word, whereas 8 x (7d + 1) bits are used. This has the disadvantage of increasing memory capacity.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by wrapping the address corresponding to the sample halfway and changing the upper address, it is possible to create a device with about half the memory capacity of the conventional one. The purpose is to provide an address circuit that can perform interleaving.

An embodiment of the memory circuit of the present invention will be described below with reference to the drawings. In Figure 6, 21 is WSCK
1 and the outputs 24a and 24b of the control circuit 24 are shown as inputs, and the gate circuit has two outputs 21a and 21b. 22 is an up-down counter with a 2-bit output, and the output 21a of one of the gate circuits 21 is up-down counter. The other output 21b is connected to the input terminal, the other output 21b is connected to the down input terminal, and the reset terminal is connected to
WBCK3 is input. Reference numeral 24 indicates a control circuit to which WSCK1, the output of the counter 22, and WBCK3 are input, and has two outputs 24a and 24b.The outputs of the gate circuit 21 and the subtraction number of the subtracter 28 are controlled by the outputs 21a and 21b. 23 is
25 is a counter with a 4-bit output that takes WBCK3 as an input and is preset by the output of the initial setting circuit 13; 25 indicates a counter that takes the carry output of the counter 23 as an input and is preset by the output of the initial setting circuit 13; The output 21b of the gate circuit 21 is connected to the up input terminal, the output of the counter 25 is connected to the parallel load input, and the write load clock (hereinafter referred to as WLDCK) is connected.
27 indicates a counter to which the output of the counter 25 is loaded; 28 indicates the output 24 of the control circuit 24;
It shows a subtracter that subtracts 0 when a is 1 and 4d+1 when it is 0 from the values indicated by counters 23 and 26. The output of counter 22 and the output of subtractor 28 are input to the selector, and the counter 22 subtracts 4d+1 from the values indicated by the counters 23 and 26. A bit address is designated, and the output of the subtracter 28 designates an upper address. The above is the configuration of the write address circuit.

Next, the configuration of the read address circuit will be explained.
31 is the output 33a, 3 of the RSCK6 and the control circuit 33
3b is an input and has two outputs 31a and 31b, 32 is an up-down counter with a 2-bit output, and the gate circuit 31
One output 31a is connected to the up input terminal, the other output 31b is connected to the down input terminal, and RBCK8 is input to the reset terminal. 33 is
RSCK6, the output of the counter 32, and RBCK8 are input, and the control circuit has two outputs 33a and 33b. The outputs 33a and 33b control the output of the gate circuit 31 and the subtraction number of the subtracter 34. 34 indicates a subtracter that subtracts 0 when the output 33a of the control circuit 33 is 1, and 3d+1 when it is 0 from the values indicated by counters 9 and 11;
The lower two bits of the memory address are specified via the selector 5 by the output of the subtracter 34, and the upper two bits of the memory address are specified via the selector 5 by the output of the subtracter 34.

Figure 7 shows the gate circuit 21 and control circuit 2 in Figure 6.
4, 201 is a NAND gate which inputs the output 22a of the counter 22 and outputs 0 when it detects 3, and 202 indicates the NAND gate 201.
The output 202a of the OR gate 202 is input to the clock input terminal, WBCK3 is input to the reset terminal, and the D input terminal is a D-flip-flop connected to the power supply. From then on
DFF), 204 is the NAND gate output 20
The output 24b of the NAND gate 204 and the inverted output 24a of the DFF 203 are the two outputs of the control circuit. The gate circuit 21 is
OR gate 205 with WSCK1 and gate output 24b as inputs, WSCK1 and DFF inverted output 24a
It is composed of two gates, an OR gate 206, which receives as inputs, and outputs output signals 21a and 21b, respectively.

Next, the operation will be explained using figures. FIG. 8 shows a time chart of the control circuit and gate circuit of FIG. 7. When WBCK1 becomes 0 at time _t1 , the counter 22 and DFF 203 are reset.
If the output 201a of the NAND gate 201 and the DFF inversion output 24a are both 1, then the OR gate 204
The output 24b becomes 0, and thereafter, WSCK1 is inputted to the up input of the counter 22 via the gate 205. At time _t6 , the output 21a of the OR gate 204 rises, and the value 22a of the counter 22 becomes 3, and the output 201a of the NAND gate 201 becomes 0.
So, at time t ₇ , the output 20 of the OR gate 202
2a changes the inverted output 24a of the DFF 203 from 1 to 0, so one output 24 of the control circuit
b is the time t ₃ at which the next change in WBCK1 occurs from time t _i
The other output 24a becomes 0 from time _t7 to time _t3 . From the above, one output 21a of the gate circuit outputs WSCK3 input between time _t1 and time _t6 , and the other output 21b outputs WSCK3 input between time _t7 and time _t3 . As a result, the output 22a of the counter 22 increases from 0 to 3, maintains the value 3 for two clocks, and then decreases to 0, which is repeated. The gate circuit 31 and the control circuit 33 are also the same as the gate circuit 21 and the control circuit 2.
It has the same configuration as 4.

FIG. 9 shows a time chart for explaining the write system address circuit in FIG. 6, and FIG. 11 shows a memory map. In FIG. The addresses are made to correspond, with circles indicating read data and triangle marks indicating write data.

In FIG. 9, at time _t1 , WBCK3 becomes 0, the output 22a of the counter 22 becomes 0, and the upper counter value 50 (the value of the counter composed of the counter 23 and the counter 25) increases by 1 to become 7d+1. At time _t8 , the value of the counter 25 is loaded into the counter 26 by the WLDCK 27. At this time, the subtracter 28 has a subtraction value of 0, so the upper address 60 becomes 7d+1, and the address becomes (7d+
1,0). At time _t2 , the counter 22 becomes 1 at the rising edge of WSCK1. First data D ₀ ,
Write n to address (7d+1,0) between times _t8 and _t2 . Sequentially up the counter 22 and write data, and from time _t7 , the control circuit output 24a
is 0 and the subtraction number is 4d+1, so address 80 changes to (3d, 3) and this address
D ₄ , write n-4d. From time _t9 , WSCK1 becomes counter 2 from the output 21b of gate circuit 21.
Since it is supplied to the down input of counter 2 and the down input of counter 26, when WSCK changes from 0 to 1, the lower address goes down by 1 and the
6 goes down by 1, that is, the upper address goes down by d. D ₅ , n-5d to (2d, 2), D ₆ , n-6d
Writing D ₇ to (d, 1) and n-7d to (0, 0) completes the writing of one block, and from t ₃ onwards, the upper counter value 50 is incremented by 1 and the writing of the next block is completed. Writing is performed.

FIG. 10 shows a time chart of the read system address circuit. At time t ₁ , RBCK8 becomes 0, the output 32a of the counter 32 becomes 0, and the upper read counter value 70 (the value of the counter composed of counter 9 and counter 10) becomes 1.
It goes up and changes from 0 to 1. This is because in the initial setting circuit 13, when the upper read counter value 70 is 0, the write system upper counter value is set to 7d, and furthermore, since WBCK3 and RBCK8 have the same frequency, the write upper counter value 50 is set to 7d.
When is 7d+1, the read upper counter value 70 becomes 1. At time _t4 , 0 is loaded into the counter 11 by the load clock 12, and the upper address becomes (1, 0). From Figure 11 (1, 0)
The data in (7d+1, ₁ ) is the data of the block 7d before n, so D ₀ ,
Data n-7d is output. At time _t5 , the output 31a of the gate circuit 31 causes the counter 3 to
2 becomes 1, the counter 11 increases by 1, the address becomes (d+1, 1), and D ₁ , n
-d-6d=D ₁ , n-7d is output from the memory.
This operation is repeated until D ₃ and n-7d are output, and from time t ₁₀ onwards, the output 33a of the control circuit 33 causes the subtractor 34 to subtract 3d+1, so the address becomes (0, 3) and D ₄ , n-7d are output from the memory, and at time t ₅ , only the counter 32 goes down by 1, and the address becomes (0, 2), and D ₅ and n-7d are output from the memory.
By lowering only the value of D ₆ , n-7d, D ₇ , n-7d
At time _t12 , reading of 8 words of the (n-7d)th error correction block is completed.

FIG. 12 shows a read address 81 and a write address 80 by a selector using a select signal 82.
A time chart that is selected and added to the memory as memory address 14 is shown. When the select signal 82 is “1”, the write address becomes memory address 14, and the select signal 82 is “0”
When , read address 81 is memory address 1
4 and is added to memory. in this way,
WBCK3 and RBCK8 perform time-sharing memory writing and reading within one block with the same cycle, and as the block is changed, the upper counter value is incremented by 1 and the memory addresses are cycled to perform continuous deinterleaving. I can do it.

In the above embodiment, the lower two bit counter 22,
32 started from 0, but if you want to start from 3, deinterleave by swapping the up and down inputs and changing the NAND gate 201 that detects 3 in the control circuit to an OR gate that detects 0. I can do things. In the case of interleaving, the counter 26 is replaced with an up counter, the counter 11 is replaced with a down counter, the initial setting is 0, the number of subtractions by the subtractor 28 is 15d+1, and the number of subtractions by the subtractor 34 is
This can be achieved by setting it to 16d.

As described above, according to the present invention, deinterleaving can be performed using 4 (7d+2) bits per word, which is about half the memory capacity of the conventional method, although the circuit size is slightly larger than that of the conventional method.
The device can be made at low cost. This is especially effective when the signal processing section is made into an LSI and the memory is externally attached.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing interleaving and deinterleaving, Fig. 2 is a diagram showing a conventional memory address circuit, Fig. 3 is a time chart for explaining a writing system address circuit of a conventional memory address circuit, and Fig. 4 is a block diagram showing interleaving and deinterleaving. 5 is a time chart for explaining a read-out system address circuit of a conventional memory address circuit, FIG. 5 is a memory map of a conventional memory address circuit, and FIG. 6 is a memory address circuit diagram showing an embodiment of the present invention. FIG. 7 is a diagram showing an example of the gate circuit and control circuit of FIG. 6,
8 is a time chart for explaining FIG. 7, FIG. 9 is a time chart for explaining the write system address circuit of FIG. 6, and FIG. 10 is a time chart for explaining the write system address circuit of FIG.
A time chart for explaining the read-out address circuit shown in the figure, FIG. 11 is a memory map in one embodiment of the present invention, and FIG. 12 is a time chart showing how write addresses and read addresses are added to memory addresses in a time-sharing manner. Show chart. In the diagram, 1 is WSCK, 3 is WBCK, and 6 is
RSCK, 8 is RBCK, 9, 10, 11, 22, 2
3, 25, 26, 32 are counters, 12 is a load counter, 21, 31 are gate circuits, 24, 33
27 is a control circuit, 27 is a WLDCK, 28 and 34 are subtracters, and 82 is a selector. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. A memory circuit that generates a different combination of data by applying different delays to each word in a block consisting of a plurality of words of data, comprising: a memory; A first row address generation means for generating a row address of the write address of this memory, a first column address generation means for generating a column address, and detecting when the value of this column address reaches a predetermined number c. a first detection means, a second row address generation means for generating a row address of the read address of the memory, and a second column address generation means for generating a column address; when the number of column addresses reaches a predetermined number c; a second detection means for detecting this, the first column address generation means, the first row address generation means, and the data write address generated by the first detection means and the second column address generation means; means, a second row address generating means and a second
a selection circuit that selects one of the data read addresses generated by the detection means and supplies it to the memory, and when writing one block of data to the memory during deinterleaving, the row address is set to an initial value. While keeping the column address at b, add a predetermined number a for each word to the initial value p of the column address, and when the column address reaches the predetermined number c, the column address of the next word is changed to the row address while keeping the predetermined number c. is changed to a value obtained by subtracting a predetermined number d from b,
After that, a write address is generated and given to the memory by subtracting the column address by a predetermined number a and the row address by a predetermined number e for each word. The address is added to the initial value p by a predetermined number a for each word, and the row address is added to the initial value f by a predetermined number e, and when the column address reaches the predetermined number c, the column address of the next word is set to a predetermined value. Change the row address to a value obtained by subtracting a predetermined number g while keeping the number c, and then change the column address to the above predetermined number a for each word without changing the row address.
A memory circuit configured to generate a read address and provide it to the memory using a step-by-step subtraction procedure. 2 When writing one block of data to the above memory during interleaving, keep the row address at the initial value b and add the column address to the initial value p by a predetermined number a for each word, so that the column address becomes the predetermined number. For the next word that reaches c, the column address remains the predetermined number c, and the row address is changed from the initial value b to the predetermined number d.
After that, for each word, the column address is subtracted by a predetermined number a, and the row address is added by a predetermined number e, thereby generating a write address and applying it to the memory to write one block of data. When reading from memory, the column address is added to the initial value p by a predetermined number a for each word, and the row address is subtracted by a predetermined number e from the initial value f, and when the column address reaches the predetermined number c, The column address of the word remains at its predetermined number c, and the row address is changed to a value obtained by subtracting a predetermined number g, and then the column address is subtracted by a predetermined number a for each word without changing the row address. 2. The memory circuit according to claim 1, wherein the memory circuit is configured to generate an address and provide it to the memory by sequential reading.