JPH0215943B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit, and more particularly to a memory circuit that uses a memory to interleave or deinterleave data in blocks.

Recently, error correction codes have been used in PCM recorders and PCM audio disks in order to obtain high quality playback sound. The error correction method using this error correction code divides the word sequence of the sampled signal obtained by sampling the analog signal into blocks of multiple words or multiple frames, and adds an error correction word to each block to eliminate one error. This is a method in which a correction block is configured to correct words that are erroneous on the transmission path during reproduction. However, such an error correction system has a limit and cannot be corrected when most of the words in one error correction block are erroneous due to burst errors occurring on the transmission path.

Conventionally, as a countermeasure against burst errors, an interleaving method is used to disperse each word in an error correction block during recording, and a device that records each word at certain intervals on the recording medium and returns it to its original arrangement during playback. By interleaving,
Errors were corrected.

FIG. 1 is an illustrative diagram of a data format for explaining the interleaving and deinterleaving processes that form the background of the present invention. In the illustration, one frame is one block, and one block is
This shows an error correction block consisting of 8 words D0 to D7. In this case, group 1 consists of 8 signals D0 to D7, which are sampled signal words with error correction codes added.
The Nth error correction block consisting of words is shown. For example, words D0-D5 are data,
Words D6 and D7 are error correction codes. However, N is an integer. Group 2 shows the delay amount of each word D0, D1, D2 to D7 in one block,
It is defined as 0, d, 2d to 7d. however,
d indicates an integer unit delay amount, and is selected, for example, as the data transmission time of one word. In the following description, d=16 as an example. When interleaving, each word D0 in one block
D7 is delayed by the amount of delay corresponding to each word. Group 3 shows the word structure of one block after interleaving. After the interleaving process, each block is composed of words that were in different numbered error correction blocks, and is recorded on a recording medium such as a vinyl record. group 4
represents the amount of delay for each word when interleaved data is deinterleaved as described above. The amount of delay during deinterleaving is selected to be inversely proportional to the amount of delay during interleaving. For example, the amount of delay during interleaving is 0, d for words D0, D1 to D7, respectively.
If ~7d is selected, the delay amounts are selected to be 7d and 6d~0 during deinterleaving, respectively. Group 5 shows the format of one error correction block after deinterleaving processing has been performed.
As is clear from the illustration, each word D0 to D7 is
All of the words are equal to the words of the N-7dth error correction block, and the combination is returned to the one before interleaving except that there is a delay amount of 7d.

When interleaving and deinterleaving are performed as shown in Figure 1, even if a burst error occurs on the transmission path and an error equal to the length of 8 words of the block shown in group 3 occurs, the deinterleaving Since the erroneous words are dispersed by performing the above processing, only one word is erroneous within one block obtained by the deinterleaving processing, and correction becomes possible. In order to realize such interleaving and deinterleaving processing, a method is used in which one block of word data is temporarily stored in a memory, and then each word is read out in a predetermined order. Memory address control when performing interleaving and deinterleaving will be described below.

First, a case in which deinterleaving is performed will be explained.

FIG. 2 is a block diagram of a conventional memory addressing device when performing deinterleaving processing. In the figure, addressing device 1
0 includes a write addressing circuit 101 and a read addressing circuit 102. The specific configuration of the addressing device 10 will be described below. A write sample clock WS (hereinafter referred to as clock WS) is applied to the input terminal 11a. This clock WS is applied to the addition input terminal UP of the counter 12. The counter 12 has a 3-bit output, performs an addition operation every time the clock WS is applied, and derives the calculated value as write address data corresponding to a word within one block. A write block change clock WB (hereinafter referred to as clock WB) is applied to the input terminal 11b. This clock WB is applied to the reset terminal R of the counter 12 and also to the addition input terminal UP of the counter 13. The write address of memory 40 is determined by the outputs of these counters 12 and 13. That is, the output of the counter 12 is given to the selector 14 as write address data specifying the lower three bits of the memory 40.
The output of the counter 13 is given to the selector 14 as write address data specifying the upper address of the memory 40.

The input terminal 11c has a read sample clock.
RS (hereinafter referred to as clock RS) is given. This clock RS corresponds to 8 words within one error correction block. The clock RS is applied to the addition input terminal UP of the counter 15 and also to the addition input terminal UP of the counter 16. Counter 15 has a 3-bit output and clock RS
is added each time input terminal 11d is given.
It is reset by the clock RB input to RB. Clock RB is a read block change clock and is applied one clock at a time as the error correction block number advances. This block RB
is applied to the addition input terminal UP of the counter 17. The counter 17 has a 4-bit output and outputs the carry output from the carry output terminal CA to the counter 1.
Give it to the addition input terminal UP of 8. The counter 18 is
The calculated value is given as a parallel load input to the counter 16. The counter 16 has an input terminal 11
The load clock LD given to e is input.
The read address of the memory 40 is determined by the outputs of these counters 15-17. That is,
The output of the counter 15 is derived as read address data specifying the address of the lower three bits.
The outputs of counters 16 and 17 are derived as read address data specifying an upper address of the memory. These read address data are given to the selector 14.

The selector 14 switches and derives a write address or a read address in response to a select signal SL applied to an input terminal 11f. The write address data or read address data selected by the selector 14 is derived from the output terminal 11g as memory address data and is applied to the memory 40.

The initial setting circuit 19 includes counters 17 and 1.
The output of 8 is input. This initial setting circuit 19
generates an output that sets the count value of the counter 13 to 7d when the value determined by the outputs of the counters 17 and 18 is 0.

Before explaining in detail the operation of the addressing device shown in FIG. 2, its general operation will be explained using FIG. FIG. 3 is a diagram schematically showing a memory map per one bit in one word when deinterleaving is performed. The upper address value is selected as the row address, and the lower 3 bit address value is selected as the column address. Triangular marks indicate write data, and circles indicate read data. Data is written by changing the column address from 0 to 7 by 1 while keeping the row address at a predetermined value. The same thing is done while updating the row addresses one by one. In the figure, data (D0, N) and (D1, N-) are at row address 7d and column addresses 0 to 7.
d), (D2, N-2d), (D3, N-3d), (D4, N-
4d), (D5, N-5d), (D6, N-6d) and (D7, N-7d) are respectively written in order. Data is read by changing the column address by 1 from 0 to 7 each time d is added to the row address obtained by subtracting 7d from the write address. The same thing is done while updating the row addresses one by one. In the figure, address (0,
1), (d, 1), (2d, 2), (3d, 3), (4d,
4), (5d, 5), (6d, 6) and (7d, 7) data (D0, 7-7d), (D1, N-7d), (D2, N
-7d), (D3, N-7d), (D4, N-7d), (D5, N
-7d), (D6, N-7d) and (D7, N-7d) are read out in sequence. This read data has been deinterleaved.

Now, the operation of the addressing device shown in FIG. 2 will be explained in detail with reference to FIGS. 3 to 5. FIG. 4 is a time chart for explaining the operation of write address designation circuit 101. Fifth
The figure is a time chart for explaining the operation of the read addressing circuit 102.

First, the operation of the write address designation circuit 101 will be explained mainly along the time chart of FIG. In the illustrated example, 8 words in one transmission block (group 3 shown in FIG. 1) are written with the upper address fixed and the lower address changed from 0 to 7, and the next block is written at the clock. This shows the case where the upper address is incremented by 1 and written by WB.

At time t1, the counter 12 is reset by the clock WB, and the counter 13 is incremented by one. Therefore, the output OUT12 of the counter 12 becomes 0, and the output OUT12 of the counter 12 becomes 0.
The output OUT13 is the previous value, for example 7d-
Changes from 1 to 7d.

At time t2, counter 12 clocks
When WS is given, it advances the count value by 1 and outputs 1. At this time, write data WDATA
Among them, the data of the first word (D0, N) in the Nth block is written to the memory during the period between time t1 and time t2. The address is (m, n) where m is the upper address value and n is the lower address value, and in this case, the counter 1
The value 7d of the output OUT13 of the counter 3 becomes the upper address value m, and the output 0 of the counter 12 becomes the lower address value n.
Therefore, the address is (7d, 0). The data of the next word (D1, Nd) is written to address (7d, 1). Thereafter, in the same way, the lower 3 bits of the address increase by 1 for each word, and the data of words D2 to D7 is written to the write address determined by the output OUT13 of the counter 13 and the output OUT12 of the counter 12. It will be done.

Then, at time t3, when the writing of 8 words of data is completed, the clock WB is applied.
Therefore, the count value of the counter 13 is incremented by 1, the upper address m becomes 7d+1, and the next N
The data of each word in the +1st block is sequentially written. Actually, in this case, the count value of the counter 13 reaches the upper limit, and the count value becomes 0.
The upper address m also cycles to 0.

Next, the operation of the read address designation circuit 102 will be explained mainly along the time chart of FIG.

When clock RB is input at time t1,
Counter 15 is reset and its output OU15
becomes 0. As a result, the lower read address is 0.
becomes. On the other hand, at this time, the counter 13 is initialized to a value of 7d by the initial setting circuit 19,
The upper address of the read address designation circuit 101 is set to lag behind that of the write address designation circuit 102 by 7d. Therefore, when the upper address of the write address designating circuit 101 is 7d, the upper read count value URCV composed of the count value of the counter 17 and the count value of the counter 18 is 0. That is, the initial setting circuit 19 is provided to prevent the write address and read address of the memory from colliding. If the initial setting circuit 19 were not present, both write and read addresses would start from random addresses when the power is turned on, and the combination of read data would not be normal. When the initial value 7d is set constant in the initial setting circuit 19, when the write and read frame frequencies are the same, both the write and read addresses circulate through the memory while maintaining a constant relationship.

At time t4, when the load clock LD is applied to the input terminal 11e, the counter 16 is loaded with 0. As a result, the upper address m becomes 0, and as a result, the read address becomes (0, 0). At this time, data (D0, N-7d), which is data 7d blocks before data (D0, N), is read out from the memory 40, as shown in FIG.

At time t5, when clock RS is given,
The output OUT15 of the counter 15 becomes 1. At the same time, the counter 16 is incremented by one. This corresponds to incrementing the upper read address m by d. Therefore, the read address of the memory is (d, 1), and the data (D1, N-d-
6d) = (D1, N-7d) is read from memory 40.

Thereafter, in the same manner, the calculated values of counters 15 and 16 are incremented by 1 by clock RS, and both counts are specified. By reading the data stored at the address, the word arrangement of the N-7dth error correction block shown in group 5 in FIG. 1 can finally be obtained.

Deinterleaving can be performed continuously by synchronizing the write system and read system and synchronizing the clock phases so that the data in word D7 is written and then read. It will be done. In the example of FIG. 1, after writing the data of the block shown in group 3 to the upper address 7d, the data of the next block is written to the address of the upper address 0, and the data (D7, 7) of the read address (7d, 7) is written. After reading data (D0, N-7d+1) of the first word of the next error correction block
By starting to read from address (1, 0), it is possible to perform deinterleaving by cycling through 8 x (7d + 1) bits of memory for each bit in a word (8 corresponds to the number of lower addresses,
7d+1 corresponds to the number of upper addresses. See Figure 3. ).

The memory address control when performing deinterleaving has been described above. Regarding memory address control when performing interleaving,
Although it will be easily understood from the above explanation, a brief explanation will be given below for clarity.

FIG. 6 is a diagram schematically showing a memory map per bit within one word when interleaving is performed. The differences from FIG. 3 will be mainly explained. Data is written by changing the column address from 0 to 7 by 1 while keeping the row address at a predetermined value. The same thing is done while updating the row addresses one by one. They are similar to those for deinterleaving. In the diagram, row address 7d,
Data (D0, N), (D1,
N), (D2, N), (D3, N), (D4, N), (D5,
The case where N), (D6, N) and (D7, N) are written in order is shown. To read data,
Each time d is subtracted from the row address at the time of writing, the column address is changed from 0 to 7 by 1. The same thing is done while updating the row addresses one by one. In the figure, addresses (7d, 0), (6d, 1),
(5d, 2), (4d, 3), (3d, 4), (2d, 5),
From (d, 6) and (0, 7), the data written there respectively (D0, N) and (D1, N-
d), (D2, N-2d), (D3, N-3d), (D4, N-
4d), (D5, N-5d), (D6, N-6d) and (D7, N-7d) are read out in sequence. As a result of the above, the delay amounts shown in group 2 in FIG. 1 are obtained, and interleaving is performed.

In order to perform interleaving as described above using the addressing device shown in FIG. 2, it is only necessary to change the counter 16 down. Therefore, for details of the operation of the addressing device of FIG. 2 when interleaving, taking into account the above changes, reference is again made to FIGS. 4 and 5 and their associated descriptions. .

However, when performing interleaving or deinterleaving as shown in Figure 1, the memory capacity truly required per 1 bit in a word is 28d bits, which is the sum of each delay amount 0 to 7d. Therefore, when using the conventional addressing device shown in FIG. 2, a memory capacity of 8.times.(7d+1) bits is required for each bit in a word, as explained above. That is, it requires a memory capacity that is approximately twice the memory capacity that is truly required, which is uneconomical. Therefore, there has been a demand for a memory circuit that can perform interleaving and deinterleaving with a memory capacity close to the truly required memory capacity.

Therefore, when interleaving or deinterleaving data using a memory, it is an object of the present invention to provide a memory circuit that can perform interleaving and deinterleaving with a memory capacity close to the memory capacity that is truly required. purpose.

In summary, the present invention is a method in which the memory addressing method is folded back within the memory.

Embodiments of the present invention will be described below based on the drawings.

FIG. 7 is a block diagram showing one embodiment of the present invention. In short, this embodiment consists of a memory 4
a write address designation circuit 20 that specifies an address when writing data to 0; an initial setting circuit 50 that is connected to the write address designation circuit 20 and provides an initial read row address; and the initial setting circuit 5.
0, and is connected to a read addressing circuit 30, a write addressing circuit 20, and a read addressing circuit 30, which designate an address when reading data from the memory 40, and is connected to a A selector 14 is provided to switch and connect to the memory 40. The write address designation circuit 20 has a first address designation means for adding a column address by a predetermined integer value B while keeping the row address at a predetermined positive integer value A, and when the column address reaches a predetermined positive integer value C a second addressing means for subtracting the row address by a predetermined integer value D in response to the row address; 3 addressing means. The read address designation means 30 includes a fourth address designation means that adds the predetermined integer value E to the initial read row address and also adds the column address by the predetermined integer value B in step with the column address. fifth addressing means for subtracting a row address by a predetermined integer value G in response to reaching the predetermined integer value C; and a fifth addressing means for subtracting the row address by a predetermined integer value G while maintaining the row address at a positive predetermined integer value H while changing the column address to the predetermined integer value B. and a sixth addressing means for subtracting by increments.

Next, the detailed configuration and operation of the addressing device shown in FIG. 7 will be explained. Figure 7 shows the second
This is a block diagram when deinterleaving is performed as in the case shown in the figure (the case where interleaving is performed will be explained later).

The write address designation circuit 20 includes a gate circuit 2
1, counter 22, control circuit 23, counter 24
26 and a subtractor 27. Gate circuit 2
1 receives the clock WS and the outputs A and B of the control circuit 23. This gate circuit 21 includes two OR gates 211, as shown in FIG.
212. The counter 22 is an up-down counter with a 2-bit output, and
One output C of the gate circuit 21 is an addition input terminal
UP and the other output D is the subtraction input terminal
Given to DN. A clock WB is input to the reset terminal R of the counter 22. counter 2
4 is a 4-bit counter, and clock WB
and initialized by the initialization circuit 50. The counter 25 receives the carry output of the counter 24 as an input, and is preset with the output of the initial setting circuit 50. In the counter 26, the output D of the gate circuit 21 is applied to a subtraction input terminal DN, and the output of the counter 25 is applied as a parallel load input. The counter 26 is connected to the input terminal 11
The output of the counter 25 is loaded every time a write load clock (hereinafter referred to as clock WL) inputted via f is given. The subtractor 27 is
0 when the output A of the control circuit 23 is "1" (high level), or 4d+1 when the output A is "0" (low level), and is composed of the output of the counter 24 and the output of the counter 26. It is subtracted from the value. The output of this counter 22 is given to the selector 14 as an n-bit write address,
The output of the subtracter 27 is applied to the selector 14 as m-bit write address data. Therefore, in the memory 40, the lower two bits of the write address are designated by the calculated value of the counter 22, and the upper write address is designated by the output of the subtracter 27.

The read address designation circuit 30 has the same configuration as the write address designation circuit 20, and the gate circuit 3
1, counter 32, control circuit 33, counter 34
.about.36 and a subtractor 37. Subtractor 37
is 0 when the output A of the control circuit 33 is “1”,
When the output A is "0", it works to subtract 3d+1 from the value made up of the output of the counter 34 and the output of the counter 36. The rest of the configuration is the same as that of the read addressing circuit 20, so a detailed explanation will be omitted.

Before providing a detailed explanation of the operations of write addressing circuit 20 and read addressing circuit 30, the individual configurations and operations of gate circuit 21, control circuit 23, subtracter 27, and initial setting circuit 28 will be explained.

FIG. 8 is a detailed circuit diagram of the gate circuit 21 and control circuit 23 of FIG. 7. To explain the specific configuration of the control circuit 23, the NAND gate 231
receives the output OUT22 of the counter 22 as an input, and outputs "0" (low level) when 3 (that is, 11 in binary) is input.
The OR gate 232 receives the output of the NAND gate 231 and the clock WS, and provides its output F to the clock input terminal T of a D-type flip-flop (hereinafter referred to as DFF) 233. A clock WB is input to the reset input terminal R of the DFF 233. An input terminal D of the DFF 233 is connected to a power supply V. Inverted output A from the inverted output terminal of DFF233 and output E from NAND gate 231
is given to NAND gate 234.

Referring to FIGS. 8 and 9, the gate circuit 21
And the operation of the control circuit 23 will be explained. FIG. 9 is a time chart for explaining the operations of the gate circuit 21 and the control circuit 23.

At time t1, when the clock WB goes low, the counter 22 and DFF 233 are reset. Therefore, the output E of the NAND gate 231 and the inverted output A of the DFF 233 both become high level, and the output B of the NAND gate 234 becomes low level. Thereafter, the clock WS is connected to the addition input terminal of the counter 22 via the OR gate 211.
Given to U.P.

At time t6, when the output C of the OR gate 211 falls, the output OUT22 of the counter 22 becomes 3.
Therefore, the output E of the NAND gate 231 becomes low level.

At time t7, the output F of the OR gate 232 causes the inverted output A of the DFF 233 to change from high level to low level. Therefore, the output B of the NAND gate 234 is output from time t6 to the next clock.
The output A of the DFF233 is at a high level during the period from time t3 when WB changes, and the output A of the DFF233 is from time t7 to time t3.
It will be at a low level during this period. By this,
The OR gate 211 outputs the clock WS input during the period from time t1 to time t6. or gate 212
outputs the clock WS input between times t7 and t3. Therefore, the counter 22 counts up the output OUT22 from 0 to 3,
After maintaining the count value 3 for two clocks, the operation of counting down to 0 is repeated.

FIG. 10 is a block diagram showing the subtracter 27. The subtracter 27 is a 4-bit adder 271, m
-4-bit adder 272 and complement setter 27
Equipped with 3. The output OUT24 of the counter 24 is input to the adder 271, and the output OUT26 of the counter 26 is input to the adder 272. Outputs OUT27 of counters 271 and 272 are applied to selector 14 as m-bit address data. The complement setter 273 sets the complement [4d+1] of the value 4d+1 to be subtracted in the subtracter 27, outputs 0 when the output A of the control circuit 23 is "1", and outputs the complement when the output A is "0". Output [4d+1]. Adders 271 and 272 output the output OUT24 of the counter 24 and the output of the counter 26.
Add 0 or complement [4d
+1] is added. However, since memory addresses cycle, if the addition result is a carry,
The carry amount is ignored. Therefore, the subtractor 27 is
When the output A of the control circuit 23 is "1", 0 is subtracted, and when the output A is "0", 4d+1 is subtracted from the value composed of the output OUT24 of the counter 24 and the output OUT26 of the counter 26. Regarding the subtracter 33, except that the value to be subtracted is 3d+1,
It is similar to the subtracter 27.

FIG. 11 is a block diagram showing the initial setting circuit 50. The initial setting circuit 50 includes a 0 detection circuit 5
1, an AND gate 52 and an inverter 53. The 0 detection circuit 51 is composed of, for example, a NAND gate having an m-bit input terminal. 0
The detection circuit 51 includes the output OUT3 of the counter 34.
4 and the output OUT35 of the counter 35 is inputted. 0 detection circuit 51
is “1” when its input is 0 and gate 5
Output for 2. A clock RB (negative logic) is input to the inverter 53, and the clock RB with its polarity inverted is applied to the AND gate 52. Therefore, the output of counter 34
When the clock RB is input when the value composed of OUT34 and the output OUT35 of the counter 35 is 0, the AND gate 52 outputs "1". The “1” output from the AND gate 52 is the counter 2
4 and counter 25, thereby forcing the value consisting of the output of counter 24 and the output of counter 25 to be initialized to 7d.

Before explaining in detail the operation of the addressing device shown in FIG. 7, its general operation will be explained using FIG. 12. FIG. 12 is a diagram schematically showing a memory map per one bit in one word when deinterleaving is performed. The upper address is selected as the row address, and the lower 2 bit address is selected as the column address. The major difference from FIG. 3 is that the column address is 2 bits. Triangular marks indicate write data, and circles indicate read data. Data writing is performed in the next step. First, while keeping the row address at a predetermined value, for example 7d+1, change the column address from 0 to 3.
change by 1. In the figure, row address 7d+
1. Data (D0, N) in column addresses 0 to 3,
(D1, N-d), (D2, N-2d) and (D3, N
-3d) are written in order. Next, when the column address reaches 3, the row address is subtracted by 4d+1. Thereafter, the row address is subtracted by d, and at the same time, the column address is also subtracted from 3 to 0 by 1. In the figure, addresses (3d, 3), (2d, 2), (d, 1)
and data (D4, N-4d) at (0,0),
(D5, N-5d), (D6, N-6d) and (D7, N
-7d) are written in order. The same thing as above is performed while updating the row addresses one by one. Data reading is performed in the next step. First, 7d from the line address when writing
Each time d is added to the row address obtained by subtracting d, the column address is changed by 1 from 0 to 3. In the figure, addresses (1, 0), (d+1, 1),
Data of (2d+1, 2) and (3d+1, 3) (D0, N-7d), (D1, N-7d), (D2, N-7d)
and (D3, N-7d) are read out in sequence. Next, when the column address reaches 3, the row address is subtracted by 3d+1. Thereafter, while keeping the row address at 0, the column address is subtracted from 3 to 0 by 1. In the figure, addresses (0, 3), (0, 2),
(0, 1) and (0, 0) data (D4, N-
7d), (D5, N-7d), (D6, N-7d) and (D7, N-7d) are read out in sequence. The same thing as above is performed while updating the row addresses one by one. As described above, the delay amounts shown in group 4 in FIG. 1 are obtained, and deinterleaving is performed.

Now, the operation of the addressing device shown in FIG. 7 will be explained in detail using FIGS. 13 to 15. FIG. 13 is a time chart for explaining the operation of the write address designation circuit 20. FIG. 14 is a time chart for explaining the operation of the read addressing circuit 30. FIG. 15 is a time chart for explaining the operation of the selector 14.

First, the operation of the write address designating circuit 20 will be explained mainly along the time chart of FIG.

At time t1, when the clock WB becomes low level, the output OUT22 of the counter 22 becomes 0. At the same time, the output of counter 24 and
The upper count value UWCV for specifying the upper address m consisting of the output of 5 is incremented by 1. As a result, the upper count value UWCV is
It changes from the previous value, for example 7d, to 7d+1.

At time t8, when the low level clock WL is applied, the value of the counter 25 is loaded into the counter 26. At this time, the output A of the control circuit 23 is "1" (see FIG. 9), and the subtracter 27
Since the subtraction number is 0, the write address is (77d
+1,0). For this reason, the written data
Data of word (D0, N) in the Nth block of WDATA is written to address (7d+1, 0) during the period from time t8 to t2.

At time t2, the count value of the counter 22 becomes 1 at the rising edge of the clock WS. Therefore, the data of the next word (D1, N-d) is at the address (7d
+1, 1). Thereafter, in the same manner, each time the clock WS is applied, the count value of the counter 22 increments by 1, and the address of the lower two bits changes.

Then, at time t7, the output of the counter 22
OUT22 becomes 3. Then, as explained in FIG. 9, the output A of the control circuit 23 becomes "0",
Since the subtraction number of the subtracter 27 becomes 4d+1, the address changes to (3d, 3). Therefore, the data in word (D4, N-4d) is at address (3d,
3).

At time t9, the clock WS becomes the output D of the gate circuit 21 and is applied to the subtraction input terminals DN of the counters 22 and 26. Therefore, when the clock WS changes from low level to high level, the output OUT22 of the counter 22 becomes 1.
, the lower address goes down by 1, and the count value of the counter 26 goes down by 1 (that is, the higher address m goes down by d).
This causes the data of word (D5, N-5d) to be written to address (2d, 2). Thereafter, data of word (D6, N-6d) is sequentially written to address (d, 1) and data of word (D7, N-7d) is written to address (0, 0) in the same manner. In this way, in the period from time t1 to t3,
One block of data writing is completed. In addition, the time
After t3, the upper count value UWCV increases by 1 (i.e., 7d+2) in the same manner as described above.
Then, the data of each word of the next block is written. Actually, in this case, the values of the counters 24 and 25 reach their upper limits, and the upper count value UWCV cycles to zero.

Next, the operation of the read address designating circuit 30 will be explained mainly along the time chart of FIG.

At time t1, when the clock RB goes low, the counter 32 is reset and its output OUT32 goes to zero. At the same time, the upper read count value URCV consisting of the output of the counter 34 and the output of the counter 35 increases by 1, and changes from the previous value A to 1. Here, comparing the upper address m of the read address designation circuit 20 and the write address designation circuit 30, when the upper read count value URCV is 0, the upper write count value UWCV is set to 7d by the initial setting circuit 50.
(see FIG. 11 and its explanation). Also, Kurotsuku WB and Kurotsuku
Since the same frequency as RB is selected, when the upper write count value UWCV is 7d+1, the upper read count value URCV becomes 1. That is, the initial setting circuit 50 is for preventing the write address and read address of the memory from colliding. If the initial setting circuit 50 were not present, both write and read addresses would start from random addresses when the power was turned on, and the combination of read data would not be normal. Once the initial value 7d is set in the initial setting circuit 50, if the write and read frame frequencies are the same, both the write and read addresses circulate through the memory while maintaining a constant relationship.

At time t4, when the load clock LD is applied to the counter 36, the counter 36 loads 0, which is the output of the counter 35. At this time, the output A of the control circuit 33 is "1", and the subtracter 37
Since the subtraction of is 0, the specified address is (1, 0). The data when the address is (1, 0) is the data of the block 7d earlier than the data (D0, N) whose address is (7d+1, 0), so the output data from the memory 40 is
RDATA becomes word (D0, N-7d) data.

At time t5, the output C of the gate circuit 31 causes the output OUT32 of the counter 32 to become 1,
The count value of the counter 36 increases by 1. That is, the upper address m increases by d. The address specified at this time is (d+1, 1). Therefore, the data read from memory 40 is word (D1, N-d-6d) = (D1, N-
7d) data. Such operations are repeated until the data of word (D3, N-7d) is read out.

After time t10, the output A of the control circuit 33 is “0”
As a result, the subtracted number of the subtracter 37 becomes 3d+
It becomes 1. Therefore, the address becomes (0, 3) and the data of word (D4, N-7d) is read from the memory.

At time t11, only the counter 32 decrements by 1, and the address becomes (0, 2). The word (D5, N) specified by this address (0, 2)
-7d) data is read from memory. Thereafter, in the same way, each time clock RS is given,
The value of the counter 32 decreases by 1, and the data of word (D6, N-7d) and word (D7, N
-7d) are read out sequentially.

At time t12, reading of 8 words of the N-7dth error correction block is completed.

FIG. 15 is a time chart for explaining the operation of the selector 14. The selector 14 is selected by the select signal SL applied to the input terminal 11f.
selectively switches the write address WAD and the read address RAD and applies them to the memory 40. for example,
When the select signal SL is high level, write address WAD is selected and the memory specified address
As SAD, memory 4 is connected via output terminal 11g.
given to 0. On the other hand, when selector signal SL is at low level, read address RAD is selected and
Output terminal 1 as memory specified address SAD
1g to the memory 40. When write address WAD is selected and read address
Since the memory designated address SAD in the case where RAD is selected can be easily understood by referring to FIG. 15, a detailed explanation thereof will be omitted. As shown in Fig. 15, clock WB and clock RB have the same period, and
WS and clock RS have the same period, and write address WAD and read address RAD are select signals.
By switching using SL, deinterleaving can be performed continuously.

Note that when deinterleaving is performed, the memory addressing method is not limited to the one described above. Other addressing methods will be briefly explained below. FIGS. 16 to 18 are diagrams schematically showing memory maps when other addressing methods are used when performing deinterleaving. Triangular marks indicate write data, and circles indicate read data.

In the case of FIG. 16, data writing is performed in the next step. First, set the row address to a predetermined value, for example
1 change column address from 3 to 0 while keeping it at 7d+1
Change it step by step. Next, when the column address reaches 0, the row address is subtracted by 4d+1. after that,
The row address is subtracted by d, and in step with this, the column address is added from 0 to 3 by 1. The same thing as above is performed while updating the row addresses one by one. Data reading is performed in the next step. First, 7d from the line address when writing
Add d to the row address obtained by subtracting d, and at the same time, add d to the column address by 3.
Change from 0 to 1 by 1. Next, when the column address reaches 0, the row address is subtracted by 3d+1.
Thereafter, while keeping the row address at 0, the column address is incremented by 1 from 0 to 3. The same thing as above is performed while updating the row addresses one by one. In order to carry out the addressing method described above using the addressing device shown in FIG. 7, the following minor changes may be made to it.

(1) Addition input terminal UP of counters 22 and 32
and the subtraction input terminal DN.

(2) Reset terminals R of counters 22 and 32 are not required, and both counters are set to 3 by clocks WB and RS, respectively.

(3) Instead of the NAND gate that detects 3 included in the control circuits 23 and 33, an OR gate that detects 0 is used.

In the case of FIG. 17, data writing is performed in the next step. First, each d is subtracted from the row address 7d, and in step with this, the column address is added 1 from 0 to 3. Next, when the column address reaches 3, the row address is 3d+
Add 1. Then, while keeping the row address at 7d+1, the column address is changed from 3 to 0 by 1. Do the same thing as above, change the row address to 1
Update it step by step. Data reading is performed in the next step. First, while keeping the row address at 0, the column address is changed from 0 to 3 by 1. Next, when the column address reaches 3, 4d+1 is added to the row address. Thereafter, the row address is added by d, and in step with this, the column address is subtracted by 1 from 3 to 0. The same thing as above is performed while updating the row addresses one by one. In order to carry out the addressing method described above using the addressing device shown in FIG. 7, the following minor changes may be made to it.

(4) Input the output C of the gate circuit 21 to the subtraction input terminal DN of the counter 26.

(5) Input the output D of the gate circuit 31 to the addition input terminal UP of the counter 36.

In the case of FIG. 18, data writing is performed in the next step. First, the row address is subtracted from 7d by d, and in step with this, the column address is subtracted from 3 to 0 by 1. Next, when the column address reaches 0, 3d+1 is added to the row address. Then, keeping the row address at 7d+1,
Change the column address from 0 to 3 by 1. The same thing as above is performed while updating the row addresses one by one. Data reading is performed in the next step. First, while keeping the row address at 0, the column address is changed from 3 to 0 by 1. Next, when the column address reaches 0, 4d+1 is added to the row address. Thereafter, the row address is added by d, and in step with this, the column address is added from 0 to 3 by 1. The same thing as above is performed while updating the row addresses one by one. In order to perform the addressing method described above using the addressing device shown in FIG.
All you have to do is make the changes in ~(5).

The details of memory address control when performing deinterleaving have been described above in detail. Memory address control when performing interleaving will also be easily understood from the above explanation, but for clarity, it will be briefly explained below. FIGS. 19 to 22 are diagrams schematically showing memory maps when interleaving is performed. Triangular marks indicate write data, and circles indicate read data.

In the case of FIG. 19, data writing is performed in the next step. First, while keeping the row address at 7d+1, change the column address from 0 to 3 by 1.
Next, when the column address reaches 3, change the row address to
Subtract 3d+1. Then set the row address to d
At the same time, the column address is subtracted from 3 to 0 by 1 at the same time. The same thing as above is performed while updating the row addresses one by one. Data reading is performed in the next step. First, each time d is subtracted from the row address 7d+1 at the time of writing, the column address is changed by 1 from 0 to 3 in step with it. Next, when the column address reaches 3, the row address is subtracted by 4d+1.
Then, while keeping the row address at 0, the column address is subtracted from 3 to 0 by 1. The same thing as above is performed while updating the row addresses one by one. As described above, the delay amounts shown in group 2 in FIG. 1 are obtained, and interleaving is performed. In order to carry out the addressing method described above using the addressing device shown in FIG. 7, the following minor changes may be made to it. For details of its operation, please refer back to the above description, taking into account the changes.

(1) Change the subtraction input terminal DN of the counter 26 to the addition input terminal UP.

(2) Change the addition input terminal UP of the counter 32 to the subtraction input terminal DN.

In the case of FIG. 20, data writing is performed in the next step. First, while keeping the row address at 7d+1, change the column address from 3 to 0 by 1. Then, when the column address reaches 0, the row address is subtracted by 3d+1. Thereafter, the row address is added by d, and in step with this, the column address is added from 0 to 3 by 1. The same thing as above is performed while updating the row addresses one by one. Data reading is performed in the next step. First, the line address when writing
Each time d is subtracted from 7d+1, the column address changes by 1 from 3 to 0 in step with it. Next, when the column address reaches 0, the row address is subtracted by 4d+1. Then, while keeping the row address at 0, set the column address to 0.
Add 1 to 3 from . The same thing as above is performed while updating the row addresses one by one.
In order to carry out the above addressing method using the addressing device shown in FIG.
You can make the following small changes to it:

(3) Changes to (1) and (2) above, and changes to (1) to (3) in the case of deinterleaving.

In the case of FIG. 21, data writing is performed in the next step. First, the row address is added by d from 0, and at the same time, the column address is also added from 0 to 3 by 1. next,
When the column address reaches 3, 4d is added to the row address
Add +1. Then set the row address to 7d+
While keeping it at 1, change the column address from 3 to 0 by 1. The same thing as above is performed while updating the row addresses one by one. Data reading is performed in the next step. First, set the row address to 0
The column address is changed from 0 to 3 in increments of 1 while maintaining the same value. Next, when the column address reaches 3,
Add 3d+1 to the row address. Thereafter, the row address is subtracted by d, and in step with this, the column address is subtracted from 3 to 0 by 1. Do the same thing as above, change the line address to 1
Update it step by step. In order to carry out the addressing method described above using the addressing device shown in FIG. 7, the following minor changes may be made to it.

(4) Changes to (1) and (2) above and changes to (4) and (5) in the case of deinterleaving.

In the case of FIG. 22, data writing is performed in the next step. First, the row address is added by d from 0 and the column address is subtracted by 1 from 3 to 0 at the same pace. Then when the column address reaches 0, 4d+1 is added to the row address.
Add. Thereafter, the column address is changed from 0 to 3 by 1 while keeping the row address at 7d+1. The same thing as above is performed while updating the row addresses one by one. Data reading is performed in the next step. First, while keeping the row address at 0, the column address is changed from 3 to 0 by 1. Next, when the column address reaches 0, 3d+1 is added to the row address. Thereafter, the row address is subtracted by d, and in step with this, the column address is added from 0 to 3 by 1. The same thing as above is performed while updating the row addresses one by one. In order to carry out the addressing method described above using the addressing device shown in FIG. 7, the following minor changes may be made to it.

(5) Changes to (3) and (4) above.

As described above, according to the present invention, for example, as is clear from FIG. D7) can be written without changing the row address, and a read operation can be performed so as to realize the deinterleaving shown in FIG. Therefore, interleaving or deinterleaving can be performed using approximately half the memory capacity when using a conventional addressing device. This makes it economical because the memory capacity is only about half that of conventional devices.
It is also possible to reduce power consumption. In particular, the effect of this invention is that in the case of a configuration in which the addressing device part is made into an LSI and the memory is externally attached,
It becomes even more noticeable.

[Brief explanation of drawings]

FIG. 1 is an illustrative diagram of a data format for explaining the interleaving and deinterleaving processes that form the background of the present invention. FIG. 2 is a block diagram of a conventional memory addressing device when performing deinterleaving processing. FIG. 3 is a diagram schematically showing a memory map per one bit in one word when deinterleaving is performed. FIG. 4 is a time chart for explaining the operation of write address designation circuit 101. Figure 5 shows read address designation circuit 1.
This is a time chart for explaining the operation of 02. FIG. 6 is a diagram schematically showing a memory map per bit within one word when interleaving is performed. FIG. 7 is a block diagram showing one embodiment of the present invention. FIG. 8 is a detailed circuit diagram of the gate circuit 21 and control circuit 23 of FIG. 7. FIG. 9 is a time chart for explaining the operations of the gate circuit 21 and the control circuit 23. FIG. 10 is a block diagram showing the subtracter 27. FIG. 11 is a block diagram showing the initial setting circuit 50. FIG. 12 is a diagram schematically showing a memory map per one bit in one word when deinterleaving is performed. FIG. 13 is a time chart for explaining the operation of the write address designation circuit 20. FIG. 14 is a time chart for explaining the operation of the read addressing circuit 30. FIG. 15 shows the selector 14
This is a time chart to explain the operation.
FIGS. 16 to 18 are diagrams schematically showing memory maps when other addressing methods are used when performing deinterleaving. 19th
22 are diagrams schematically showing memory maps when interleaving is performed. In the figure, 14 is a selector, 20 is a write address designation circuit, 21 is a gate circuit, 22 is a counter, 23 is a control circuit, 24 to 26 are counters, 27 is a subtracter, 30 is a read address designation circuit, and 31 is a gate 32 is a counter, 33 is a control circuit, 34 to 36 are counters, 37 is a subtracter, 40 is a memory, and 50 is an initial setting circuit.

Claims (1)

[Scope of Claims] 1. A memory circuit that generates a combination of data different from the original by giving a different delay to each word in a block consisting of a plurality of words of data as a unit, comprising: a memory; a first row address generating means for generating a row address of the write address of the memory; and a first address generating means for generating a column address; detecting when the value of the column address reaches a predetermined number c; a first detection means; a second row address generation means for generating a row address of the read address of the memory; and a second column address generation means for generating a column address; and when the column address reaches a predetermined number c. a second detection means for detecting this; a data write address generated by the first column address generation means, the first row address generation means and the first detection means;
a selection circuit that selects one of the data read addresses generated by the column address generation means, the second row address generation means, and the second detection means and supplies it to the memory; When writing one block of data to the memory during deinterleaving, add the column address to the initial value p by a predetermined number a for each word, and
The row address is subtracted by a predetermined number e from the initial value f, and the column address of the next word when the column address reaches the predetermined number c remains the predetermined number c, and the row address is changed to a value obtained by adding a predetermined number g, Thereafter, a write address is generated and given to the memory by subtracting the column address by the predetermined number a for each word without changing the row address, and when reading one block of data from the memory. keeps the row address at the initial value b and adds the column address to the initial value p by a predetermined number a for each word, and when the column address reaches the predetermined number c, the column address of the next word is set to the predetermined value. Change the row address from b to the value obtained by adding a predetermined number d while keeping the number c, and then change the column address to a predetermined number a for each word.
A memory circuit characterized in that a read address is generated and applied to the memory by subtracting the row address by a predetermined number e and adding the row address by a predetermined number e. 2. When writing one block of data to the memory during the interleaving, the column address is added to the initial value p by a predetermined number a for each word, and the row address is added by a predetermined number e from the initial value f. The column address of the next word when the address reaches the predetermined number c is changed to the value obtained by adding the predetermined number g to the row address while keeping the predetermined number c, and then the column address is added for each word without changing the row address. A write address is generated and given to the memory by subtracting it by a predetermined number a, and when reading one block of data from the memory, the column address is set to the initial value p while keeping the row address at the initial value b. A predetermined number a is added to each word, and in the next word when the column address reaches a predetermined number c, the column address remains the predetermined number c, but the row address changes from the initial value b to the value obtained by adding a predetermined number d. let me,
Thereafter, a read address is generated and given to the memory by subtracting a predetermined number a from the column address and subtracting a predetermined number e from the row address for each word. Memory circuit described in section. 3. The memory circuit according to claim 2, wherein said b=f.