JPS58106868A - Insulated gate type field-effect semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To unnecessitate the diffusion of a P type well, and to prepare a CMOS, which is operated at high speed, the degree of integration thereof is high and which has high reliability, with excellent reproducibility, by forming the MISFET to a single crystal, which is obtained by converting polycrystalline silicon formed by previously etching an SiO2 film selectively, at the positions of source and drain regions. CONSTITUTION:Respective silicon layer 6, 7 is formed onto a substrate 1, and the source and drain regions 8, 9, 12, 13 of P and N each channel FETs are shaped into the layers, but both layers 6, 7 have the same depth and can severally be changed into N type and P type through selectively impurity diffusion. Accordingly, since the deep P type well need not be diffused and shaped, the degree of integration is improved, the impurity concentration of the P type layer 7 is easily controlled to low value particularly, the mobility of carriers is ameliorated, and speed can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an insulated gate field effect semiconductor device, special KM Engineering 8
F I T (Metal engineering n5ulator F
The present invention relates to a complementary conductor element constructed of a conductor (transistor) and a method for manufacturing the same.

Previous OM OEl (oompl, mental
According to YMO8), a deep PIIi well is formed in the In- region of an N-type silicon substrate in IpHL, a KN channel xMI8FIIITk is provided in this process, and an N
Type silicon @KP channel pbMXH1tlATt-crotch tj? I, I:+. However, it has been found that such 0M0B requires a limit in order to increase the speed and increase the number of combination points.

(1) Due to manufacturing conditions, impurities in sea urchins are 5 itt-1! k
<Conductance CgMk due to separation %A>
Or if the carrier's mobility is bad, it is difficult to plan for a high-level meeting.

(2) In connection with the bulge, the junction capacitance between the well and the diffusion region increases, resulting in a decrease in operation speed.

(3), since last year occupies a relatively large area 1,
It is difficult to raise the exe as a whole.

(4), M + xii diffusion f in Ptl1 well
il castle-P fatwell-M substrate connection and P+ of Nm substrate
Type diffusion movement range 1714 substrate-P type twell, respectively NP
M and PNP parasitic transistors are formed, and this parasitic transistor has a so-called latch-ag structure in which the PMPM resistor structure easily conducts power when an abnormal voltage is applied, and the current flows from one element to the other. This will cause the breakdown voltage to deteriorate.

Therefore, one object of the present invention is to provide a high-speed, high-integration, and high-voltage lA edge gate resin that eliminates the above-mentioned problems. ,.

Field-effect semiconductor device tII is provided by a manufacturing method capable of producing such #P-dedicated device with good reproducibility t-
I have a lot to offer.

Hereinafter, the actual jtI hook to which the present invention is applied with 10MO8 OK will be described in detail with reference to Figure gK)%A.

Regarding blind figure 1 and calculation 21, 0M0 according to this implementation
I will explain the structure of I. M@Silicon substrate 1〇-On the main surface,
A comparatively thick sto port II2.3.
4.5 is provided respectively, and a thickness of 30 is provided on this 810=ll.
00~5000AOII! 1! shinjj: yin layer 6 and p
g silicon layer 7 is formed respectively. 11, in order to separate these 9=r layers
0 is selectively formed, and the above 810
1112 to 5 are arranged in series. In M@silicon layer 6, t+maro source region 8 is placed on 1110m #2 and 3.
And Dray / 11 area 9 or form lE damn, there are many insects on the gate oxidation play 10 between these internal areas 1/91 n O gate electric @
11 is provided and v%a, -10,000, pH&l:sy layer 7 is formed with 810° horse number and 9711:, M @ drain region 12 and source region 13, and gate oxidation between these inner regions. A polycrystalline silicon gate electrode 14 is provided on the gate electrode 1110. Note that 15 is a surface oxidation layer of polycrystalline silicon, and a phosphorus silicate glass layer for interlayer insulation. Each aluminum wiring [17
, 18, 19 are provided respectively, and the summer channel M111P]
@72G and P channel AM18? 0M0B is constructed by wiring m21 in a known wiring format.

According to the 0M0IIK constructed as described above, each silicon layer 6.7 is provided on the substrate l, and each 11? The source and drain regions of both silicon layers 6 are formed.
%7 are both the same -S Now, due to selective impurity diffusion, each is M! It is possible to change the temperature and pH value. Therefore,
It is not necessary to form a deep P well t-diffusion as in the conventional structure. It's easy to move to a low contomire, and you can use Yaria's ability or the same as the above to make a sat attack, and you can make it perform a high-level attack. Moreover, in this case,
The source and drain regions are relatively thick 810III2~
1 because it is separated from the substrate 1 by 8, l1i4
[The volume of response with 1 is significantly smaller (about 1/3 of II & capacity), and the PMII association formed by each source and human region is only formed in the outer fog. As a result, the overall capacitance (parasitic capacitance) including the junction capacitance can be reduced based on the capacitance (delay time), resulting in faster operation.

In addition, unlike the conventional structure, a KP well is not formed, so there is no need to consider the area of the well or the alignment with the source and drain regions.
tt can be increased.

In addition to this, #1G is placed under each source and drain region.
, l12 to 5 exist, and the P summer seam is only made in y# of each source and drain region -1, so -
The distance between the OνIT source/drain region and the OνIT source/drain region is much longer than the known 0M0B.

Therefore, the current amplification factor hv1 of the P)TP or 121W raw transistor as described above becomes small, and the latch-up phenomenon described above is less likely to occur, so that element destruction due to breakdown voltage deterioration can be prevented.

I! rt*,! <In the above P-channel AM [Fl'J' film, since the l-type silicon 57 layer 6 and the substrate l are connected to 1-11t, carriers that do not contribute as a current flow from the silicon layer 6 to the substrate l by 1!1 It will pass through.

Therefore, the potential of the silicon layer 6 can be kept stable 1c, and its fluctuation i can be reduced. On the other hand, [1icon On 8apphir
e) According to the structure, when a KMI811 tube was formed on a sapphire substrate, carriers such as those described above in the channel image area of the WET could not pass through to the sapphire substrate, and the potential fluctuation in the channel image area became large. I end up.

The 0M0B structure shown in Figure 1 and m2tlAK is
You may also make some changes as shown in Figure 3 and 411g.

According to the diagram lllN3, if it is full, Pf Yarnel M Eng. 81
1 Te, the above 810. It is made shorter than @2.3t, and partially protrudes to the negative side of the P+ source lI region 8 and drain 9 region 91 substrate 1. Even if K is like this, the second
It can be seen that the same effect can be obtained, although the III capacity is somewhat larger than in the structure shown in the figure.

According to ll4tjlJ, Gaba P Channel M Engineering 8FM
At T, the 61° film 3Fi 2nd below the drain 1 region 9
It is set up as shown in the figure, but the source work completed 8@8101 error 2F
iK is set so that it does not form at all. In this case, the 5tol film 3 is required to eliminate the parasitic capacitance that occurs in the relationship with the substrate 1 due to the high voltage applied to the drain region 9, but in the case of the source region 8, such protection is not necessary. 8 because it is an expense
101 film 2Fi is not necessarily required. Furthermore, the drain region 9 can act as a trigger for the parasitic transistor mentioned above due to the application of a high voltage.
IIIO1aSt* and PMIII meeting Note that the presence of the 8tol film 3 in the drain region 911M makes it difficult for the depletion layer to extend from there, so the field
1 pho! It is possible to prevent the threshold line voltage Vth from decreasing by 1 and maintain it at a relatively high level, thereby satisfying the demand for higher Vth.

In addition, in FIG. 4, ff81 is indicated by a chain -.
0. Membrane 3tll! Stretch it out, and also under the source area 8
to, l[2 may be partially expanded. Also, two-point chain■
KaLO, @3f is further extended as shown in (810*1I
If you do this (without 2tl), the effect will be greater than the above.

Next, the manufacturing method of ONα8 shown in Figure 2 will be explained with reference to Figure 5, but it can be produced in the same manner as the structure shown in Figure 3 and Figure 3.

As shown in Fig. 5, M [810.
! &[[0,92 to 5' are left only at the positions corresponding to the source and drain image areas by photoetching technology, respectively.

Next, as shown in Figure IE5B, chemical vapor deposition technology (OV
D) [Therefore, a polycrystalline silicon layer 30 is placed on the entire surface.
0 to 5oooX. After that, laser annealing is performed by irradiation with a laser beam of 31t-gX/cdO energy using a ruby laser, for example, or high-temperature heat treatment in an inert atmosphere at 1000 to 1100°C for 1 to several hours. The application converts the entire polycrystalline silicon layer 30 into broom crystalline silicon. All of this oak-crystalline silicon is grown epitaxially on the substrate 1.

Next, as shown in FIG.
D810. Discipline 33 [Form IEL, further VC So (D YoK CV
8LsN in D, T-deposition field and then patterned using photoetching technology to form a stem as an oxidation-resistant mask.
Meditation s4.35151.

Then KvLOOO8(LOaa
lOXiaatiOn of 8LlioOn )techniques@
Field insulation lA (ginsg') 801 is selectively grown in the @ region other than [email protected] by thermal saponification. This field insulation 80 penetrates the single-crystal silicon layer 32 to reach the substrate IK, and the single-crystal silicon layer 32 is separated into each element region.

Then, as shown in Figure IIE51, % B1 Hatake N41134.
35 and aio*l [331 after removal by etching,
- Master (e.g. photoresist) with 3 million elements
6 a%A, if this soft wire is used, arsenic or phosphorus is introduced into the single crystal silicon layer 32 by ion implantation technology, and Nf
It is selectively formed on the f1l silicon layer 6.

Next, as in *sywJ, the other single crystal silicon layer 3
The same IIK boron as above is introduced into 2 to form the P-silicon layer 7.
After selectively forming t:al, thermally oxidize the entire i1 to form a gate insulation stow, and pattern the polycrystalline silicon grown on the entire surface by IKOVD by photoetching to form polycrystalline silicon Jll111 in the shape of a gate electrode. Form .14.

Next, as shown in FIG. 5G, a polycrystalline silicone layer i is formed by thermal oxidation.
After forming 810105 on the surface of t and ta, a thin 81s MalKaovt is deposited on the entire surface, ? ! ml' recon layer 711tff star (in case of iFI, own-sto film) 37 and next to it, in this state I, a boron ion beam 38t
- selectively implanting boron into the MfIi silicon layer 6 by irradiation; As a result, by the masking action of the polycrystalline silicon layer 11 and the field 5iOsl[8, the P+ hazy source region 8 and drain region 9 are
2 and 3 in a self-aligned manner.

Next, as shown in FIG. 6H, the pill silicon layer 7 is
Arsenic or phosphorus is selectively implanted into MII! in the same manner as above. The drain region 12 and the source 1 region tSt are formed on the above-mentioned 810×4.5, respectively. IK, mask 3
Phosphorsilicate glass 11161r was precipitated by KOVD on the entire surface of the removed fireflies, and after each contact hole was formed through the gaffs [116] by photoetching, Afnium was deposited by vacuum evaporation technique [photoetching]. Each aluminum arrangement shown in Figure 2 after buttering! 17 to 191, respectively.

Like Jin, 0M0Iil&! The Pro 7th to be constructed has several points as described below.

First, look at the knees in Figures 51 and 31151.

Convert the polycrystalline silicon 30 into single crystal silicon 32 by leaving the positions 2 to 5 in advance in the source and drain region 1, and convert this single crystal silicon 32KM.
Since the structure 811A is formed, it is fundamentally different from the conventional manufacturing method of 0M013, and there is no need for pH well diffusion, and impurities can be introduced into each single crystal silicon 32 with good control. Therefore, the high speed as mentioned above,
Highly integrated 0M08Yr with good Illability can be produced with good reproducibility.

This platform, source and drain regions are 810°11 as described above.
Since it can be selectively formed on the substrates 2 to 5, the parasitic capacitance with the substrate can be reduced. Moreover, 8LOsil12~Sa
It is only necessary to form the source and drain at the location of the drain.
These flesh areas become 1 in fortune telling as they become finely patterned! Polycrystalline silicon 3o has a long primary Kwt due to its small area.
The bonding area between the substrate 1 and the substrate 1 can be made sufficiently large. For this reason,
During single crystallization, monocrystalline silicon grows on substrate 1! This facilitates axial growth and allows the formation of a single crystalline silicon layer 32W1.

1+, since the above ato and @2 to 5 are left in advance at the source and drain region positions, FIGS. 50 to 115H (
2) LOOOEL & MI8F] In the IITO production process, it is possible to selectively form a feed insulating film for element isolation, as well as sources and drains at desired positions.

Although the present invention has been described above, the above-described implementation IFil can be further modified based on the technical idea of the present invention.

For example, the pattern 5tol@z~5 may be varied in various ways, and its thickness may also be varied within a range that can suppress parasitic capacitance. Further, the material of the gate electrode may be polycrystalline silicon, a high melting point metal such as molybdenum, tantalum, tungsten, or a silicide thereof. Further, regarding the manufacturing process 1, amorphous silicon may be deposited in place of the polycrystalline silicon 30, and this may be t-C crystallized.

These deposition methods may be vacuum evaporation techniques other than the above-mentioned OVD. In addition, in the above-mentioned case, since the special KMJII silicon layer 6 can be formed by doping impurities from the substrate 1, the impurity introduction process 1il shown in the 51st IAK is performed.
is not necessarily IflI*^. In addition, as a method for introducing each impurity, you can choose from vapor phase diffusion technology, ion implantation technology, etc. 5th AI￥l 531st? ! 5th Cr21 Fig. 5D Fig. 5E Fig. 5F Fig. 5Q Fig. t Fig. 5H

Claims (1)

[Claims] 1. An insulating film is provided on the cow guide base at least at the position where the drain region tube is to be formed, and this insulating film 11tjF
The semiconductor layer formed on the conductor substrate is separated into element regions by an insulating layer passing through the semiconductor layer in the thickness direction, and an insulated gate is formed in the element region through a predetermined element region K. An insulated gate type field effect conductor in which the source and drain active regions of the type field effect transistor are located at least above the insulation layer and the insulated gate type field effect transistor.
i*. 2. At least at the position II where the drain region tube is to be formed, the knee forming the #Ps body substrate upper body upper border membrane, and this J1
! A knee for forming a polycrystalline semiconductor layer on the conductive body substrate through the edge #, a willow for converting this polycrystalline semiconductor layer into a conductive layer, and this single crystal conductive layer. Is the coma layer t penetrated in the direction of its thickness? an impurity*1 is introduced into the front crystal conductor layer in a predetermined device image area so that at least the drain region is located at least above the insulating film; A method for manufacturing an insulated gate field effect semiconductor device, characterized in that the tube has source and drain regions vc* and l1 formed by h.