JPH09281933A - Data driver and liquid crystal display device and information processing device using it. - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device which realizes a multi- gradation display and a moving video picture display which reducing the power consumption and the cost. SOLUTION: Still-frame picture data are transferred from the CPU 304 to memory in a data driver 307 (307-1 to 307-4). Moving video picture data which require multi-gradation display are processed by a moving video picture driver 311 and sent to the data driver 307 through a panel 302. The regions of still- frame picture and moving picture in a liquid crystal panel 309 are preset in a register. In the still-frame picture display region, a selector selects the still- frame picture data sent from the memory. In the moving picture display region, the selector selects the moving picture data sent from the bus 302. The register, the latch, and the liquid crystal drive circuit impresses liquid crystal drive voltage on the data line of the liquid crystal panel 309 based on the data outputted by the selector.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driver, a liquid crystal display device using the same, and an information processing device.

[0002]

2. Description of the Related Art Liquid crystal display devices are strongly desired to have low power consumption not only for improving display quality but also for mounting in portable equipment. Therefore, the display memory is built into the data driver LSI, and the access frequency to the memory storing the display data is reduced to reduce the power consumption. Hereinafter, such a conventional liquid crystal display device will be described with reference to FIGS. 18, 19, and 20.

FIG. 18 is a system block diagram using a conventional liquid crystal driver with a built-in memory, FIG. 19 is a main block diagram of a liquid crystal display device, and FIG. 20 is a detailed block diagram of a liquid crystal driver with a built-in memory. Shown here is a liquid crystal display device which drives a liquid crystal panel 109 of 320 × 480 dots by using four 160-output data driver LSIs 107.

In FIG. 18, reference numeral "101" is an address bus. Similarly, “102” is a data bus, “103” is a control signal line, “104” is a CPU, and “1”.
"05" is a memory, "106" is an I / O device, and "10"
7-1 "to" 107-4 "are data driver LSIs having a built-in display memory," 108 "is a scanning circuit, and" 109 ".
Is a liquid crystal panel, and "110" is a signal line for a display synchronization signal. The data driver LSI 107-1 to
The data driver LSI1 is simply referred to as 107-4.
Sometimes called 07.

In FIGS. 19 and 20, reference numeral "201"
The display oscillator circuit is marked with. Similarly, "20
2 "is a power supply circuit of the liquid crystal driver," 203-1 "to" 2 "
03-4 "is a data driver LSI 107-1 to 107
-4 is a signal line for transmitting a control signal indicating the arrangement position. Hereinafter, the control signals 203-1 to 203-4 may be collectively referred to simply as the control signal 203. "20
4 "is a signal line for transmitting a display control signal," 20 "
5 "is a line for supplying the power supply voltage for the scanning circuit," 2 "
“06” indicates a line for supplying a power supply voltage for the data driver LSI 107. “207” indicates a control signal 2
03 is an address management circuit for performing address control, “208” is a signal line for transmitting a column address obtained by address control by the address management circuit 207, and “209” is an address address management circuit 20.
7, a signal line for transmitting the row address of the display memory that has been subjected to address control, “210” is a timing control circuit for generating various control signals inside the data driver LSI 107 based on the control signal 103, and “211” is a display A signal line for transmitting a control signal for controlling the input / output of data, "212" for transmitting a control signal for controlling the row address 218 for display, and "213" for controlling the selector 221. A signal line for transmitting a control signal, "214" is a signal line for transmitting a latch signal, "215" is a signal line for transmitting a control signal for controlling alternating current of liquid crystal driving, and "217" is A display address counter that generates a display address, “218” is a signal line for transmitting a row address for display, and “219” is a bidirectional control of data. I / O buffers, "220" points to data bus for transmitting data. "2
21 "is the display address and the system (CPU 10
, Etc.), a selector for selecting any one of the addresses sent from (4 etc.), “222” indicates a signal line for transmitting a row address selected and output by the selector 221. "223" is the column address decoder, "22"
4 ”is a signal line for transmitting the selection signal generated by the column address decoder 223, and“ 225 ”is the display memory 2.
29 data selectors, “226” is the display memory 229
Refers to the data bus. “227” indicates a row address decoder. “229” is a display memory (memory cell, RAM) holding display data, “230” is a display data bus from the display memory 229, “231” is a signal line for transmitting a control signal for controlling FRC data, “232” is an FRC data circuit that generates FRC data, “233” is a signal line for transmitting FRC data, and “234” is the FRC corresponding to the display data 230.
FRC selector for selecting data, "235" is FRC
A data bus for transmitting display data selected by the selector 234, "236" and "238" are latch circuits for latching display data, "237" and "239" are display data buses, and "240" is display data. A liquid crystal drive circuit that generates a liquid crystal drive voltage based on "241" indicates a line for supplying the liquid crystal drive voltage.

In the present specification, signals, data, etc. may be referred to with reference numerals attached to signal lines and buses for transmitting the signals. For example, the display synchronization signal transmitted through the signal line 110 may be referred to as “display synchronization signal 110”. Further, the display data transmitted via the display data bus 235 may be referred to as “display data 235”.

The driving operation of this liquid crystal display device will be described with reference to FIG.

The display data is drawn from the memory 105 or the I / O device 106 to the display memory of the data driver LSI 107 under the control of the CPU 104. The drawing operation of the display data from the memory 105 to the data driver LSI 107 is performed as follows.

The CPU 104 outputs a read address and a control signal to the memory 105 to temporarily fetch the data of the memory 105 into a register of the CPU 104, and executes a read cycle. Subsequently, the CPU 104 outputs a write address and a control signal to the data driver LSI 107 to write the data once stored in the register of the CPU 104 into the display memory of the data driver LSI 107, and executes a write cycle. CPU 104
By repeating this operation, the display data of the memory 105 is transferred to the display memory of the data driver LSI 107 to update (draw) the display data.

Further, the detailed operation of the data driver LSI 107 will be described with reference to FIGS.

Each data driver LSI 107 has its layout position set with respect to the liquid crystal panel 109 by a control signal 203 indicating the layout position of the panel.

Therefore, the four data driver LSIs 107 determine which of the four data driver LSIs 107 is being accessed with respect to the address from the CPU 104 based on the control signal 203. Upon receiving the write address from the CPU 104, the address management circuit 207 determines whether or not the address is the address that the data driver LSI 107 to which it belongs is in charge. If the result of the determination is that the address is for the data driver LSI 107 to which it belongs, that address is converted to an address (column address 208, row address 209) in the display memory 229, and this is converted to the column address decoder 223, selector. Two
21.

In the write cycle from the CPU 104, the selector 221 selects the row address 209 and outputs it to the row address decoder 227. Then, the row address decoder 227 selects the gate line of the display memory 229 corresponding to the address. On the other hand, the column address decoder 223 selects the data line of the display memory 229 by enabling the data selector 225 corresponding to the column address 208. This gives I /
The write data 220 from the O buffer 219 can be written to a predetermined address in the display memory 229. The display data is updated (drawn) by repeating the above operation.

The display memory 229 holds display data of 1 screen × 2 bits (4 gradations).

When reading the display data from the display memory 229, the selector 221 selects the row address (display address) 218 generated by the display address counter 217.
Select As a result, the display address 218 at that time is displayed.
The display data of the address specified by
The C selector 234 sequentially reads one line at a time. This reading is performed in synchronization with the horizontal synchronizing signal. The FRC selector 234 uses the read display data as the 1-bit display data 235 and latch circuit 23.
6 is output. This display data 235 is stored in the latch circuit 2
36 and 238, the display data 237 and 239 are sequentially transferred and input to the liquid crystal drive circuit 240.
The liquid crystal drive circuit 240 generates a liquid crystal drive voltage 241 corresponding to the display data 239 and drives the liquid crystal panel 109.

In synchronization with this, the scanning circuit 108 sequentially enables the gate lines of the liquid crystal panel 109 line by line. As a result, the display is performed.

Here, the latch circuit is constructed in two stages (latch circuit 236, latch circuit 238), and the operation timing of each is controlled by the latch signals 214, 215, so that access from the CPU 104 (display memory 229) is possible. Write to) and display operation (display memory 22)
Arbitration operation is performed when there is a conflict with (reading from 9).

[0018]

By the way, in recent years, with the development of multimedia technology, display of moving images has been required. In order to display a moving image, practically, multi-gradation display of 32 gradations or more is essential. In order to display 32 gradations per pixel, display data of 5 bits per pixel is required. In order to realize this with the above-mentioned conventional technique, it is necessary to increase the capacity of the memory built in the data driver LSI.

However, when the capacity of the built-in memory is increased, the chip size is increased and it is difficult to reduce the cost. Further, the drawing data of the moving image needs to be updated for 30 frames or more per second, but for that purpose, the data must be transferred for each frame, and high-speed rewriting of the memory is essential. As the number of gradations increases, the amount of data also increases. Therefore, the number of gradations also increases. Therefore, rewriting is required to be faster. Such speedup leads to an increase in power consumption. As described above, it is difficult for the conventional technology to realize both low power consumption and low cost.

It is an object of the present invention to provide a data driver capable of displaying moving images while realizing low cost and low power consumption, and a liquid crystal display device and an information processing device using the data driver.

[0021]

According to the present invention, a moving picture controller is provided separately from the data driver, and processing for moving picture processing and liquid crystal multi-gradation display is performed here. The data processed through the display memory in the data driver is used for displaying the still image. On the other hand, the data sent from the moving image controller is used for displaying the moving image. By switching and using both depending on the display area, it is possible to cope with a moving image without increasing the power consumption and the capacity of the display memory. That is, the access frequency of the display memory can be slowed down for a still image whose display screen does not change (if the display memory is read out line by line, the display memory can be accessed only once in the horizontal period). On the other hand, in moving image display, it is not necessary to increase the display memory capacity built in the data driver by causing the moving image controller to perform the processing. Further, since the moving image controller performs gradation control processing, the number of gradation display is not limited only by the data driver. If the gradation control by the data driver and the gradation control by the moving image controller are combined, the number of gradation display can be increased.

The structure of the present invention will be described in more detail below.

According to a first aspect of the present invention, in a data driver for outputting a liquid crystal drive voltage applied to a data line of a liquid crystal panel according to display data input from the outside, data to which the display data is input from the outside A bus, an address bus to which an address is input from the outside, a display memory for storing display data, and an output bus for outputting the data read from the display memory,
The display data input through the data bus is temporarily stored in an area on the display memory that is determined based on the address input through the address bus, and then the display data stored in the display memory is separately determined. A data processing system for sequentially reading and outputting through the output bus, a selection means for selecting one of the output bus of the data processing system and the data bus, and a bus selected by the selection means. And a voltage output means for outputting a liquid crystal drive voltage according to the data transmitted through the data driver.

The selecting means stores a selection information serving as a selection reference, an instruction circuit for outputting a selection instruction according to the selection information, and the data bus or the data according to an instruction from the instruction circuit. It is preferable that it is configured to include a selector that selects one of the output buses of the processing system.

The selection information defines a region on the liquid crystal panel, and the instruction circuit sends data to be output to the region defined by the selection information through the data bus. It is preferable to issue an instruction to select the data bus during the incoming period, and to issue an instruction to select the output bus of the data processing system at other times.

The selection information may define an area for displaying a moving image on the liquid crystal panel.

The data processing system first controls gradation based on the display data read from the display memory.
The gradation control circuit may be provided, and the data after gradation control by the first gradation control circuit is output through the output bus.

The first gradation control circuit may perform the gradation control by an FRC method.

The voltage output means has a second gradation control circuit for performing gradation control based on the data sent through the bus selected by the selection means. A voltage obtained by gradation control by the gradation control circuit may be output as the liquid crystal drive voltage.

The second gradation control circuit may perform the gradation control by a PWM system or an AM system.

As a second aspect of the present invention, the data driver of the above-mentioned first aspect and a data controller for processing display data are provided, and the data controller outputs the result of the above-mentioned data through the data bus. Is provided to the data driver, and a liquid crystal display device is provided.

The data controller includes a third gradation control circuit for performing gradation control on display data, and outputs the data obtained by the gradation control by the third gradation control circuit. Preferably there is.

The third gradation control circuit may perform the gradation control by the FRC method.

At least two of gradation control by the first gradation control circuit, gradation control by the second gradation control circuit, and gradation control by the third gradation control circuit. Grayscale display may be performed by combining the two.

A third aspect of the present invention is the above-mentioned second aspect.
There is provided an information processing device comprising the liquid crystal display device according to the aspect.

The operation of each of the above-mentioned modes will be described collectively.

In the data processing system, the display data input through the data bus is temporarily stored in the display memory. The storage area at this time is determined based on the address input through the address bus. Then, the display data stored in the display memory is read out in a separately determined order and output through the output bus. When the data processing system has the first gradation control circuit, the output bus has gradation control by the first gradation control circuit for the display data read from the display memory ( For example, the data after the gradation control by the FRC method) is performed is output.

The data controller outputs the result of processing the display data to the data driver through the data bus. If the data controller has a third gradation control circuit, gradation control by this third gradation control circuit (for example, gradation control by FRC method)
Output the data obtained by.

The selecting means is an output bus of the data processing system,
Either the data bus or the data bus is selected. This selecting means can be realized by the selector selecting either the data bus or the output bus of the data processing system in accordance with the selection instruction output from the instruction circuit according to the selection information.
If the selection information defines an area (for example, a moving image display area) on the liquid crystal panel, the instruction circuit determines that the data to be output to the area defined by the selection information is transmitted via the data bus. During the period sent from the data controller, it issues an instruction to select the data bus. In other cases, an instruction to select the output bus of the data processing system is issued.

The voltage output means outputs a liquid crystal drive voltage according to the data sent through the bus selected by the selecting means. When the voltage output means has the second gradation control circuit, the gradation control by the second gradation control circuit (for example, PWM method or AM) is performed on the input data. The voltage obtained by performing the gradation control according to the method is output as the liquid crystal drive voltage.

[0041]

Embodiments of the present invention will be described with reference to the drawings.

A liquid crystal display device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 5 and 10 to 15.

First, the outline will be described with reference to FIG.

This liquid crystal display device includes a liquid crystal panel 309 of 320 × 480 pixels and a data driver LSI 307-.
1 to 307-4, the scanning circuit 308, the moving image controller 311, the CPU 304, the memory 305, and the I / O.
And a device 306. Then, these units are connected by an address bus 301, a data bus 302, a control signal line 303, and a display synchronization signal line 310. In the following description, the data driver LSIs 307-1 to 307-4 may be collectively referred to simply as “data driver LSI 307”. In addition, in the present specification, a signal may be referred to with a reference numeral of a signal line that transmits the signal. For example, the display synchronization signal sent through the display synchronization signal line 310 may be referred to as the “display synchronization signal 310”.

The CPU 304 receives the data driver LSI 307 through the address bus 301 and the data bus 302.
The built-in display memory can be accessed directly. Similarly, the moving image controller 311 can access the data driver LSI 307 through the address bus 301 and the data bus 302. As a result, in this liquid crystal display device, for still image data, the display data is updated (drawn) by the CPU 304 and the memory 305. On the other hand, the moving image data is output from the moving image controller 311 to the data driver LSI 307.
The data driver LSI 307 internally includes information indicating the moving image display area, and according to the information, the CP
The display data (still image data) sent from the U304 or the like and the display data (moving image data) sent from the moving image controller 311 are switched to switch the liquid crystal panel 30.
It is designed to output to 9.

The structural feature for realizing such an operation is mainly in the data driver LSI 307.
Therefore, hereinafter, the description will be focused on the data driver LSI 307.

Each data driver LSI 307 includes a display memory (memory cell 433) having a capacity capable of holding 2-bit display data of each pixel for 160 outputs and 240 lines. Therefore, one data driver LSI 307 is used to drive a liquid crystal panel with 160 × 240 pixels.
It can be displayed in gradation. 32 for the liquid crystal panel 309
This data driver LSI has 0x480 pixels.
Two 307 are arranged in the upper and lower parts (four in total), and 24
It is designed to perform two-screen drive for each 0 line.

As shown in FIGS. 2 and 3, the data driver LSI 307 includes an address management circuit 408, a timing control circuit 411, an I / O buffer 419, a display address counter 421, a selector 423, a row address decoder 425, and an FRC data circuit 427. , Column address decoder 429, data selector 431, memory cell 43
3, FRC selector 435, selector 437, shift register 439, latch circuit 441, liquid crystal drive circuit 443
It has. In addition, various signal lines and buses 42 for connecting these respective units (or other circuit units)
0, 432, 434, 442 and the like.

2 and 3, the oscillator circuit 402 and the power supply circuit 4 which are not shown in FIG. 1 are omitted.
04 is also drawn.

The address management circuit 408 controls the control signal 30.
The address 301 is converted into a column address 409 and a row address 410 based on 3, 401. The address management circuit 408 uses the column address 409.
To the column address decoder 429 and the row address 410 to the row address decoder 425 via the selector 423. The control signal 401 is 4
It is for designating which one of the data driver LSIs 307 is the access target at that time.

The timing control circuit 411 controls the control signal 3
03 and display synchronization signal 310 to data driver LS
Various control signals 412, 413, 414, inside I307
415, 416, 417, 418, 445 are generated. Of these control signals, the control signal 412 is output to the I / O buffer 419. Control signal 41
3 is output to the display address counter 421.
The control signal 414 is output to the selector 423.
The control signal 415 is output to the FRC data circuit 427. The shift clock 416 is the shift register 439.
Is output to The latch signal 417 is the latch circuit 4
It is output to 41 and is used to control the timing of latching the display data. Control signal 418
Is output to the liquid crystal drive circuit 443 and is used to control the alternating current of the liquid crystal drive. Control signal 445
Are output to the selector 437.
Two data buses (data bus 43
6, data bus 302) is used to select either one. The timing control circuit 411
Also, the above-mentioned control signal 401 is input.

The timing control circuit 411 includes a register 4110 in which information indicating a region where a moving image is displayed on the liquid crystal panel 309 is stored. In addition, at that time, the timing control circuit 411 is set to the liquid crystal panel 30.
A row address 422 indicating which display line corresponding to the 9th line from which the display data should be read from the memory cell 433 is input. The control signal 445 is generated based on the contents of the register 4110 and the row address 422. That is, the display data 3 is displayed in the moving image display area.
02 (moving image data sent from the moving image controller 311) while displaying data 436 in the still image display area.
A control signal 445 is generated so that the selector 437 selects (still image data). Such a point is the most characteristic point of this embodiment.

The I / O buffer 419 receives the control signal 412.
According to the above, the input / output of the display data 302, 420 is controlled.

The display address counter 421 is for generating a display row address 422 in accordance with the control signal 413. The display address counter 421 outputs the row address 422 to the timing control circuit 411 and the selector 423.

The selector 423 selects either the display row address 422 or the drawing row address 410 according to the control signal 414. The selector 423 outputs the selected one as a row address 424 to the row address decoder 425.

The row address decoder 425 decodes the row address 424 to generate a word selection signal 426 and outputs it to the gate line of the memory cell 433.

The column address decoder 429 is for generating the selection signal 430 based on the column address 409. The column address decoder 429 outputs this selection signal 430 to the data selector 431.

The data selector 431 has a selection signal 430.
By selecting the data line of the data bus 432 of the memory cell 433 according to the above, the input / output of the display data 420 to / from the memory cell 433 is controlled.

The memory cell 433 is a memory for temporarily storing display data (still image data) and is composed of a RAM. The area of the memory cell 433 to which the display data is written / read can be designated based on the above-mentioned column address and row address. As described above, the memory cell 433 of this embodiment stores 16-bit display data of 2 bits for each pixel.
It has the capacity to hold 0 output and 240 lines.

The FRC data circuit 427 and the FRC selector 435 are for performing gradation display by the FRC system. As shown in FIG. 15, the FRC gradation method is a method of displaying the brightness of an intermediate gradation by changing the applied voltage (that is, display brightness) for each frame (in the example of FIG. Display brightness is changed with even frames). The FRC data circuit 427 is
The FRC data 428 necessary for performing gradation display by the gradation method is generated. The generation timing of the FRC data 428 is determined according to the control signal 415. The FRC selector 435 performs a process (FRC control) of selecting 1 bit of FRC data corresponding to the display data 434 of 2 bits per pixel. The FRC selector 435 outputs the data generated by the FRC control to the selector 437 as the display data 436.

The selector 437 selects either the display data 436 (still image data) or the display data 302 (moving image data) input from the moving image controller 311 according to the control signal 445. . That is, in the present embodiment, the data bus 302
Two routes are provided before the display data sent through the selector reaches the selector 437. The first route is the I / O buffer 41 after the data bus 302.
9, data selector 431, memory cell 433, FRC
Selector 4 through selector 435, data bus 436
It is a route to 37. The second route is a route in which the data bus 302 is directly connected to the selector 437 without passing through the memory cell 433 or the like. During the period in which the display data for the area preset as the moving image display area is to be input, moving image data is input to the data bus 302 from the moving image controller 311. On the other hand, still image data is being input to the data bus 302 from the CPU 304, the memory 305, and the like during a period in which display data for an area that has been set in advance as a still display area should be input. Therefore, the selector 43
7, by selecting one of the data bus 436 and the data bus 302 according to the control signal 445, one of two routes from the data bus 302 to the selector 437 can be selected according to the display data. It is like this. The selector 437 outputs the thus selected one to the shift register 439 as display data 438.

Note that the selector 437 in this embodiment is used.
FIG. 4 shows a specific internal structure of the above.

The shift register 439 is an 8-bit bidirectional shift register, and has a shift clock (control signal) 4
It operates according to 16.

The latch circuit 441 latches the display data 440 according to the control signal 417 (that is, in synchronization with the display selection signal 407 of the scanning circuit 308).
The latch circuit 441 outputs the latched data to the liquid crystal drive circuit 443 as display data 442.

The liquid crystal drive circuit 443 displays the display data 442.
The liquid crystal drive voltage 444 is generated corresponding to

The oscillation circuit 402 generates the display clock 403 for defining the display timing, and the scanning circuit 308.
Is to be supplied to.

The power supply circuit 404 generates and supplies a liquid crystal panel drive voltage (power supply voltage 405 for the scanning circuit 308, power supply voltage 406 for the data driver LSI 307).

Next, the display operation in this embodiment will be described.

The description will be divided into a still image display operation and a moving image display operation.

[Still image display operation] Regarding still images,
The CPU 304 reads (read-accesses) the display data in the memory 305, and the data is read by the data driver LSI 3
Writing to the memory cell 433 of 07 (write access)
As a result, the display data is updated (drawn). Memory 4
Access to 33 is performed randomly. At this time,
The access of the CPU 304 is performed by the SRAM interface. The read / write timing of the SRAM interface is shown in FIGS. Of the signals shown in FIGS. 10 and 11, the address signal is transmitted through the address bus 301. The data signal is sent to the data bus 30.
2 is transmitted. Other signals are included in the control signal 303.

Hereinafter, the display data is written into the memory cell 433 of the data driver LSI 307, and the memory cell 4 is read.
The reading of the display data from 33 will be described.

First, writing of display data to the memory cell 433 will be described.

The read / write address from the system (CPU 304 etc.) is input to the address management circuit 408 of the data driver LSI 307 through the address bus 301. The address management circuit 408 of each data driver LSI 307 accesses the data driver LSI to which it belongs based on the control signal 401.
It is determined whether or not it is for 307. As a result of the determination, if the access is to the data driver LSI 307 to which the device belongs, the address 301 input at this time is used as the column address 409 and the row address 41.
Convert to 0.

The column address decoder 429 decodes this column address 409. Data selector 4
31 selects the data line of the corresponding address based on this decoding result.

On the other hand, the selector 423 selects the row address 4
10 is selected and output as a row address 424 to the row address decoder 425. Row address decoder 42
5 decodes this row address 424, and selects one gate line according to the decoding result. Thereby, the CP
The U 304 can access a predetermined bit on the memory cell 433 determined by the data line and the gate line selected at that time and transfer the display data to a predetermined address.

Next, reading of display data (display operation) from the memory cell 433 will be described.

The FRC selector 435 is connected to the memory cell 43.
The display data (data of 2 bits for each pixel for 1 line) held in 3 is converted into 1-bit FRC data 436.

By the way, the timing control circuit 411 is
By confirming the contents of the register 4110 and the row address 422, it is known that the still image area is being displayed at this time. Therefore, the timing control circuit 411
At this time, the control signal 445 outputs a value such that the selector 437 selects the data bus 436. The selector 437 follows the control signal 445,
The data bus 436 is selected, and the FRC data sent through the data bus 436 is output as the display data 438.

The shift register 439 displays the display data 43.
Latch 8 in the horizontal cycle. Following this, the latch circuit 4
41 latches the display data 440 output from the shift register 439 in the next horizontal cycle, and the liquid crystal drive circuit 443.
Output as display data 442. Liquid crystal drive circuit 44
3 is a liquid crystal drive voltage 4 corresponding to the display data 442.
44 is selected and output to the liquid crystal panel 309. The output of the liquid crystal drive voltage 444 is output in synchronization with the scan selection voltage 407 generated by the scan circuit 308, and thus display of one line of the liquid crystal panel 309 can be realized.

By repeating the above operation, a still image can be displayed.

[Movie Display Operation] When displaying a movie, multi-gradation display and high-speed transfer of display data are actually required. Data driver LSI 307 of this embodiment
Performs the following drawing operation to deal with this.

The moving image data is expanded from the compressed moving image data by the moving image controller 311 and the CPU 304 into the display data. The moving image controller 311 performs FRC control on the expanded display data.

By the way, the moving image controller 311 also includes a register (control register circuit 505 in FIG. 5, which will be described later) that stores information indicating the moving image area. By confirming the contents of this register, the moving image controller 311 can know whether or not the target of the display processing at that time is the moving image display area. If the target of display processing at that time is the video display area,
The moving image controller 311 performs the above-mentioned FRC control.
Then, the 1-bit FRC data obtained as a result is
The data of one line is sequentially sent to the data driver LSI 307 through the data bus 302.

Similarly, the timing control circuit 411 of the data driver LSI 307 also confirms the contents of the register 4110 and the row address 422 to know that the display processing target at that time is the moving image display area.
Therefore, the timing control circuit 411 sets the control signal 445 at this time to a value such that the selector 437 selects the data bus 302. As a result, the selector 437
The FRC data sent from the video controller 311 via the data bus 302 is selected, and the shift register 4 is selected.
39 to output. After this, the liquid crystal drive voltage 444 based on the FRC data is processed in the same manner as in the case of a still image.
Will be output.

Next, the timing of moving image data transfer from the moving image controller 311 to the data driver LSI 307 and the processing timing of this moving image data in the data driver LSI 307 will be described in more detail with reference to FIGS. 12, 13 and 14. explain.

In the description here, the timing control circuit 4
In the register 4110 of 11, the area (n <m) from the n line to the m line of the liquid crystal panel 309 is set as the moving image display area (see FIG. 12).

The moving image display data passes from the moving image controller 311 to the data driver LSI 3 through the data bus 302.
One line is serially transferred every 07. FIG.
3, CL1 is a sync signal representing a horizontal period and is a signal included in the display sync signal 310 (see FIGS. 2 and 3).

The timing control circuit 411 uses the CL1
Is output to the display address counter 421 as a control signal 413. The display address counter 421 counts the control signal 413 (CL1) and outputs the count value to the selector 423 as a display row address 422.

The selector 437 switches its selected state according to the control signal 445. The selected state is
It has the following relationship with the count value of the display address counter 421. That is, when the count value of the display address counter 421 is n−1 (when it is not the moving image display area), the selector 437 causes the data bus 436 (that is, the n−1 line stored in the memory cell 433). The FRC data obtained based on the eye display data) is selected. When the count value of the display address counter 421 is n (in the moving image display area), the selector 437
Is the data bus 302 (that is, the video controller 31
The display data sent from 1) is selected. Thus, the selector 437 selects the data bus 302 (display data from the moving picture controller 311) in the moving image display area, and selects the display data of the memory cell 433 in the areas other than the moving image display area.

The operation of the moving image controller 311 is also as follows.
The following relationships are associated with the operations of the selector 437 and the display address counter 421. That is, the display counter 421
When counting (n-1), the video controller 3
11 sequentially transfers the display data of the nth line.

In the data driver LSI 307,
The shift register 439 fetches the data of the nth line (for one line) sent from the moving image controller 311 at the timing shown in FIG. That is, the shift register 439 sequentially fetches the display data 438 (data of the nth line sent from the moving image controller 311) for one line by the shift clock 416 synchronized with the WE signal (Note: as described above. At this time,
The selector 437 is in a state where the data bus 302 is selected). The display data is transferred from the moving image controller 311 in synchronization with the WE signal (write enable signal) in FIG. The shift register 439 transfers the data taken in at such timing to the latch circuit 441 as the display data 440.

The latch circuit 441 latches the display data 440 in synchronization with the next CL1 signal and outputs the display data 4
The data is transferred to the liquid crystal drive circuit 443 as 42 (see FIG. 13). The liquid crystal drive circuit 443 generates and outputs a liquid crystal drive voltage 444 according to the display data 442. The output of the liquid crystal drive voltage 444 is output in synchronization with the scan selection voltage 407 generated by the scan circuit 308, and thus display of one line of the liquid crystal panel 309 can be realized.

By repeating the above operation, a moving image can be displayed.

The moving image controller 311 will be described with reference to FIG.

The moving image controller 311 expands compressed data such as MPEG and reproduces display data. As shown in FIG. 5, the moving image controller 311 includes a timing control circuit 501 and an I / O that controls input / output.
An O control circuit 502, an address control circuit 503, a moving image processing circuit 504, a control register circuit 505, and an FRC control circuit 506 are provided. Also, signal lines 507, 508, 509, 510, 511, 512, address buses 513, 514, data buses 515, 51 connecting these respective units.
6,517,518,519,520.

The I / O control circuit 502 is connected to the data bus 30.
Input / output of data signal through 2, address bus 301
The input / output of the address signal is controlled through. I /
The O control circuit 502 outputs the compressed data input through the data bus 302 to the moving image processing circuit 504. Further, the address signal input through the address bus 301 is output to the address control circuit 503.

The moving picture processing circuit 504 performs processing such as decompression, reproduction of input compressed data, and scaling adapted to the display size. Then, the display data obtained by the processing is output to the FRC control circuit 506. FRC
The control circuit 506 converts this display data into FRC data. Thereafter, the FRC data is returned to the I / O control circuit 502 through the moving image processing circuit 504 again.

The control register circuit 505 stores information indicating the moving image display area set at that time.
The I / O control circuit 502 confirms the contents of the control register circuit 505 to know whether or not the display process for the moving image area is being performed at that time. Then, the FRC data is output through the data bus 302 only when the display process for the moving image area is being performed. Data driver LS
The relationship with the operation timing of I307 is as shown in FIGS. 13 and 14 described above.

Regarding the operation timing of each part in the moving image controller 311, the timing control circuit 501 controls the control signal 30.
Various control signals 507, 50 generated and output based on 3
8, 509, 510, 511. Address management is performed by the address control circuit 503.
Has been made by

As described above, in the liquid crystal display device of this embodiment, the memory cell 433 included in the data driver LSI 307 is used only for displaying a still image. for that reason,
It is not necessary to rewrite the memory cell 433 at high speed, and low power consumption can be achieved. Further, the FRC control for gradation display in moving image display is performed by the moving image controller. Therefore, it is possible to easily realize multi-gradation moving image display (32 gradations in this embodiment) without increasing the memory capacity of the data driver LSI 307.

A liquid crystal display device according to a second embodiment of the present invention will be described with reference to FIGS. 6, 7, 10 to 14 and 16.

In the second embodiment, a pulse width modulation method (PWM method) is used as the gradation method.

The overall structure of this liquid crystal display device is the same as that of the first embodiment (see FIG. 1) except that the data driver 900 is used instead of the data driver 307. The feature of the second embodiment is mainly in the data driver LSI 900. Therefore, hereinafter, the description will be focused on the data driver LSI 900.

Each data driver LSI 900 has a display memory (memory cell 933) having a capacity capable of holding 2-bit display data of each pixel for 160 outputs and 240 lines. Therefore, one data driver LSI 900 can be used to create a liquid crystal panel with 160 × 240 pixels.
It can be displayed in gradation. 32 for the liquid crystal panel 309
This data driver LSI has 0x480 pixels.
Place two 900s each on the top and bottom (4 in total), and place 24
It is designed to perform two-screen drive for each 0 line.

As shown in FIGS. 6 and 7, the data driver LSI 900 includes an address management circuit 908, a timing control circuit 911, an I / O buffer 919, a display address counter 921, a selector 923, a row address decoder 925, and a column address decoder 929. , Data selector 931, memory cell 933, selector 937, shift register 939, latch circuit 941, liquid crystal drive circuit 9
43. Also, between these parts (or
Various signal lines for connecting (to other circuit parts), bus 9
20,932,934,942 etc. are provided.

6 and 7, the oscillator circuit 402 and the power supply circuit 9 not shown in FIG. 1 are omitted.
04 is also drawn.

The address management circuit 908 uses the control signal 30
The address 301 is converted into a column address 909 and a row address 910 based on 3, 901. The address management circuit 908 uses the column address 909.
To the column address decoder 929 and the row address 910 to the row address decoder 925 via the selector 923. The control signal 901 is 4
It is for designating which one of the data driver LSI 900 is the access target at that time.

The timing control circuit 911 controls the control signal 3
03 and display synchronization signal 907 to data driver LS
Various control signals 912, 913, 914 inside I900
916, 917, 918, 927, 945 are generated. Of these control signals, the control signal 912 is output to the I / O buffer 919. Control signal 91
3 is output to the display address counter 921.
The control signal 914 is output to the selector 923.
The control signal (shift clock) 916 is the shift register 9
It is output to 39. Control signal (latch signal) 917
Is output to the latch circuit 941 and is used to control the timing of latching the display data.
The control signal 918 is output to the liquid crystal drive circuit 943 and is used to control the alternating current of the liquid crystal drive.
The control signal 927 is output to the liquid crystal drive circuit 943 and is used to control the timing of pulse width modulation. The control signal 945 is output to the selector 937, and is used by the selector 937 to select one of the two data buses (data bus 436 and data bus 302) connected to the selector 937. There is. The above-mentioned control signal 901 is also input to the timing control circuit 911.

The timing control circuit 911 includes a register 9110 which stores information indicating a region where a moving image is displayed on the liquid crystal panel 309. Further, at that time, the timing control circuit 911 includes the liquid crystal panel 30.
A row address 922 indicating the display data corresponding to which line on the display cell 9 should be read from the memory cell 933 is input. The control signal 945 described above is generated based on the contents of the register 9110 and the row address 922. That is, the control signal 945 causes the selector 937 to select the display data 302 (moving image data sent from the moving image controller 311) in the moving image display area and the display data 934 (still image data) in the still image display area. Is being generated. Such a point is the most characteristic point of this embodiment.

The I / O buffer 919 receives the control signal 912.
According to the above, the input / output of the display data 302, 920 is controlled.

The display address counter 921 generates a display row address 922 in accordance with the control signal 913. The display address counter 921 outputs this row address 922 to the timing control circuit 911 and the selector 923.

The selector 923 selects either the display row address 922 or the drawing row address 910 according to the control signal 914. The selector 923 outputs the selected one as a row address 924 to the row address decoder 925.

The row address decoder 925 decodes the row address 924 to generate a word selection signal 926 and outputs it to the gate line of the memory cell 933.

The column address decoder 929 generates a selection signal 930 based on the column address 909 output from the address management circuit 908. The column address decoder 929 sends this selection signal 930 to
It is output to the data selector 931.

The data selector 931 has a selection signal 930.
By selecting the data line of the data bus 933 of the memory cell 933 according to the above, the input / output of the display data 920 to / from the memory cell 933 is controlled.

The memory cell 933 is a memory for temporarily storing display data (still image data) and is composed of RAM. The area on the memory cell 933 to which the display data is written / read can be designated based on the above-mentioned column address and row address. As described above, the memory cell 933
Displays the output data of 2 bits for each pixel by 160 outputs, 24
It has enough capacity to hold 0 lines.

The selector 937 selects either one of the display data 934 (still image data) and the display data 302 (moving image data) input from the moving image controller 311 according to the control signal 945. . That is, in the present embodiment, the data bus 302
Two routes are provided until the display data sent through the selector reaches the selector 937. The first route is the I / O buffer 91 after the data bus 302.
9, a data selector 931, a memory cell 933, and a data bus 934 to reach the selector 937. The second route is a route in which the data bus 302 is directly connected to the selector 937 without passing through the memory cell 933 or the like. During the period in which the display data for the area preset as the moving picture display area is to be input, the moving picture controller 31 is connected to the data bus 302.
Video data is input from 1. On the other hand, during the period in which the display data of the area preset as the still display area is to be input, the data bus 302 has a C
Still image data is input from the PU 304, the memory 305, and the like. Therefore, the selector 937 selects either one of the data bus 934 and the data bus 302 according to the control signal 945, whereby the data bus 3
Any of two routes from 02 to the selector 937 can be selected according to the display data. The selector 937 outputs the selected data as the display data 938 to the shift register 939.

The selector 937 in the present embodiment.
The specific internal configuration of the above may be the same as that of the selector 437 in the first embodiment (see FIG. 4).

The shift register 939 is an 8-bit bidirectional shift register, and operates according to the control signal 916.

The latch circuit 941 latches the display data 940 according to the control signal (latch signal) 917 (that is, in synchronization with the scanning selection signal 903 of the scanning circuit 902). The latch circuit 941 outputs the latched data to the liquid crystal drive circuit 943 as display data 942.

The liquid crystal drive circuit 943 uses the pulse width modulation method to drive the liquid crystal drive voltage 94 corresponding to the display data 942.
4 is generated. The pulse width modulation method is shown in Fig. 1.
As shown in FIG. 6, by changing the voltage applied to the data electrodes of the liquid crystal panel 309 during the selection period, the effective value of the voltage applied to the liquid crystal is controlled to realize gradation display. In the example of FIG. 16, a four-gradation display is realized by dividing the selection period into three equal parts and switching the voltage applied to the data electrodes every three equal parts.

The oscillation circuit 402 generates the display clock 403 for defining the display timing, and the scanning circuit 902.
Is to be supplied to.

The power supply circuit 904 generates and supplies a liquid crystal panel drive voltage (power supply voltage 405 for the scanning circuit 902, power supply voltage 906 for the data driver LSI 900).

The structure and operation of the moving image controller 311 are basically the same as those of the first embodiment (FIG. 5).
reference). However, in the second embodiment, unlike the first embodiment, the FRC data is 2-bit data for each pixel. Multi-gradation display is realized by combining the gradation control by the FRC control performed by the moving image controller 311 and the gradation control by the pulse width modulation control performed by the data driver LSI 900. If four gradations are controlled by pulse width modulation control and 12 or more gradations are controlled by FRC control, display of 32 or more gradations can be realized by combining these.

Next, the display operation in this embodiment will be described.

The description will be divided into a still image display operation and a moving image display operation.

[Still picture display operation] Regarding the still picture,
The CPU 304 reads (read-accesses) the display data in the memory 305, and the data is read by the data driver LSI 9
00 memory cell 933 (write access)
As a result, the display data is updated (drawn). Access to the memory 933 is performed at random. The access of the CPU 304 at this time is performed by the SRAM interface. The read / write timing of the SRAM interface is as shown in FIGS.

Hereinafter, the display data is written to the memory cell 933 of the data driver LSI 900, and the memory cell 9
The reading of the display data from 33 will be described.

First, writing of display data to the memory cell 933 will be described.

The read / write address from the system (CPU 304 etc.) is input to the address management circuit 908 of the data driver LSI 900 through the address bus 301. The address management circuit 908 of each data driver LSI 900 accesses the data driver LSI to which it belongs based on the control signal 901.
It is determined whether or not it is for 900. If the result of this determination is that the data driver LSI 900 to which it belongs is accessed, the address 301 input at this time is changed to the column address 909 and the row address 91.
Convert to 0.

The column address decoder 929 decodes this column address 909. Data selector 9
31 selects the data line of the corresponding address based on this decoding result.

On the other hand, the selector 923 selects the row address 9
10 is selected and output as a row address 924 to the row address decoder 925. Row address decoder 92
5 decodes this row address 924 and selects one gate line according to the decoding result. Thereby, the CP
The U 304 can access a predetermined bit on the memory cell 933 determined by the data line and gate line selected at that time and transfer the display data to a predetermined address.

Next, reading (display operation) of display data from the memory cell 933 will be described.

The timing control circuit 911 uses the register 9
By confirming the contents of 110 and the row address 922, it is known that the still image area is being displayed at this time. Therefore, at this time, the timing control circuit 911 outputs a value such that the selector 937 selects the data bus 934 as the control signal 945. The selector 937 determines the data bus 9 according to the control signal 945.
34, and data read from the memory cell 933 through the data bus 934 (2 bits for each pixel,
One line) is output as display data 938.

The shift register 939 displays the display data 93.
Latch 8 in the horizontal cycle. Following this, the latch circuit 9
41 latches the display data 940 output from the shift register 939 in the next horizontal cycle, and the liquid crystal drive circuit 943
To display data 942. LCD drive circuit 94
3 is a pulse width modulation (P
The liquid crystal drive voltage 944 controlled by the WM) is applied to the liquid crystal panel 3
09 is output. The output of the liquid crystal drive voltage 944 is output in synchronization with the scanning selection signal 903 generated by the scanning circuit 902, and thus display of one line of the liquid crystal panel 309 can be realized.

By repeating the above operation, a still image can be displayed.

[Movie Display Operation] When displaying a movie, multi-gradation display and high-speed transfer of display data are actually required. Data driver LSI 900 of this embodiment
Performs the following drawing operation to deal with this.

The moving picture data is expanded from the compressed moving picture data by the moving picture controller 311 and the CPU 304 into the display data. The moving image controller 311 performs FRC control on the expanded display data.

By the way, the moving image controller 311 also includes a register (control register circuit 505 in FIG. 5) which stores information indicating the moving image area. By confirming the contents of this register, the video controller 311
At that time, it is possible to know whether or not the target of the display process is the moving image display area. If the moving image display area is the target of the display process at that time, the moving image controller 311 performs the FRC control described above. And
The resulting 2-bit FRC data for each pixel is set to 1
The lines are sequentially sent to the data driver LSI 900 through the data bus 302.

Similarly, the timing control circuit 911 of the data driver LSI 900 also confirms the content of the register 9110 and the row address 922 to know that the display processing target at that time is the moving image display area.
Therefore, the timing control circuit 911 sets the control signal 945 at this time to a value such that the selector 937 selects the data bus 302. As a result, the selector 937
The FRC data sent from the video controller 311 is selected via the data bus 302, and the shift register 9 is selected.
39 to output. After this, the liquid crystal drive voltage 444 for which the pulse width control has been performed is performed in the same manner as in the case of a still image.
Will be output. As described above, by combining the 4-gradation control by the pulse width modulation method and the 12-gradation control by the FRC gradation method, it is possible to realize a display of 32 gradations or more.

Next, the timing of moving image data transfer from the moving image controller 311 to the data driver LSI 900 and the processing timing of this moving image data in the data driver LSI 900 will be described in more detail with reference to FIGS. 12, 13 and 14. To do.

In the description here, the timing control circuit 4
In the register 4110 of 11, the area (n <m) from the n line to the m line of the liquid crystal panel 309 is set as the moving image display area (see FIG. 12).

The transfer of the moving image display data from the moving image controller 311 to the data driver 900 is the same as in the first embodiment.

The 2-bit moving image display data for each pixel is serially transferred from the moving image controller 311 to the data driver LSI 900 through the data bus 302 for each line. In FIG. 13, CL1 is a synchronizing signal representing a horizontal period, and is a display synchronizing signal 907 (see FIGS. 6 and 7).
Signal) included in the reference.

The timing control circuit 911 uses this CL1
Is output to the display address counter 921 as a control signal 913. The display address counter 921 counts the control signal 913 (CL1) and outputs the count value to the selector 923 as a display row address 922.

The selector 937 switches its selected state according to the control signal 945, and the selected state is
It has the following relationship with the count value of the display address counter 921. That is, when the count value of the display address counter 921 is n−1 (when it is not the moving image display area), the selector 937 causes the data bus 934 (that is, the n−1 line stored in the memory cell 933). Eye display data) is selected. When the count value of the display address counter 921 is n (in the moving image display area), the selector 937 selects the data bus 302 (that is, the display data sent from the moving image controller 311). Thus, in the moving image display area, the selector 937 selects the data bus 302 (display data from the moving image controller 311), and selects the display data of the memory cell 933 outside the moving image display area.

The operation of the moving image controller 311 is also as follows.
The following relationships are associated with the operations of the selector 937 and the display address counter 921. That is, when the display address counter 921 counts (n-1), the moving image controller 311 sequentially transfers the display data of the nth line.

In the data driver LSI 900,
The shift register 939 takes in the data of the n-th line (for one line) sent from the moving image controller 311 at the timing shown in FIG. That is, the shift register 939 sequentially fetches the display data 938 (data of the nth line sent from the moving image controller 311) for one line with the shift clock 916 synchronized with the WE signal (Note: as described above. At this time,
The selector 937 is in a state where the data bus 302 is selected). The display data is transferred from the moving image controller 311 in synchronization with the WE signal (write enable signal) in FIG. The shift register 939 transfers the data captured at such timing to the latch circuit 941 as the display data 940.

The latch circuit 941 latches this display data 940 in synchronization with the next CL1 signal,
The data is transferred to the liquid crystal drive circuit 943 as 42 (see FIG. 13). The liquid crystal drive circuit 943 uses this display data 942.
A liquid crystal drive voltage 944 that is pulse width modulated corresponding to (2 bits for each pixel) is generated and output. LCD drive voltage 94
The output of 4 is the scan selection signal 90 generated by the scanning circuit 902.
3 is output in synchronization with the liquid crystal panel 3
Display of one line of 09 can be realized.

By repeating the above operation, a moving image can be displayed.

As described above, in the liquid crystal display device of the second embodiment, the memory cell 933 included in the data driver LSI 900 is used only for displaying a still image. Therefore, it is not necessary to rewrite the memory cell 933 at high speed, and low power consumption can be achieved. Further, the gradation display in the moving image display is the FRC control by the moving image controller,
It is realized by combining with pulse width modulation control by a data driver. Therefore, the data driver LS
It is possible to easily realize a multi-gradation moving image display (32 gradations in this embodiment) without increasing the memory capacity of the I900.

Next, a liquid crystal display device according to the third embodiment will be described with reference to FIGS. 8 to 14 and 17.

In the third embodiment, the voltage modulation method (AM method) is used as the gradation method.

The overall structure of this liquid crystal display device is the same as that of the first embodiment (see FIG. 1) except that the data driver 1400 is used in place of the data driver 307. The feature of the third embodiment resides mainly in the data driver LSI 1400. So, after this,
The description will focus on the data driver LSI 1400.

Each data driver LSI 1400 has a display memory (memory cell 1433) having a capacity capable of holding display data of 3 bits for each pixel for 160 outputs and 240 lines. Therefore, a single data driver LSI 1400 can display a liquid crystal panel of 160 × 240 pixels in 8 gradations. LCD panel 309
Is 320 × 480 pixels, two data driver LSIs 1400 are arranged vertically (four in total),
Two-screen drive is performed for each of the upper and lower 240 lines.

As shown in FIGS. 8 and 9, the data driver LSI 1400 includes an address management circuit 1408, a timing control circuit 1411, an I / O buffer 1419, a display address counter 1421, a selector 1423, a row address decoder 1425, and a column address decoder 14.
29, a data selector 1431, a memory cell 1433,
A selector 1437, a shift register 1439, a latch circuit 1441, and a liquid crystal drive circuit 1443 are provided. Also, between these parts (or between other circuit parts)
Various signal lines for connecting the buses 1420, 1432, 1
434 and 1442 etc. are provided.

8 and 9, the oscillator circuit 402 and the power supply circuit 1 which are not shown in FIG. 1 are omitted.
I also draw 404.

The address management circuit 1408 controls the control signal 3
The address 301 is converted into a column address 1409 and a row address 1410 based on 03,1401. The address management circuit 1408 outputs the column address 1409 to the column address decoder 1429 and the row address 1410 to the row address decoder 1425 via the selector 1423. In addition,
The control signal 1401 is generated by the four data driver LSIs 14
This is for designating which of 00 is the access target at that time.

The timing control circuit 1411 uses the control signal 303 and the display synchronization signal 1407 to control various control signals 1412 and 141 in the data driver LSI 1400.
3,1414,1416,1417,1418,142
7, 1445 is generated. Of these control signals, the control signal 1412 is output to the I / O buffer 1419. The control signal 1413 is output to the display address counter 1421. Control signal 1414
Are output to the selector 1423. The control signal (shift clock) 1416 is output to the shift register 1439. The control signal (latch signal) 1417 is output to the latch circuit 1441 and is used to control the timing of latching the display data. The control signal 1418 is output to the liquid crystal drive circuit 1443 and is used to control the alternating current of the liquid crystal drive.
The control signal 1427 is output to the liquid crystal drive circuit 1443 and used to control the timing of voltage modulation control. The control signal 1445 is output to the selector 1437 and is connected to the selector 1437.
Data bus (data bus 436, data bus 30
It is used by the selector 1437 to select either one of 2). The timing control circuit 1
The control signal 1401 described above is also input to 411.

The timing control circuit 1411 is provided with a register 14110 in which information indicating a moving image display area on the liquid crystal panel 309 is stored. Also,
At that time, a row address 1422 is input to the timing control circuit 1411, which indicates which number line on the liquid crystal panel 309 the display data corresponding to which should be read from the memory cell 1433. Control signal 1445
Indicates the contents of this register 14110 and the row address 142
2 is generated based on That is, the display data 302 (moving image data sent from the moving image controller 311) is displayed in the moving image display area, while the display data 1434 (still image data) is displayed in the still image display area.
A control signal 1445 is generated to cause 37 to select. Such a point is the most characteristic point of this embodiment.

The I / O buffer 1419 receives the control signal 14
12, the input / output of the display data 302, 1420 is controlled.

The display address counter 1421 generates a display row address 1422 according to the control signal 1413. The display address counter 1421
Sets the row address 1422 to the timing control circuit 1
411 and selector 1423.

The selector 1423 selects either the display row address 1422 or the drawing row address 1410 according to the control signal 1414. The selector 1423 uses the selected one as a row address 1424 and a row address decoder 1425.
Is output to.

The row address decoder 1425 decodes the row address 1424 to generate the word selection signal 142.
6 is generated and is output to the gate line of the memory cell 1433.

The column address decoder 1429 outputs the column address 140 output from the address management circuit 1408.
9 to generate the selection signal 1430. The column address decoder 1429 outputs this selection signal 1430 to the data selector 1431.

The data selector 1431 has the selection signal 14
Data bus 1432 of memory cell 1433 according to 30
The input / output of the display data 1420 to / from the memory cell 1433 is controlled by selecting the data line.

The memory cell 1433 is a memory for temporarily storing display data (still image data), and is a RAM.
It is composed of The area on the memory cell 1433 which is the target for writing / reading the display data can be designated based on the above-mentioned column address and row address. Memory cell 1 as described above
The reference numeral 433 has a capacity capable of holding 3-bit display data for each pixel for 160 outputs and 240 lines.

The selector 1437 has display data 1434.
Either (still image data) or the display data 302 (moving image data) input from the moving image controller 311 is selected according to the control signal 1445. That is, in the present embodiment, the display data sent via the data bus 302 is the selector 1
Two routes are provided before reaching 437.
The first route is, after the data bus 302, the I / O buffer 1419, the data selector 1431, and the memory cell 1.
433, selector 1437 through data bus 1434
Is the route to. The second route is memory cell 1
It is a route in which the data bus 302 is directly connected to the selector 1437 without passing through 433 or the like. During the period in which the display data for the area preset as the moving image display area is to be input, moving image data is input to the data bus 302 from the moving image controller 311. On the other hand, during the period when the display data for the area set as the still display area in advance should be input,
Still image data is input to the data bus 302 from the CPU 304, the memory 305, and the like. Therefore, selector 1
At 437, data bus 1434 and data bus 30
By selecting either one of the two from the data bus 302 according to the control signal 1445, the selector 143 from the data bus 302 is selected.
Either of the two routes up to 7 can be selected according to the display data. The selector 14
37 is the display data 143 for the one selected in this way.
8 is output to the shift register 1439.

It should be noted that the selector 143 according to the present embodiment.
The specific internal configuration of 7 may be the same as that of the selector 437 in the first embodiment (see FIG. 4).

The shift register 1439 is a 12-bit bidirectional shift register, and operates according to the control signal (shift clock) 1416.

The latch circuit 1441 displays the display data 1440 according to the control signal (latch signal) 1417 (that is, in synchronization with the scanning selection signal 1403 of the scanning circuit 1402).
Is to latch. The latch circuit 1441 outputs the latched data to the liquid crystal drive circuit 1443 as display data 1442.

The liquid crystal drive circuit 1443 uses the voltage modulation method to drive the liquid crystal drive voltage 94 corresponding to the display data 1442.
4 is generated. As shown in FIG. 17, the voltage modulation method is a method in which a grayscale display is realized by applying a halftone voltage according to grayscale data to the data electrodes of the liquid crystal panel 309 to control the effective value of the voltage applied to the liquid crystal. Is. In the voltage modulation method, the voltage applied during the non-selection period varies depending on the gradation of the display data, so the halftone voltage is set so that the effective voltage value is constant in two frames (see FIG. 17). The liquid crystal drive circuit 1443 enables 8-gradation display by voltage modulation.

The oscillation circuit 402 generates the display clock 403 for defining the display timing, and the scanning circuit 140
2 is to be supplied.

The power supply circuit 1404 generates and supplies a liquid crystal panel drive voltage (power supply voltage 405 for the scanning circuit 1402, power supply voltage 1406 for the data driver LSI 1400).

The configuration and operation of the moving image controller 311 are basically the same as those of the first embodiment (FIG. 5).
reference). However, in the third embodiment, unlike the first embodiment, the FRC data is 3-bit data for each pixel. Multi-gradation display is realized by combining gradation control by FRC control performed by the moving image controller 311 and gradation control by voltage modulation control performed by the data driver LSI 1400. If 8 gradations are controlled by voltage modulation control and 6 gradations or more are controlled by FRC control, display of 32 gradations or more can be realized by combining these.

Next, the display operation in this embodiment will be described.

The description will be divided into a still image display operation and a moving image display operation.

[Still picture display operation] Regarding the still picture,
The CPU 304 reads (read-accesses) the display data in the memory 305, and the data is read by the data driver LSI 1
By writing (write access) to the memory cell 1433 of 400, display data is updated (drawing). Access to the memory 1433 is performed at random. The access of the CPU 304 at this time is performed by the SRAM interface. The read / write timing of the SRAM interface is as shown in FIGS.

Writing display data to the memory cell 1433 and reading display data from the memory cell 1433 of the data driver LSI 1400 will be described below.

First, writing of display data to the memory cell 1433 will be described.

A read / write address from the system (CPU 304 etc.) is passed through the address bus 301 to the address management circuit 1408 of the data driver LSI 1400.
Is input to The address management circuit 1408 of each data driver LSI 1400 determines based on the control signal 1401 whether or not the access at that time is to the data driver LSI 1400 to which it belongs. As a result of the determination, the data driver LSI to which it belongs
If the access is to 1400, the address 301 input at this time is set to the column address 1409,
Convert to row address 1410.

The column address decoder 1429 decodes this column address 1409. The data selector 1431 selects the data line of the corresponding address based on this decoding result.

On the other hand, the selector 1423 selects the row address 1410 and outputs it as the row address 1424 to the row address decoder 1425. The row address decoder 1425 decodes the row address 1424, and selects one gate line according to the decoding result. As a result, the CPU 304 causes the memory cell 1433 determined by the data line and gate line selected at that time.
The display data can be transferred to a predetermined address by accessing the predetermined bit above.

Next, reading of display data (display operation) from the memory cell 1433 will be described.

The timing control circuit 1411 confirms that the still image area is being displayed at this time by checking the contents of the register 14110 and the row address 1422. Therefore, the timing control circuit 1411
At this time, the selector 1437 causes the data bus 143 to
A value for selecting 4 is output as the control signal 1445. The selector 1437 selects the data bus 1434 according to the control signal 1445, and selects the data bus 1434.
The data (3 bits for each pixel, 1 line worth) read out from the memory cell 1433 through 34 is the display data 1
Output as 438.

The shift register 1439 displays the display data 1
Latch 438 on a horizontal cycle. Following this, the latch circuit 1441 shifts the shift register 143 in the next horizontal cycle.
The display data 1440 output from No. 9 is latched and output to the liquid crystal drive circuit 1443 as the display data 1442. The liquid crystal drive circuit 1443 performs a liquid crystal drive voltage 1444 that has been subjected to voltage modulation (AM) control according to the display data 1442.
Is output to the liquid crystal panel 309. LCD drive voltage 1444
Of the scanning selection signal 14 generated by the scanning circuit 1402.
It is output in synchronism with 03, so that the display for one line of the liquid crystal panel 309 can be realized.

By repeating the above operation, a still image can be displayed.

[Movie display operation] When displaying a movie, multi-gradation display and high-speed transfer of display data are actually required. Data driver LSI 1400 of this embodiment
Performs the following drawing operation to deal with this.

With respect to the moving picture data, the moving picture controller 311 and the CPU 304 perform moving picture decompression processing from the moving picture compressed data and expand it into display data. The moving image controller 311 performs FRC control on the expanded display data.

By the way, the moving image controller 311 also includes a register (control register circuit 505 in FIG. 5) which stores information indicating the moving image area. By confirming the contents of this register, the video controller 311
At that time, it is possible to know whether or not the target of the display process is the moving image display area. If the moving image display area is the target of the display process at that time, the moving image controller 311 performs the FRC control described above. And
The resulting 3-bit FRC data for each pixel is set to 1
The lines are serially sent to the data driver LSI 1400 via the data bus 302.

Similarly, the timing control circuit 1411 of the data driver LSI 1400 also confirms the contents of the register 14110 and the row address 1422 to know that the display processing target at that time is the moving image display area. Therefore, the timing control circuit 1411 sets the control signal 1445 at this time to a value such that the selector 1437 selects the data bus 302. As a result, the selector 1437 selects the FRC data sent from the video controller 311 via the data bus 302,
It is output to the shift register 1439. After that, the liquid crystal drive voltage 444 subjected to this voltage modulation control is output in the same manner as in the case of a still image. In this way, by combining the 8 gradation control by the voltage modulation method and the control of 6 gradations or more by the FRC gradation method, 32
It is possible to realize display with gradation or more.

Next, the timing of moving image data transfer from the moving image controller 311 to the data driver LSI 1400 and the data driver LSI 140 for this moving image data.
The processing timing within 0 will be described in more detail with reference to FIGS. 12, 13 and 14.

In the description here, the timing control circuit 4
In the register 4110 of 11, the area (n <m) from the n line to the m line of the liquid crystal panel 309 is set as the moving image display area (see FIG. 12).

The transfer of the moving image display data from the moving image controller 311 to the data driver 1400 is the same as in the first embodiment.

The 3-bit moving picture display data for each pixel is serially transferred from the moving picture controller 311 to the data driver LSI 1400 by one line through the data bus 302. In FIG. 13, CL1 is a sync signal representing a horizontal period, and the display sync signal 1407 (FIG. 8,
(See FIG. 9).

The timing control circuit 1411 uses this CL
1 as the control signal 1413 and the display address counter 14
21. Display address counter 1421
Counts the control signal 1413 (CL1) and outputs the count value to the selector 1423 as a display row address 1422.

The selector 1437 switches its selected state according to the control signal 1445, and the selected state has the following relationship with the count value of the display address counter 1421. That is, the display address counter 1
When the count value of 421 is n−1 (when it is not the moving image display area), the selector 1437 causes the data bus 1434 (that is, the display data of the n−1th line stored in the memory cell 1433). Is selected. When the count value of the display address counter 1421 is n (in the moving image display area), the selector 1437 selects the data bus 302 (that is, the display data sent from the moving image controller 311). Thus, the selector 1437 selects the data bus 302 (display data from the moving image controller 311) in the moving image display area, and selects the display data of the memory cell 1433 in areas other than the moving image display area.

The operation of the moving image controller 311 is also as follows.
The following relationships are associated with the operations of the selector 1437 and the display address counter 1421. That is, when the display address counter 1421 counts (n-1), the moving image controller 311 sequentially transfers the display data of the nth line.

In the data driver LSI 1400, the shift register 1439 is sent from the moving picture controller 311 at the timing shown in FIG.
The data of the line (one line) is fetched. That is, the shift register 1439 sequentially displays the display data 1438 with the shift clock 1416 synchronized with the WE signal.
(Data of the nth line sent from the moving image controller 311) for one line is fetched (Note: as described above, at this time, the selector 1437 is operated by the data bus 302.
Has been selected). It should be noted that the transfer of the display data from the moving image controller 311 is performed by W in FIG.
It is performed in synchronization with the E signal (write enable signal). The shift register 1439 transfers the data captured at such timing to the latch circuit 1441 as display data 1440.

The latch circuit 1441 latches this display data 1440 in synchronization with the next CL1 signal and transfers it as display data 1442 to the liquid crystal drive circuit 1443 (see FIG. 13). The liquid crystal drive circuit 1443 generates and outputs a liquid crystal drive voltage 1444 that is voltage-modulated corresponding to the display data 1442 (3 bits for each pixel). The output of the liquid crystal drive voltage 1444 is output in synchronization with the scan selection signal 1403 generated by the scan circuit 1402, and thus display of one line of the liquid crystal panel 309 can be realized.

By repeating the above operation, a moving image can be displayed.

As described above, in the liquid crystal display device of the third embodiment, the memory cell 1433 included in the data driver LSI 1400 is used only for displaying a still image.
Therefore, it is not necessary to rewrite the memory cell 1433 at high speed, and low power consumption can be achieved. The gradation display in the moving image display is realized by combining the FRC control by the moving image controller and the voltage modulation control by the data driver. Therefore, the data driver LS
A multi-gradation moving image display (32 gradations in this embodiment) can be easily realized without increasing the memory capacity of the I1400.

In the first to third embodiments described above, the number of outputs of the data driver is 160, but the number of outputs is not limited to this. This can be easily handled by simply changing the configurations of the memory, the output circuit, etc. according to the number of outputs. Also, F
Other combinations of gradation control such as RC, pulse width modulation, and voltage modulation can be easily supported.

The configurations of the first, second and third embodiments described above may be combined. For example, gradation control may be performed at a total of three positions, that is, the position immediately after the memory cell, the moving image controller, and the liquid crystal drive circuit.

If the data driver and the liquid crystal display device described above are used, an information processing device with low power consumption and capable of multi-gradation display and moving image display can be obtained.

The "data bus" referred to in the claims is the data bus 302 in the above embodiment.
Is equivalent to "Address bus" means address bus 30
Equivalent to 1. The "data processing system" includes an address management circuit 408 (908, 1408), a column address decoder 429 (929, 1429), and a selector 431 (93).
1, 1431), the I / O buffer 419 (919, 14)
19), memory cells 433 (933, 1433), row address decoders 425 (925, 1425), selectors 423 (923, 1423), data buses 436 (9).
34, 1434), etc. What is "display memory"?
This corresponds to the memory cell 433 (933, 1433). "
The “output bus” means the data bus 436 (934, 143).
It corresponds to 4). "First gradation control circuit" means FRC
It corresponds to the data circuit 427 and the FRC selector 435.
The “selection unit” is the timing control circuit 411 (91
1, 1411), selector 437 (937, 143)
7), display address counter 421 (921, 142)
1) etc. What is "memory"? Register 4110
(9110, 14110) and "selection information" correspond to the setting information indicating the moving image area stored in these registers 4110 (9110, 14110). "
The instruction circuit "is a timing control circuit (911, 141).
1), display address counter 421 (921, 142)
It corresponds to 1). “Selection instruction” means a control signal 445.
This corresponds to (945, 1445). What is a "selector"?
Selector 437 (937, 1437) "voltage output means"
Is the shift register 439 (939, 1439), the latch circuit 441 (941, 1441), the liquid crystal drive circuit 4
43 (943, 1443). The "second gradation control circuit" corresponds to a part related to gradation control included in the liquid crystal drive circuit 943 (1443). The “data controller” corresponds to the moving image controller 311. The “third control circuit” corresponds to the FRC control circuit 506.

However, the above-mentioned units operate in close cooperation with each other, and the definition described here is not strict.

[0208]

As described above, according to the present invention, multi-gradation display and moving image display can be performed without increasing the display memory capacity built in the data driver. Further, since the data driver has a built-in display memory, the access frequency of the display memory can be reduced (once in the horizontal period) for still images. Therefore, it is possible to achieve both low cost and low power consumption. Since the number of gradation display is FRC controlled by an external controller, it can be arbitrarily set regardless of the data driver LSI. By using the data driver and the liquid crystal display device of the present invention, it is possible to obtain an information processing device with low power consumption and capable of multi-gradation display and moving image display.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device which is a first embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a main part of a liquid crystal display device.

FIG. 3 is a block diagram showing a detailed configuration of a data driver LSI 307.

FIG. 4 is a circuit diagram showing an internal configuration of a selector 437.

5 is a block diagram showing an internal configuration of a moving image controller 311. FIG.

FIG. 6 is a diagram showing a configuration of a main part of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a data driver LSI 900.

FIG. 8 is a diagram showing a configuration of a main part of a liquid crystal display device according to a third embodiment of the present invention.

9 is a diagram showing an internal configuration of a data driver LSI 1400. FIG.

FIG. 10 is a diagram showing memory write timing of an SRAM interface.

FIG. 11 is a diagram showing memory read timing of an SRAM interface.

12 is a diagram showing a moving image display area on the liquid crystal panel 309. FIG.

FIG. 13 is a diagram showing a moving image controller 311 to a liquid crystal driver 3
It is a figure which shows the transfer timing of the moving image display data to 07 (900, 1400).

FIG. 14 is a shift register 439 (939, 1439).
FIG. 5 is a diagram showing a transfer timing of display data according to FIG.

FIG. 15 is a diagram showing an FRC gradation method.

FIG. 16 is a diagram showing a pulse width modulation gradation method.

FIG. 17 is a diagram showing a voltage modulation gradation method.

FIG. 18 is a configuration diagram of a conventional liquid crystal display device.

FIG. 19 is a configuration diagram of a main part of a conventional liquid crystal display device.

FIG. 20 is a configuration diagram of a conventional data driver.

[Explanation of symbols]

[FIG. 1] 301 ... Address bus, 302 ... Data bus (display data), 303 ... Control signal, 304 ... CPU,
305 ... Memory, 306 ... I / O device, 307 ... Data driver, 308 ... Scan circuit, 309 ... Liquid crystal panel, 310 ... Display synchronization signal, 311 ... Movie controller [FIG. 2, FIG. 3] 401 ... Control signal, 402 ... Oscillator circuit,
403 ... Display clock, 404 ... Power supply circuit, 405 ... Power supply voltage, 406 ... Power supply voltage, 407 ... Scan selection signal, 4
08 ... Address management circuit, 409 ... Column address, 4
10 ... Row address, 411 ... Timing control circuit, 4
12 ... Control signal, 413 ... Control signal, 414 ... Control signal, 415 ... Control signal, 416 ... Shift clock, 41
7 ... Control signal (latch signal), 418 ... Control signal, 41
9 ... I / O buffer, 420 ... Data bus, 421 ... Display address counter, 422 ... Row address, 423 ...
Selector, 424 ... Row address, 425 ... Row address decoder, 426 ... Select signal, 427 ... FRC data circuit, 428 ... FRC data, 429 ... Column address decoder, 430 ... Select signal, 431 ... Data selector, 432 ... Data bus, 433 ... Memory cell, 434
... data bus (display data), 435 ... FRC selector, 436 ... data bus (display data), 437 ... selector, 438 ... data bus (display data), 439 ... shift register, 440 ... data bus (display data), 4
41 ... Latch circuit, 442 ... Data bus (display data), 443 ... Liquid crystal drive circuit, 444 ... Liquid crystal drive voltage,
445 ... Control signal, 4110 ... Register [FIG. 5] 501 ... Timing control circuit, 502 ... I / O
Control circuit, 503 ... Address control circuit, 504 ... Video processing circuit, 505 ... Control register circuit, 506 ... FRC control circuit, 507 ... Control signal, 508 ... Control signal, 509
... control signal, 510 ... control signal, 511 ... control signal, 5
12 ... Control signal (register latch signal), 513 ... Address bus, 514 ... Address bus, 515 ... Data bus, 516 ... Data bus, 517 ... Data bus, 518
Data bus, 519 Data bus, 520 Data bus [FIGS. 6 and 7] 900 Data driver, 901 Control signal, 902 Scan circuit, 903 Scan selection signal, 90
4 ... Power supply circuit, 1405 ... Power supply voltage, 1406 ... Power supply voltage, 907 ... Display synchronization signal, 908 ... Address management circuit, 909 ... Column address, 910 ... Row address,
911 ... Timing control circuit, 912 ... Control signal, 91
3 ... control signal, 914 ... control signal, 916 ... control signal (shift clock), 917 ... control signal (latch signal), 918 ... control signal, 919 ... I / O buffer, 9
20 ... Data bus, 921 ... Display address counter, 9
22 ... Row address, 923 ... Selector, 924 ... Row address, 925 ... Row address decoder, 926 ... Word selection signal, 927 ... Control signal, 929 ... Column address decoder, 930 ... Selection signal, 931 ... Selector,
932 ... Data bus, 933 ... Memory cell, 934 ... Data bus, 937 ... Selector, 938 ... Data bus, 9
39 ... Shift register, 940 ... Data bus (display data), 941 ... Latch circuit, 942 ... Data bus (display data), 943 ... Liquid crystal drive circuit, 944 ... Liquid crystal drive voltage, 945 ... Control signal, 9110 ... Register [Figure 8, FIG. 9] 1400 ... Data driver, 1401 ...
Control signal, 1402 ... Oscillation circuit, 1403 ... Scan selection signal, 1404 ... Power supply circuit, 1405 ... Power supply voltage, 140
6 ... Power supply voltage, 1407 ... Display synchronization signal, 1408 ... Address management circuit, 1409 ... Column address, 1410
... row address, 1411 ... timing control circuit, 14
12 ... Control signal, 1413 ... Control signal, 1414 ... Control signal, 1416 ... Control signal (shift clock), 141
7 ... control signal (latch signal), 1418 ... control signal, 1
419 ... I / O buffer, 1420 ... Data bus, 14
21 ... Display address counter, 1422 ... Row address, 1423 ... Selector, 1424 ... Row address, 1
425 ... Row address decoder, 1426 ... Word selection signal, 1427 ... Control signal, 1429 ... Column address decoder, 1430 ... Selection signal, 1431 ... Data selector, 1432 ... Data bus, 1433 ... Memory cell,
1434 ... Data bus, 1437 ... Selector, 1438
... data bus (display data), 1439 ... shift register, 1440 ... data bus, 1441 ... latch circuit, 1
442 ... Data bus, 1443 ... Liquid crystal drive circuit, 144
4 ... Liquid crystal drive voltage, 1445 ... Control signal, 14110 ...
Register [FIG. 18] 101 ... Address bus, 102 ... Data bus, 103 ... Control signal line (control signal), 104 ... CP
U, 105 ... Memory, 106 ... I / O device, 107
... data driver, 108 ... scanning circuit, 109 ... liquid crystal panel, 110 ... display synchronization signal [FIGS. 19 and 20] 201 ... display oscillation circuit, 202 ...
Power supply circuit, 203 ... Control signal line, 204 ... Display control signal line, 205 ... Power supply voltage, 206 ... Power supply voltage, 207 ... Address management circuit, 208 ... Column address, 209 ... Row address, 210 ... Timing control circuit, 211 ... Control signal, 212 ... Control signal, 213 ... Control signal, 214
Control signal (latch signal), 215 Control signal (latch signal), 216 Control signal, 217 Display address counter, 218 Row address, 219 I / O buffer, 220 Data bus, 221 Selector, 222 …
Row address, 223 ... Column address decoder, 22
4 ... Selection signal, 225 ... Data selector, 226 ... Data bus, 227 ... Row address decoder, 228 ... Word selection signal, 229 ... Memory cell, 230 ... Data bus (display data), 231 ... Control signal, 232 ... FRC data Circuits, 233 ... FRC data, 234 ... FRC selector, 235 ... Display data bus, 236 ... Latch circuit, 2
37 ... Data bus, 238 ... Latch circuit, 239 ... Data bus, 240 ... Liquid crystal drive circuit, 241 ... Liquid crystal drive voltage

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoru Tsunekawa 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division

Claims (13)

[Claims] 1. A data driver for outputting a liquid crystal driving voltage applied to a data line of a liquid crystal panel according to display data input from the outside, and a data bus to which the display data is input from the outside and an address from the outside. An address bus, a display memory for storing display data, and an output bus for outputting data read from the display memory. Display data input through the data bus is transmitted through the address bus. A data processing system that temporarily stores in a region on the display memory determined based on the input address, then reads the display data stored in the display memory in a separately determined order and outputs the read data through the output bus; Selecting means for selecting one of the output bus of the data processing system and the data bus; A data driver, comprising: voltage output means for outputting a liquid crystal drive voltage according to data sent through the bus selected by the selecting means. 2. The selection means comprises a memory for storing selection information serving as a selection reference, an instruction circuit for outputting a selection instruction according to the selection information, and the data bus or the data bus according to an instruction from the instruction circuit. 2. The data driver according to claim 1, further comprising: a selector that selects one of the output buses of the data processing system. 3. The selection information defines an area on the liquid crystal panel, and the instruction circuit sends data to be output to the area defined by the selection information through the data bus. 3. The data driver according to claim 2, wherein an instruction to select the data bus is issued during the incoming period, and an instruction to select the output bus of the data processing system is issued at other times. 4. The data driver according to claim 3, wherein the selection information defines an area for displaying a moving image on the liquid crystal panel. 5. The first data processing system controls gradation based on display data read from the display memory.
2. The gradation control circuit according to claim 1, wherein the data after gradation control by the first gradation control circuit is output through the output bus. The data driver according to 3 or 4. 6. The data driver according to claim 5, wherein the first gradation control circuit performs the gradation control by an FRC method. 7. The voltage output means has a second gradation control circuit for performing gradation control based on the data sent through the bus selected by the selection means. 7. The data driver according to claim 1, wherein the voltage obtained by gradation control by the gradation control circuit of 2 is output as the liquid crystal drive voltage. 8. The data driver according to claim 7, wherein the second gradation control circuit performs the gradation control by a PWM system or an AM system. 9. A data driver according to claim 1, 2, 3, 4, 5, 6, 7 or 8, and a data controller for processing display data, wherein the data controller outputs the result of the processing as described above. A liquid crystal display device, which outputs data to the data driver through a data bus. 10. The data controller includes a third gradation control circuit for performing gradation control on display data, and outputs data obtained by gradation control by the third gradation control circuit. The liquid crystal display device according to claim 9, wherein the liquid crystal display device is a liquid crystal display device. 11. The liquid crystal display device according to claim 10, wherein the third gradation control circuit performs the gradation control by an FRC method. 12. A gradation control by the first gradation control circuit, a gradation control by the second gradation control circuit, and a gradation control by the third gradation control circuit. 11. The liquid crystal display device according to claim 10, wherein gradation display is performed by combining at least two. 13. An information processing apparatus comprising the liquid crystal display device according to claim 10, 11 or 12.