JP3018329B2 - Display system and liquid crystal display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display system of a liquid crystal display device capable of multicolor display applied to a personal computer or the like.

[Related Art] In recent years, liquid crystal display devices have rapidly advanced in accordance with the rapid spread of the laptop computer market. Current status,
Most of these laptop computers are capable of color display, and the majority are of single color display.

However, most of the applications of this type of computer are based on color display, so that the monochrome display supports gradation display. In short, color information is converted into monochromatic shading information to emulate color display.

An example of such a gradation display is disclosed in Japanese Patent Application Laid-Open No. 58-57192.
Is described in Japanese Patent Application Publication No.

FIG. 2 shows a conventional example of a display circuit of a computer using such a conventional technique.

FIG. 2 is a block diagram of a computer display system circuit for performing gradation display.

In the figure, 1 is a central processing unit (hereinafter abbreviated as MPU), 2
Is a liquid crystal display timing controller (hereinafter abbreviated as LCTC), 3 to 5 are display memories, 6 is a palette that determines a display color from information read from the display memory, and 7 is a gradation control circuit that converts color information into a gradation signal. , 8 are liquid crystal display devices for monochromatic display.

This block diagram has three display memories I, II, and III, and can display eight gradations corresponding to eight colors.
However, by writing information to be displayed in each display memory, desired information is output to the liquid crystal display device 8.

The process of outputting desired information from the display memory to the liquid crystal display device 8 is performed by the LCTC 2.

The LCTC 2 generates a display memory address corresponding to the scanning order of the liquid crystal display device 8 and outputs a synchronization signal necessary for display to the liquid crystal display device 8.

According to this address, the display memories I3 to III5
Output display data. These data are sent to the palette 6 as 3-bit information for one pixel. The pallet 6 is a memory having a structure of 8 words × 3 bits, and outputs the contents of the memory (color information of 8 colors expressed by 3 bits) according to input 3-bit address information.

In short, the palette 6 converts 3-bit logical information into 8-color physical information.

Further, the gradation control circuit 7 generates a display signal of eight gradations to be displayed on the single-color liquid crystal display device 8. The gradation display is a frame thinning method for controlling display and non-display in units of one screen scan.

That is, of the eight screen scans, the ratio of display to non-display is 8
Express gradation. For example, what percentage is shown or hidden?
It is set to 7: 1, 5: 3, etc., and realizes 8 levels of grayscale display.

According to this method, in addition to being able to realize eight gradation display with a liquid crystal display device having two gradations of a single color, the gradation control circuit 7 is provided with an LSI.
It is advantageous in that hardware can be reduced in size due to, for example, high cost performance.

However, in this method, it is difficult to control a delicate difference in gray scale, and 8 to 16 gradations are limited. Therefore, in order to realize multi-gradation display exceeding this, it is necessary to perform gradation display by the liquid crystal display device itself.

Specifically, there is a pulse width modulation method employed in a plasma display device. This controls the lighting time of one pixel. For example, the time to display one pixel
If it is 50n seconds, if pulse control is performed in units of 5n seconds, 1
One gradation display is possible.

FIG. 3 shows a block diagram of a computer display system circuit using such a liquid crystal display device with gradation.

In the figure, circuit blocks having the same functions as those in FIG. 2 are denoted by the same reference numerals.

12 is a 64-gradation palette, and 13 is a 64-gradation liquid crystal display. This display system has a function of selecting and displaying eight gradations out of 64 gradations.

Data read from the display memories 3 to 5 is input to the 64-gradation palette 12, and the 64-gradation palette 12 is 8 words ×
This is a 6-bit memory, which stores 3-bit logical information in 6 bits.
Convert to bit physical display information.

In short, the contents of the memory determine to which of the 64 gradations the eight pieces of logical information are assigned. The 6-bit gradation display information is sent to the 64-gradation liquid crystal display device 13, and the video information of the display memories 3 to 5 is displayed on the screen. As described above, in comparison with the frame thinning method shown in FIG.
(Gradation ÷ 2 gradation).

[Problems to be Solved by the Invention] As described above, in the conventional example, when the number of display gradations is increased, the following points are problematic.

First, in the frame thinning method, it is difficult to make a subtle gradation difference, and the limit is about 8 to 16 gradations.

On the other hand, when using a liquid crystal display device with a gradation function,
There is a problem that the amount of information received by the liquid crystal display device increases. In other words, an increase in the amount of information increases the number of interface signal lines provided to the liquid crystal display device, resulting in an increase in the size of the connector and an increase in the wiring area on the substrate, which is disadvantageous in terms of high-density mounting.

On the other hand, in order to suppress the increase in the number of signal lines, it is necessary to improve the transfer speed of the video signal, and it becomes impossible to cope with a low-cost device such as CMOS. There is also a problem that it is difficult to take measures against electromagnetic interference from the cable.

This problem becomes more remarkable when a multi-color display is displayed rather than a single-color gradation display. In the case of 260,000 color display, which is a global standard specification of a computer display system, 18 bits per pixel are required, and in this case, a transfer speed of about 20 to 30 Mbps is required.

On the other hand, in the conventional single-color display, since the transfer rate is about 3 Mbps with an information amount equivalent to 8 bits per pixel, the transfer amount is about 10 times as large as that in the related art.

On the other hand, the current liquid crystal display device has a maximum transfer speed of about 12 Mbps even at the maximum, and is in a situation where it is difficult to take measures against electromagnetic interference.

It is a serious problem to realize a multi-color display in the future.

The problem described above is due to the large amount of data required to be transferred between the host device and the liquid crystal display device.

Accordingly, an object of the present invention is to provide a display system and a liquid crystal display device that can reduce the amount of data required to be transferred between the host device and the liquid crystal display device.

[Means for Solving the Problems] The present invention provides, as display information,
A display device comprising: a host device having a display system circuit for outputting logical display information; and a display device having means for converting the logical display information input into physical display information and imaging it on a display panel. Provide system.

Further, in this case, the host device includes a synchronization generation unit that generates display synchronization information, a central processing unit that outputs display control information only when the display synchronization information indicates that retrace scanning is being performed, and a logic device. Means for outputting display information, and means for switching between logical display information and display control information in a time-division multiplexed manner and outputting the information to a liquid crystal display device, wherein the liquid crystal display device includes display control information from a host device and the logic. An input port shared with display information, a unit for separating input logical display information and display control information input in a time-division multiplexed manner, and a rewritable storage unit for storing a table for converting the logical display information input into physical display information Means for converting physical display information to a display panel such as a liquid crystal panel, and a central processing unit for accessing the table stored in the storage means in accordance with display control information. It is desirable to have a device.

According to another aspect of the present invention, there is provided a liquid crystal display device to which logical display information is input as display information, comprising a table for converting the input logical display information into a physical display device. And means for visualizing physical display information on a liquid crystal panel.

Further, the liquid crystal display device preferably includes a central processing unit that accesses the table stored in the rewritable storage unit.Furthermore, the liquid crystal display device further includes an input port or It is desirable to have an input / output port.

Further, the liquid crystal display device may include, as the input port,
It has a common input port for the input to the central processing unit from the outside of the liquid crystal display device and the logical display information, and separates the logical display information and the input from outside the liquid crystal display device which are time-division multiplexed and input. Means may be provided.

Further, in order to achieve the above object, the present invention provides a liquid crystal display device, characterized in that the liquid crystal display device is provided with means for restoring logical display information divided and received.

In addition, at least one of two means of converting one or more pieces of parallel data into serial data and outputting it to the outside of the liquid crystal device, and one or more means converting one or more pieces of serial data input from outside the liquid crystal display device into parallel data It is desirable to have one means.

[Operation] An operation of a display system capable of multicolor display, which is one embodiment of the present invention, will be described.

According to this display system, when displaying an image, the central processing unit of the host device determines whether or not the display synchronization information for the liquid crystal display device generated by the synchronization generation means indicates that a blanking period is being performed. If necessary, display control information is output, and the logical display information and physical display information conversion table in the rewritable storage means of the liquid crystal display device stores the physical display information and the logical display of the display color to be displayed. Write or change the conversion table for the correspondence of information.

In the liquid crystal display device, the central processing unit extracts display control information from the input host device, and writes a table in a rewritable storage unit included in the conversion unit based on the content of the display control information, or change.

Thereafter, the host device, in the display system circuit, during the period during which the display synchronization information for the liquid crystal display device generated by the synchronization generating means indicates that the display period is in the display period, as the display information in the display system circuit. The logical display information is output to the liquid crystal display.

The liquid crystal display device takes out the received logical display information input and converts the logical display information input into physical display information by using a conversion table stored in the storage means. Then, the physical display information is visualized on a liquid crystal panel.

Further, the host device outputs a request for transmission of the contents of the conversion table between the logical display information and the physical display information in the storage means during the flyback period as display control information, and the central processing unit of the liquid crystal device has the You may make it respond to a request.

It is desirable that the above-mentioned transfer of each information between the host device and the liquid crystal display device is performed through a common port.

Alternatively, the host device may transmit the logical display information in a divided manner, and the liquid crystal display device may restore the divided logical display information.

The display control information and the logical display information output from the host device to the liquid crystal display device are originally parallel data, but are converted into serial data and output to the outside of the liquid crystal device, and the serial data is converted into parallel data in the liquid crystal display device. It is desirable to do so.

As described above, since the liquid crystal display device has a built-in storage unit that stores a conversion table between logical display information and physical display information, multicolor or multi-gradation display can be performed by receiving the logical information. Since the amount of logical information is smaller than the amount of physical display information, the amount of information input from the outside to the liquid crystal display device can be reduced, and the increase in signal lines and the improvement in transfer speed can be reduced.

[Example] Hereinafter, a first example of the display system according to the present invention will be described.

The display system includes a host and a liquid crystal display device 18.

 FIG. 1 shows the configuration of the host-side display system circuit.

Circuit blocks having the same functions as in FIGS. 2 and 3 showing the conventional example are denoted by the same reference numerals.

In the figure, 1 is a central processing unit (hereinafter abbreviated as MPU), 2 is a liquid crystal display timing controller (hereinafter, LC).
TC is abbreviated), 3 to 5 are display memories, 9, 10, and 11 are parallel / parallel conversion circuits for converting parallel data read from the display memory into serial data, and 14 to 16 are display information read from the display memories 3 to 5. Serialized serial signal line, 17
Is a synchronization signal line output by LCTC2.

18 shows a liquid crystal display device with a built-in palette that can display 64 gradations.

The display system circuit outputs 3-bit logical information of the serial signal lines 14 to 16 to the liquid crystal display device 18. That is, eight gradations out of 64 gradations are selected and displayed.

This means that, in a display system such as a personal computer, to simultaneously display all 64 gradations, 6 bits of display logic information are required, the capacity of the display memory is twice as large as that of the present embodiment, and the cost is increased. Therefore, selecting and displaying an arbitrary cut-out gradation from many gradations is in accordance with a general method.

In the present embodiment, the logical display information read from the display memory is converted into serial data by the parallel / parallel conversion circuit and output to the liquid crystal display device 18.

In short, paying attention to the fact that the logical display information is limited,
By directly outputting the logical display information to the liquid crystal display device 18, the amount of transfer data is reduced and the number of signal lines of a cable connected to the liquid crystal display device 18 is reduced.

Next, a detailed configuration of the liquid crystal display device 18 is shown in FIG.

In the figure, the same reference numerals are given to circuit blocks and signal lines having the same functions as those in FIG.

As shown in the figure, the synchronization signal line 17 is composed of the following four types of signals 19 to 22.

19 is a data shift signal (hereinafter abbreviated as CL2), 20 is a liquid crystal AC drive signal (hereinafter abbreviated as M), 21 is a data latch signal (hereinafter abbreviated as CL1), 22 is a signal indicating the start of screen scanning (hereinafter FLM). Abbreviation). 23 is the timing circuit, 24
Is an x driver, 25 is a y driver, 26 is a liquid crystal display panel,
27 is a pallet. The liquid crystal display panel 26 is the part that actually displays, and when the screen resolution is 640 x 400 dots, 640 electrodes in the horizontal direction and 400 electrodes in the vertical direction (total of 256K
) Constitute the panel surface.

These electrodes are driven by 640 signals output by the x driver and 400 signals output by the y driver.

The y driver is scanning 1 out of 400 lines on the panel surface.
Works to determine the line. In other words, 40 from the first line
Select sequentially up to the 0th line.

In contrast, the x driver is responsible for one line 64
This is for outputting display information of 0 dots.

The X driver 24 and the y driver 25 are controlled by the synchronization signal line 17. The M signal 20 and the CL1 signal 21 are input to a timing circuit 23, and control the AC voltage applied to the electrodes of the x driver 24 and the y driver 25 and horizontal synchronization of screen scanning.

The CL2 signal 19 determines the timing for the x driver 24 to capture one line of display information. The FLM signal 22 indicates the timing of the first line scanned by the Y driver, and synchronizes the vertical scanning of the screen.

The logical display information of the serial signal lines 14 to 16 is converted into physical display information on the pallet 27 and sent to the x driver 24,
It is latched at the timing of the CL2 signal 19.

The x driver 24 receives the physical display information of 6 bits per dot, converts it into analog gradation information, and drives the liquid crystal display panel 26 in synchronization with the scanning of the y driver 25.

The pallet 27, which is the point of the present invention, can be constituted by an 8 word × 6 bit memory by connecting the serial signal lines 14 to 16 which are the logical display information to the address line and connecting the data line to the driver 24. .

In short, the contents (data) of the memory corresponding to each address determine 64 gradation levels corresponding to each of the eight pieces of logical display information.

The present invention can be applied not only to a single-color multi-tone display but also to a multi-color display, and the contents of a pallet incorporated in a liquid crystal display device can be read and written from outside.

Hereinafter, an example in this case will be described as a second embodiment.

FIG. 5 is a block diagram of a host-side display system circuit showing a second embodiment. In the figure, circuit blocks and the same signal lines having the same functions as those in FIG.

In the figure, 5a is a display conversion circuit, 11a is a serial memory, 28 is a serial signal line indicating logical display information, 29 is a serial port controlled by the MPU 1, and 30 is a serial data line.

Reference numeral 31 denotes a color liquid crystal display device capable of displaying 260,000 colors with a built-in palette that can be read and written by the MPL 1 via the serial port 29.

In the present embodiment, the display memory is increased in order to use 16 types of logical display information (5a), and the serial signal line 28
Is newly connected to the liquid crystal display device 31. Further, in order to reduce the number of signal lines connected to the liquid crystal display device 31, the contents of the palette inside the liquid crystal display device 31 are accessed via the serial port 29.

This serial port 29 can be easily realized by a commercially available communication control LSI.

Next, the liquid crystal display device 31 will be described with reference to FIG.

FIG. 6 is a block diagram showing details of the liquid crystal display device 31. As shown in FIG.

5, the same circuit blocks and the same signal lines as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted. In the figure, 32
Is MPU with built-in ROM, RAM and serial port, 33 is MPU32
Write signal line, 34 is the MPU32 read signal line, 35 is the MPU32
Data bus, 36 is an output port line of the MPU 32, 37 is a selection circuit, 38 is a composite address bus, 39 is a palette of 16 words × 6 bits, and 40 to 42 are 6 corresponding to red, blue and green color components. A physical display bus having a bit configuration, 43 is an x driver corresponding to color display, and 44 is a liquid crystal display panel for displaying color information.

The MPU 32 has the serial data line 30 connected to the serial port with the host, and receives write information to the pallet 39 or read request information from the pallet 39 from the host.

When a read request is received, information is read from the pallet 39 and output to the serial data line 30.

When the MPU 1 reads / writes the contents of the pallet 39, first, the output port line 36 is controlled and the selection circuit 37
The U32 address bus is selected.

As a result, the composite address bus 38 becomes the address information of the MPU 32. In this state, the write signal line 33 is enabled at the time of the write operation, and the write information received from the host via the serial data line 30 to the data bus 35. Is output.

On the other hand, at the time of read operation, the read signal line 34 is enabled,
The read information is read from the pallet 39 via the data bus 35, and then output to the host via the serial data line 30.

When the reading and writing are completed, the MPU 32 controls the output port 36 so that the selection circuit 37 selects the serial data lines 14 to 16 and 28 which are the logical display information.

As a result, 6-bit physical information corresponding to the 4-bit logical display information of the composite address bus 38 is output from the pallet 39 to the physical display buses 40 to 42.
Can receive 260,000 colors of physical display information, generate gradation information for each color component of red, blue, and green, and drive the liquid crystal display panel 44.

By the way, if the LCD panel 44 has 640 x 400 dots,
It has (640 × 3) × 400 pixels.
Make up the dots. In short, 1920 in red-blue-green order
It has a pixel configuration.

 Here, the details are shown in FIG.

Since the information of the physical display bus 40 of the red component is a 6-bit gradation (64-level gradation), the x driver 43 outputs the red 1
It outputs 64-level analog information for the pixel. The same applies to the blue component and the green component. This enables display of 260,000 colors.

 Next, the pallet 39 will be described in detail.

FIG. 8 is a block diagram showing details of the pallet 39.
In the figure, the same reference numerals are given to circuit blocks and the same signal lines having the same functions as those in FIG. 6, and description thereof will be omitted.

In the figure, 45 is an address decoder, 46 to 48 are decode signal lines 49 to 51 are 16 word × 6 bit RAM blocks.

When the 6-bit address information output by the MPU 22 is input from the composite address bus 38 to the pallet 39, the decoder 45, when the information on the composite address bus is at addresses O to F, decodes the decode lines 46, 10O to 1F. The hour decode line 47 and the hour decode line 48 at addresses 2O to 2F are enabled.

On the other hand, each of the RAM blocks 49 to 51 stores physical display information corresponding to the red, blue and green color components. Therefore, O
The content of the address is physical display information of the red component of logical display information 0,
Address 1 corresponds to the physical display information of the red component of the logical display information 1. Similarly, address 1O and address 2O are logical display information 0
Corresponding to the physical display information of the blue component and the green component.

Each of the RAM blocks 49 to 51 has a configuration of 16 words × 6 bits. The details of the RAM block 49 will be described below.

FIG. 9 is a block diagram showing details of the RAM block 49.

In the figure, circuit blocks and the same signal lines having the same functions as those in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted.

In the figure, 52 and 53 are NAND circuits, 54 and 55 are 16 words × 4 bits RAM, and 550 is a 3-state buffer.

When the decode line 46 and the write signal line 33 become valid, the NAND circuit 52 outputs a write signal to the RAMs 54 and 55. Therefore, the information on the data bus 35 at this time is
It is written to the address indicated by 38.

On the other hand, when the decode line 46 and the read signal line 34 become valid, the high-impedance state of the buffer 550 is released, so that the contents of the address indicated by the composite address bus 38 at this time are transferred to the data via the physical display bus 40. Output to the bus 35. When the read operation is completed and the read signal line 34 becomes invalid, the buffer 550 becomes a high impedance state again, and the information on the physical display bus 40 does not affect the data bus 35.

The RAMs 54 and 55 shown here may use commercially available TTL elements or the like.

In this embodiment, the RAM 54 is connected to the lower bits of the data bus 35, and the RAM 55 is connected to the upper 2 bits of the data bus 35.

As described above, the contents of the palette built in the liquid crystal display device can be read and written from the outside, and the host can rewrite the contents of the palette as needed,
Multi-color display such as all colors is also possible.

In particular, conventionally, it was necessary to input 18 bits of physical display information from the outside, but according to the present invention, a total of 5 bits of 4 bits of logical display information and 1 bit of serial data information
260,000 colors can be displayed with a bit.

As described above, according to the present invention, the logical address information is
The focus is on being limited by the cost of the display memory. Assuming that the cost (capacity) of the display memory is kept constant, the resolution of the display system and the amount of logical display information are in inverse proportion.

That is, when the resolution is reduced, the amount of logical display information can be increased. According to the above-described embodiment, the logical display information is 16 colors at 640 × 400 dots, but the logical display information can correspond to 256 colors at 320 × 200 dots.

An example in which the resolution and the corresponding color of the logical display information are variable will be described below as a third embodiment.

FIG. 10 shows a logical display information of 16 colors at a resolution of 640 × 400,
And 256 logical display information with a resolution of 320 x 200 dots
It is a block diagram of a host side display system circuit of a display system which can be changed to a color.

In the figure, circuit blocks and the same signal lines having the same functions as those in FIG.

56 and 57 are 4-bit to 1-bit parallel conversion circuits,
Reference numeral 61 denotes a combined logical display information line for transmitting 2-bit logical display information in a time-division manner. Reference numeral 62 denotes a liquid crystal display device capable of responding to 256 colors of logical display information.

 The display memory 3 is an 8-bit data memory.

When the logical display information has 256 colors at a resolution of 320 × 200, among the 8 bits of each display memory, n (n = 1, 2,
3 and 4) and 2 bits of the (n + 4) th bit are assigned to one pixel. That is, data for four pixels per address. Then, for example, the 8 bits of each display memory 3 are distributed to the parallel / parallel conversion circuits 56 and 57, and are converted into serial data.
It is converted into 2 bits × 4 time-divided logical display information for each pixel.

The same processing is performed for the other three display memories,
A total of 8 bits of logical display information (256 colors) of 4 bits are generated.

Further, when the logical display information is 8 bits, the number of signal lines connected to the liquid crystal display device 62 increases, so that the logical display information is further time-divided into 2-bit logical display information,
Output to 58-61.

In this case, since the display resolution is low, there is no problem that the frame frequency is lowered even if the transfer speed of the logical display information is reduced. Therefore, time division transfer can be realized. Thereby, the signal lines connected to the liquid crystal display device 62
It can be a book.

When the logical display information has 16 colors at a resolution of 640 × 400, one bit among the eight bits of each display memory is assigned to one pixel. In this case, the first to eighth pixels are
1, 3, 5, 7, 2, 4, 6, and 8 are stored in the display memory in this order. That is, data for eight pixels is used for one address. Then, for example, the 8 bits of each display memory 3 are distributed to the parallel / parallel conversion circuits 56 and 57, converted into serial data, and converted into 2-bit × 4 time-division logical display information for every two pixels.

The same processing is performed for the other three display memories,
Bit x 4

Further, as in the case where the logical display information is 256 colors, two bits are further time-divided to generate a composite logical display signal line.
Output to 58-61.

As a result, logical display information of parallel 4 bits (16 colors) is sequentially output to the liquid crystal display device 62 for each pixel.

In the above example, the case where the logical display information has 16 colors at the resolution of 640 × 400 and the logical display information has 256 colors at the resolution of 320 × 200 has been described. By changing the number of bits, it is possible to cope with a case where the logical display information has a resolution of 160 × 100 and the number of colors is 64,000, or a multi-color display with more than that.

Next, the liquid crystal display device 62 according to the present embodiment will be described.

The liquid crystal display device 62 in the present embodiment supports both 320 × 200 dot 256-color display and 640 × 400 dot 16-color display.

This display mode switching information is sent to the liquid crystal display device 62 via the serial port 29. That is, information exchanged between the serial port 29 and the liquid crystal display device 62 is not limited to pallet read / write information.

FIG. 11 shows a configuration of a liquid crystal display device 62 according to the present embodiment.

In the drawing, circuit blocks and the same signal lines having the same functions as those in FIGS. 10 and 6 are denoted by the same reference numerals, and description thereof will be omitted.

In the figure, 63 is an output port line for switching the display mode, 64
Is a logical display information converter, 65 is a logical display information bus, 66 is 25
This is a palette with a RAM configuration of 6 words x 18 bits.

The MPU 32 receives the display mode information from the host via the serial data line 30 and controls the output port line 63.

The logical information conversion unit 64 includes an output port line 63 as described later.
, The logical display information is determined to be 16 colors or 256 colors, and the logical display information is output to the palette 66.

That is, in the 256-color mode, the time-divided 4-bit logical display information is expanded into 8-bit logical display information and output.

The pallet 66 has an increased RAM capacity with an increase in logical display information, and can be easily configured by increasing the number of memory elements shown in the second embodiment.

On the other hand, the liquid crystal display panel 26 has a resolution of 640 × 400 dots. On the other hand, in order to display information of 320 × 200 dots, it is sufficient to display the information in units of 4 dots in order to double the size both vertically and horizontally.

 This method is a general method and is easy to realize.

Therefore, the details of the logical information conversion unit 64 that adjusts the logical display information amount, which is the main point of the present embodiment, will be described.

 FIG. 12 shows the configuration of the logical information conversion unit 64.

In the figure, circuit blocks and signal lines having the same functions as those in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted.

In the figure, 67 is a 4-bit latch circuit, and 68 is a logical product circuit.

In the 16-color display mode, since the output port line 63 is in the “L” state, the output of the AND circuit 68 is “L”. Therefore, the information on the combined logic display signal lines 58 to 61 is output to the logic display information bus 65 as it is, as in the second embodiment.

On the other hand, in the case of the 256-color display mode,
It is necessary to convert the information of 8-61 into 8 bits. Therefore, at the timing of the data shift signal line 19, the 4 bits of the logical display information sent first time are latched, and together with the 4 bits of the logical display information sent second time, the logical display information is 8 bits. Output to the logical display information bus 65.

By the operation of the logical information conversion unit 64, various display modes can be supported.

In this example, the 16-color display mode of 640 x 400 dots and 320 x 2
It corresponds to two modes of a 256-color display mode of 00 dots, but can also correspond to a 64-color mode of 640 × 200 dots and the like.

As described above, the provision of the means for exchanging information with the outside of the liquid crystal display device not only simply reads and writes the contents of the pallet, but also allows the liquid crystal display device to have various internal display modes. An intelligent liquid crystal display device capable of performing timing adjustment and the like can be provided.

By the way, in the second and third embodiments, an MPU is provided inside the liquid crystal display device to realize information exchange with the outside.

On the other hand, an example in which hardware is simplified so that only simple information can be exchanged in pursuit of cost merit will be described as a fourth embodiment.

FIG. 13 shows a configuration of a host-side display system circuit according to the fourth embodiment.

In the figure, circuit blocks and the same signal lines having the same functions as those in FIG.

In the figure, 69 is a selection circuit, 70 is an input port for reading information on the synchronization signal line 17, 71 is an output port for controlling information transfer to the liquid crystal display device 74, 72 is a selection signal line, 73 is a write signal line, 74 Is a liquid crystal display device for inputting logical display information and pallet write information in a time-division manner.

The selection circuit 69 normally selects the logical display information of the serial signal lines 14 to 16 and 28 and outputs it to the liquid crystal display device 74.

In the present embodiment, the pallet is read and written during the flyback period by utilizing the characteristic of the liquid crystal display device that the display information during the flyback period does not affect the actual display.

In other words, the logical display information and the read / write information are time-divided,
Since the transfer is performed, the number of signal lines connected to the liquid crystal display device can be reduced.

When writing to the pallet inside the liquid crystal display device 74, the MPU 1 first detects a retrace period via the input port 70.

After the detection, the MPU 1 outputs the signal to the selection circuit 69 via the output port 71.
The selection signal line 72 is controlled so as to select the data bus of the MPU1.

Next, the write signal line 73 is also output through the output port 71.
Output the pulse information and access the pallet via the data bus. With the above operation, the liquid crystal display device 74
Internally, a write operation is performed on the pallet.

After the writing is completed, the selection signal line 72 is controlled to return the selection circuit 69 to a state where the logic display information is selected.

 With the above procedure, the pallet writing operation is completed.

Next, a liquid crystal display device 74 according to the present embodiment will be described.

FIG. 14 shows a configuration of a liquid crystal display device 74 according to the present embodiment.

In the figure, the same reference numerals are given to circuit blocks and the same signal lines having the same functions as those in FIG. 13, and description thereof will be omitted.

In the figure, 75 is a time division bus output from the selection circuit 69, and 76 is 4
Bit latch circuit, 77 is a write control unit, 78 is a latch 76
Light signal line of 79, light signal line of pallet 80, 80
This is a 16 word × 18 bit RAM configuration palette.

During the display period, the logical display information is sent to the pallet 80 via the time division bus 75 and is converted into physical display information.

On the other hand, when pulse information enters the write signal line 73 during the flyback period, the write control unit 77 sequentially outputs pulse information to the write signal lines 78 and 79.

The first pulse information is output to the write signal line 78, and the information of the time division bus 75 is held in the latch 76. The second pulse information is output to the write signal line 79, and the contents of the palette corresponding to the logical display information indicated by the information of the time division bus 75 are rewritten. That is, the information of the latch 76 held in the first write operation is written.

The third pulse information is output again to the ride signal line 78,
Next, the physical display information of the pallet 80 to be rewritten is held in the latch 76, and the physical display information corresponding to the logical display information indicated by the information of the time division bus 75 is rewritten by the fourth pulse information.

As described above, by using the time-division bus 75, writing of the pallet 80 can be performed with simple hardware such as the latch 76 and the write control unit 77.

In particular, by using the time-division bus, the number of external connection signal lines that increase for writing pallet information can be reduced to only one write signal line.

As described above, according to the above-described embodiment, since logical display information is input to the liquid crystal display device, the number of externally connected signal lines is reduced, and the wiring area on the substrate that controls the liquid crystal display device is reduced. Can be reduced.

In addition, there is an effect on high-density mounting in that the cable connector can be downsized. Further, by reducing the number of signal lines of the cable, there is also an effect of reducing interference radio waves generated from the cable.

In addition, by providing a means for transmitting and receiving information from the outside in the liquid crystal display device, the operation mode inside the liquid crystal display device can be switched, so that various display modes such as resolution and the number of colors can be supported. There is.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a display system and a liquid crystal display device that can reduce the amount of data required to be transferred between the host device and the liquid crystal display device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a display system circuit according to a first embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a display system circuit according to a first conventional example, and FIG. FIG. 4 is a block diagram showing a configuration of a display system circuit according to a second conventional example, and FIG.
Block diagram showing a configuration of a liquid crystal display device according to the embodiment of
FIG. 5 is a block diagram showing a configuration of a display system circuit according to the second embodiment, FIG. 6 is a block diagram showing a configuration of a liquid crystal display device according to the second embodiment, and FIG. FIG. 8 is a block diagram showing the configuration of a pallet according to the second embodiment, and FIG. 9 is an RA according to the second embodiment.
FIG. 10 is a block diagram showing a configuration of an M block, FIG. 10 is a block diagram showing a configuration of a display system circuit according to a third embodiment of the present invention, and FIG. 11 is a configuration of a liquid crystal display device according to a third embodiment. FIG. 12 is a block diagram showing the configuration of a logical information conversion unit according to the third embodiment, FIG. 13 is a block diagram showing the configuration of a display system circuit according to the fourth embodiment, and FIG. FIG. 14 is a block diagram illustrating a configuration of a liquid crystal display device according to Example 4. 1 ... MPU, 2 ... LCTC, 3, 4, 5 ... Display memory,
9, 10, 11 ... parallel conversion circuit, 18 ... liquid crystal display device, 23
…… Timing circuit, 24 …… X driver, 25 …… Y driver, 27 …… Pallet, 29 …… Serial port, 32 ……
MPU, 44: LCD panel, 45: Decoder, 49, 5
0, 51: RAM block, 54, 55: RAM, 64: Logical information conversion unit, 70: Input port, 71: Output port, 77: Write control unit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Nobuo Tsuchiya 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Within Hitachi Video Engineering Co., Ltd. (72) Inventor Hiroyuki Mano 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. (56) References JP-A-61-205983 (JP, A) JP-A-64-46794 (JP, A) JP-A-58-155873 (JP, A) JP-A Sho-63 −132363 (JP, A)

Claims (2)

(57) [Claims] 1. An information processing apparatus comprising: a host device; and a liquid crystal display device having a dot matrix type liquid crystal panel, wherein the host device comprises: a display memory for storing logical display information; A circuit for generating and outputting a synchronizing signal for use with the synchronizing signal, and n bits for specifying a color within 2 n colors that can be simultaneously displayed on the liquid crystal display panel from the display memory in synchronization with the synchronizing signal. A time-division output circuit for reading the logical display information and outputting the read logical display information in a time-division manner. The liquid crystal display device comprises: a port to which the logical display information is input; and the host A logical information conversion unit for converting logical display information input from the device in a time-sharing manner into n-bit logical display information; A pallet circuit for converting into m-bit (m> n) physical display information designating a color in a displayable 2 m-th color, and a driver circuit for performing a display corresponding to the converted physical display information on the liquid crystal panel And the time-division output circuit includes: a first display mode in which the number of bits of logical display information for one dot is 2 times the bit width of the port to the L-th power (L is a natural number); In the second display mode in which the logical display information for one dot is output in a time-division manner and the number of bits of the logical display information for one dot is equal to the bit width of the port, the logical display information for a plurality of dots is output. In the case of the first display mode, the logical information conversion unit converts the logical display information input by time division into n-bit logical display information and outputs the logical display information, In display mode, time-division input Display system, characterized in that the physical display information, and outputs it. 2. A liquid crystal display device having a dot matrix type liquid crystal panel, wherein n bits of logical display information for specifying a color within 2 n colors that can be simultaneously displayed on the liquid crystal panel are time-divisionally displayed. A first port to be input; a second port to which display mode information is input; and a display mode to input logical display information input from the first port in a time division manner from the second port. A logical information conversion unit that converts the logical display information into n-bit logical display information in accordance with the information; and designates a color in a 2 m color that can be displayed on the liquid crystal panel with the logical display information having the changed number of bits. a pallet circuit for converting into physical display information of m bits (m>n); and a driver circuit for performing display corresponding to the converted physical display information on the liquid crystal panel. Dot theory In the first display mode in which the number of bits of the display information is 2 times the bit width of the first port (L is a natural number), logical display information for one dot is input in a time-division manner. In the case of the second display mode in which the number of bits of the logical display information for dots is equal to the bit width of the first port, the logical display information for a plurality of dots is input in a time-division manner, In the case of the first display mode, the logical display information input in a time-division manner is converted into n-bit logical display information and output, and in the second display mode, the logical display information input in a time-division manner A liquid crystal display device that outputs information as it is.