JPH0658216B2 - Pattern defect determination device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for inspecting a pattern on a printed board, an integrated circuit or the like, and particularly by comparing two patterns which have the same shape. The present invention relates to a pattern defect determination device that determines a defect if there is a difference.

[Background of the Invention]

FIG. 12 shows the entire configuration of an example of the pattern inspection apparatus, but in this case, the circuit scale for pattern comparison becomes unnecessarily large.

That is, the pattern 2 to be inspected mounted on the XY stage 1 is imaged by the pattern detector 4 via the objective lens 3. The image pickup signal is binarized by the binarization circuit 5 and becomes the pattern signal 10 to be inspected. Then, the pattern signal 10 to be inspected is synchronized with the signal from the synchronizing signal generator 8 and compared with the standard pattern signal 9 read from the standard pattern generator 6 in the defect judgment device 7 to perform defect inspection. Is to be done.

By the way, in the conventional pattern defect determination apparatus, while superposing the inspected pattern and the standard pattern,
The actual condition is that the inspection is performed in real time in synchronization with the input of each pattern signal.

FIG. 13 shows an outline of the defect determination device so far. The contents of signals corresponding to the inspected pattern signal 10 and the standard pattern signal 9 in FIG.
In addition to being two-dimensionally arrayed and developed on 13 and 12, a local region in the pattern to be inspected is cut out by a window F _{o, o} having a predetermined number of pixels (n × n). Similarly, a pattern corresponding to the local area is cut out from the standard pattern, and pattern comparison is performed for each corresponding pixel between both patterns.

However, in general, there are errors in manufacturing the pattern to be inspected,
The circuit configuration shown in the drawing is adopted to allow the positional deviation error (± m pixels) in both X and Y directions caused by the pattern detection error. That is, the size is ((2m + 1) × (2m +
1) A window G _{m, m} , G _m which has a size of (n × n) and is evenly arranged by one pixel in each of the X and Y directions over the entire surface within the pixel positional deviation allowable range. _{, m-1} … ， G _{o, o} ，… G
patterns cut out from each of _{-m + 1, -m} , G _{-m, -m} ,
The pattern from the window F _{o, o} is configured to be compared by the comparison / determination group 14.

The judgment result of each of the comparison / determination devices is ORed by the OR gate 15 and obtained as the comparison / determination signal 11.If the pattern is matched by any of the comparison / determination devices, the comparison / determination signal is in a so-called high level state. It will be obtained as.

However, in each of the comparison / determination devices, as shown in FIG. 14, it is necessary to take the exclusive OR with the exclusive OR gate group 16 corresponding to each (n × n) pixel in the cutout pattern. Specifically, each of the comparison / determination units includes n ² exclusive OR gates and a plurality of (for detecting whether or not the states of these gate outputs are all at a low level (“0”)). n ² ) input NOR gate 17 is required. This means that (2m + 1) ² comparison decision units are required for the entire standard pattern cut-out windows G _{m, m} , G _{m-1, m} ..., G _{−m, −m} , and Is
n ² × (2m + 1) ² exclusive OR gates are required.

For example, the window size is set to 5 × 5 pixels (n = 5), and the positional deviation allowable value is ± 5 pixels (m = 5) in the X and Y directions.
In that case, 3025 (= 5 ² × (2 × 5 + 1) ² ) pieces are required by the number of exclusive OR gates. Considering the tendency that the pixel size at the time of pattern detection becomes smaller and the allowable positional deviation amount m becomes relatively larger as the circuit pattern becomes finer and higher in density, the circuit scale and the number of wiring lines are increased. It means enormous growth.

A known example related to this type of device is "Automatic Inspection of Mask Defects (SPIE).
Vol.100 Semi-conductor Microlithography II 1977
, P26-36), "Detection Method of Circuit Pattern Defects by Extracting and Comparing Local Features" (IEICE Thesis: Sho58-
395, P-117) and the like.

[Object of the Invention]

In order to solve the above-mentioned problems of the prior art, the object of the present invention is to enable defect determination of a pattern to be inspected at high speed without performing duplicate comparison inspection, and also in a simple circuit configuration in real time. A pattern defect determination device is provided.

[Outline of Invention]

To this end, according to the present invention, a local area pattern (inspection window) of n × n pixels is arranged in the X direction from the inspected pattern in order to reduce the circuit size by reducing the duplicate inspection of the inspected pattern. , The Y direction is sequentially cut out in a cycle of every one pixel, and the cut out local area pattern is compared with each of the standard patterns within the positional deviation allowable range of ± m pixels corresponding thereto, and the comparison result The entire surface of the pattern to be inspected is inspected by determining the presence or absence of a defect. That is, according to the present invention, an image pickup means for two-dimensionally scanning and picking up a pattern to be inspected to detect a pattern image signal to be inspected, and a pattern image signal to be inspected detected by the image pickup means are binarized. The binarizing means for converting into the binarizing means, the binarized inspected pattern signal binarized by the binarizing means, and the binarized standard pattern signal generated in synchronization with the inspected pattern image signal. m (m: an integer of 2 or more predetermined to allow positional deviation in the horizontal and vertical directions; the same applies hereinafter) Comparison is performed in a state where relative positional deviation within pixels is allowed, and the above-mentioned inspection is performed due to a mismatch. In a pattern defect determination device for determining a pattern defect, the binarized standard pattern signal is
It is composed of a delay circuit for delaying by a pixel and a shift register group having a capacity of one horizontal scanning line width, and the binary standard pattern signal delayed by the delay circuit is inputted and sequentially (2
A first shift memory that outputs a binarized standard pattern signal for (m + 1) horizontal scanning lines, and each binarization for (2m + 1) horizontal scanning lines output from the first shift memory. A standard pattern signal is input and n (n: an integer greater than or equal to 2 determined according to the size n × n of the inspection window; the same applies hereinafter) pixels are output in parallel and cut out in parallel with a capacity of n pixels or more. The first (2m + 1) register group of the output format and the binarized inspected pattern signal output from the binarization circuit are input and the (m + 1) th horizontal scanning line is binarized inspected. A second shift memory that outputs a pattern signal and a binarized inspected pattern signal of the (m + 1) th horizontal scanning line from the second shift memory are input, and parallel output is output at n pixels or more and cut out. A second register of the parallel output format more capacitive pixels, were cut in a register of said 2 (m
A third register for storing the parallel output with n or more pixels of the binary-coded inspected pattern signal of the +1) th horizontal scanning line and holding it for every 1 (integer of 1: 2 or more, the same applies) pixel clock cycle. And the binarized inspected pattern signal of the (m + 1) th horizontal scanning line for each n pixel section, which is held from the third register for one pixel clock cycle and is output in parallel every pixel clock cycle, and First (2m + 1)
The output of the (2m + 1) comparison circuits and the output of the (2m + 1) comparison circuits that match or do not match the binarized standard pattern signal for each n pixel section output in parallel from each register of the register groups. Third (2m + 1) shift memories, which are provided correspondingly and sequentially cut out coincidence / non-coincidence signals from each of the (2m + 1) comparison circuits over m horizontal scanning lines, and the third (2m + 1) shift memories. ) Output from the (2m + 1) logical product circuits and the logical product of the match signals over the n horizontal scanning lines sequentially cut out by each of the shift memories. n
A first logical sum circuit for taking a logical sum of logical product signals of the coincidence signals over the horizontal scanning lines and outputting a coincidence signal within the range of (2m + 1) horizontal scanning lines (permissible vertical position deviation); Of the coincidence signal output from the logical sum circuit of (2m + 1) pixels and the coincidence signal of (2m + 1) pixels cut out by the clipping circuit over (2m + 1) pixels. A second logical sum circuit that outputs a coincidence signal within a range of (2m + 1) pixels (horizontal position deviation allowance), allows position deviation of ± m pixels in the horizontal and vertical directions, and has a size n.
The xn inspection window is intermittently set at intervals of 1 pixel or more, and the binary determination pattern signal of the inspection window and the corresponding binary standard pattern signal are compared and determined to determine the second A pattern defect determination device characterized in that it is configured to determine a defect of a pattern to be inspected based on a mismatch signal output from an OR circuit.

Example of Invention

 The present invention will be described below with reference to FIGS. 1 to 11.

First, the outline of the present invention will be described with reference to FIG. 2. The present invention is designed to perform pattern defect determination processing in real time in synchronization with pattern detection by a pipeline method. The outline is as follows. is there.

That is, the local area pattern f _o of n × 1 pixel first horizontal scanning direction from the inspection pattern is cut sequentially to the pixel spacing in the shift memory 13, it is maintained.

The comparison and determination is performed by the comparison and determination device 22 in parallel with each of the local area patterns g _i cut out by the shift memory to the same size as the above area from the positional deviation allowable range of the standard pattern. As a result, a binary judgment value representing a match / mismatch is obtained.

After that, the judgment values are sequentially input to the shift memory in correspondence with the local area pattern g _i, and are arranged two-dimensionally corresponding to the inspection pattern. On the other hand, from this array data, a region of 1 × n pixels (X direction 1 and n in Y direction) is sequentially cut out in the vertical scanning direction, and it is determined whether all the determination values are coincidence signals. .

As a result of the combination as described above, the comparison result of the two-dimensional local region F (x _o , y _o ) of n × n pixels can be obtained.

More specifically, n × 1 from the pattern to be inspected
For pixels of the clip region f _o, on a standard pattern in the corresponding position within the range of position shift tolerance ± m pixels in the Y direction (2m + 1) n × 1 for cutting out the pieces of local area
Pixel windows g _m , g _m-1 , ..., g _-m are provided in parallel,
Window g _m, ..., and the pattern from g _-m each area f _o
It is designed such that the comparison with the patterns from (1) to (3) is performed in parallel at the same time.

Each result is simultaneously recognized in parallel by the shift memory and the cutout decision circuit provided corresponding to the windows g _m , g _m-1 , ..., G _-m .

Furthermore, the pattern from the region f _o cut to remain that,
Window _{g m, g m-1,} ..., patterns from g _-m each shifted one pixel within a positional shift tolerance in the X direction (+ m to-m pixels), from the region f _o After being compared with the pattern, these comparison results are also subjected to recognition processing by the cutout determination circuit via the shift memory as in the previous case.

The recognition processing results corresponding to the windows g _m , g _m-1 , ..., G _-m are then logically ORed, and again ORed through the serial-in / parallel-out shift register. , A final comparison and determination signal 23 (FIG. 2) is obtained.

Now, the present invention will be described in detail. FIG. 1 shows a basic configuration of an embodiment of the defect determining apparatus according to the present invention. Hereinafter, the cutout area n × n and the positional deviation allowable range + m
The case where ~ -m is n = 5 and m = 4 will be described.

The standard pattern signal 9 (upper left in FIG. 1) and the pattern signal 10 to be inspected are respectively y _i = 1; x _i = 1, 2, ..., K y _i = 2; x _i = 1 from the two-dimensional pattern. 2, ..., K 1 and the like are shifted and input serially in units of one pixel to the shift memories 12 and 13 in the defect determination device in synchronization with the clock.

Here, the standard pattern signal 9 is input to the shift memory 12 after passing through the shift register 18.

The shift register 18 is a serial-in / serial-out having a 4 (= m) bit length,
On the other hand, the standard pattern signal 9 functions so as to be relatively delayed by four pixels.

Further, the shift memory 12 is configured such that 8 (= 2 m) stages of shift registers each having a length corresponding to one scanning line width 1H are provided, and the shift registers 18 are sequentially output from each other by a delay of 4 pixels. The standard pattern signal 9 is arranged in two-dimensional image data.

Furthermore, the shift register group 19 sequentially cuts out 5 (= n) pixels in the horizontal direction and 9 (= 2m + 1) pixels in the vertical direction from this array pattern in synchronization with the clock by pipeline processing. It is composed of serial-in / parallel-out shift registers 19-1 to 19-9 each having a bit length.

On the other hand, the shift memory 13 has a configuration in which 4 (= m) stages of shift registers each having a length of 1 scanning line width 1H are provided. The pattern signal 10 to be inspected is four pixels in the vertical direction with respect to the standard pattern signal from the shift register 18, that is,
It is delayed by 4H and is serially output from the shift memory 13.

The shift register 20 is a serial-in / parallel-out register having a length of 5 (= n) bits for cutting out pixels by receiving the output signal from the shift memory 13.

Therefore, with the above circuit, the standard pattern of 5 × 1 pixels cut out on the shift registers 19-1 to 19-9 is in the horizontal direction with respect to the inspection pattern of 5 × 1 pixels cut out on the shift register 20. And -4 pixels in the vertical direction and +4 to -4 pixels in the vertical direction.

These pattern cutting operations will be specifically described with reference to the examples shown in FIGS. 5 (a) and 5 (b). This figure shows a case where there is no positional deviation between the corresponding pixels on the standard pattern (a) and the pattern to be inspected (b), and when the same pattern exists.

Consider the timing when f (x _o , y _o ) of 5 × 1 pixel is cut out from the pattern to be inspected to the shift register 20 (lower left of FIG. 1). The shift registers 19-1 to 19-9 are shown in FIG.
As shown in (a), g (x _o −4, _yo +4), g (x _o −
4, y _o +3), ..., G (x _o −4, _yo −3), each pattern of 5 × 1 pixel is cut out.

The patterns are cut out from the shift registers 20, 19-1 to 19-9 by moving pixel by pixel in the horizontal direction sequentially in the order of x _o , x _{o + 1} , ... In synchronization with the clock signal. After the cutout in one horizontal scanning direction is completed, the pixel is further moved by +1 pixel in the vertical direction and returned to the head in the horizontal direction, and the movement and cutout in the horizontal direction are repeated again. As a result, the inspection pattern and the standard pattern are entirely scanned.

By the way, the register 21 (FIG. 1) samples and inputs the pattern cut out by the shift register 20 every 9 (= 2m + 1) clocks, and holds the cut out pattern until then.

This holding pattern and shift registers 19-1 to 19-9
The patterns cut out respectively are compared with the comparison circuits 22-1-1, 22-2-1 ..., 22 in the comparison / determination circuits 22-1 to 22-9.
It is designed to be compared in parallel in -9-1.

Here, considering the cutout pattern in the register 20 and the shift register 19-1, the cutout pattern f (x _o , y _o ) in the register 20 is constant for 9 clocks, but in the shift register 19-1 The cutout pattern of is g (x _o −4, _yo +
4), g (x _o -3, _yo +4), ..., g (x _o , _yo +4), ...,
It changes for each clock in the order of g (x _o +4, _yo +4).

Accordingly, the comparison circuit 22 determines the coincidence determination result with each pattern in the range shifted by -4 to +4 pixels in the horizontal direction at the position shifted by +4 pixels in the vertical direction between the 9 clocks.
It is obtained sequentially from -1-1.

Similarly, according to the shift registers 19-2 to 19-9, the respective patterns in the range shifted by -4 to +4 pixels in the horizontal direction at each of the positions shifted by +3 to -4 pixels in the vertical direction are cut out, and the comparison circuit 22-2-1, ..., 22-9
From -1, the coincidence determination result is sequentially obtained.

FIGS. 6 (a) and 6 (b) are for explaining the above operation. Five clocks elapse after the pattern of f (x _o , y _o ) is held in the register 20 (FIG. 1). It shows the latter state. The shift registers 19-1 to 19-9 have g (x _o , _yo +4), g (x _o , _yo +3), ..., G (x _o , _yo − −), respectively.
4) is cut out, and the state of the circuit at this time is shown in FIG.

The register 20 and shift registers 19-1 to 19-9 are
F (x _o , _yo ), g (x _o , _yo +4), g (x _o , _yo +3),
_{..., g (x o, y} o -4) each pattern cut out, comparing circuit 22-1-1, ..., so matching determination result is outputted as shown from 22-9-1 ing.

In the examples shown in FIGS. 6 (a) and 6 (b), it is assumed that there is no relative displacement between the standard pattern signal and the pattern to be inspected. Therefore, only the comparison circuit 22-5-1 (FIG. 7) outputs the coincidence determination signal "1" and the other outputs the non-coincidence signal "0".
The configurations of the comparison circuits 22-1-1, ..., 22-9-1 are the same.

Incidentally, as shown in FIG. 3, the comparison circuit 22-1-1 is configured to obtain an exclusive OR for each pixel and obtain a coincidence determination result by taking a logical product with a NOR gate.

The output results of the comparison circuits 22-1-1 and the like are sequentially input to the shift memories 22-1-2 (FIG. 1) and the like provided corresponding to them.

The shift memories 22-1-2, ..., 22-9-2 have the same circuit configuration, and as shown in FIG.
It is composed of five stages of long shift registers. After the coincidence determination signal is two-dimensionally developed, the AND of the 5-bit determination results in the vertical direction on the developed data is AND gate 22-1-3 or the cutout determination circuit.
It is calculated in 22-9-3 and output in synchronization with the clock (Fig. 1).

This output result serves as a coincidence determination signal for a 5 × 5 (n × n pixel) bit cutout pattern at each cutout position on the standard pattern.

The operation of this circuit is shown in FIGS. 8 and 9 for a specific example shown in FIGS. 5 (a) and 5 (b).

In FIG. 8, the coincidence determination signal (FIG. 7) is the shift memory 22-
The shift memory 22-5 after the pattern scanning for four scanning lines (4H) period has progressed after being input to 5-2
2 shows the internal state of No. 2. "1" in the shift register at the fifth stage shows the coincidence determination signal output after being shifted by 4H. That is, it is the result of matching detection between f (x _o , y _o ) and g (x _o , y _o ) in FIGS. 5 (a) and 5 (b).

Similarly, it is the result of the match detection between the f (x _o , y _o +1) and the corresponding standard pattern signal g (x _o , y _o +1) at the 4th stage. , it at the first stage _{f (x o, y o +2} ), f (x o, y o +3), f (x o, y o +4) each with a corresponding g of (x _o, y _o +2) , G (x _o , y _o +3), f (x _o , y _o
The result is a match detection result with +4).

Further, "0" means that it is determined that there is no corresponding pattern at each position of -1 to -4 pixels in the x direction with the same y coordinate for each f (x _o , _yo ) or f (x _o , _yo +4). Is shown.

Now, FIG. 9 shows the state of the shift memory 22-5-2 after (1H-1) clocks from the state shown in FIG. Then, f (x _o , y _o ) to f (x _o , y _o +4) (hereinafter, defined as F (x _o , y _o )) corresponding to the 5 × 5 cutout pattern of the pattern to be inspected is the standard pattern. It is detected by the AND gate 22-5-3 that it exists at the corresponding position of.

The output value of "0" output in the 4 clock periods before FIG. 9 and in the 4 clock periods after that is the same y coordinate on the standard pattern with respect to the above F (x _o , y _o ) pattern. The above shows that there is no corresponding pattern at each position where the x coordinate is shifted from -4 to -1 pixel and from +1 to +4 pixel.

The operation of the comparison / determination circuit 22-5 has been described above, but similarly in the comparison / determination circuits 22-1 to 22-4 and 22-6 to 22-9, the y-coordinates are -4 to -1, +1 to +4. At each position where the pixel shifts, the allowable positional shift in the x direction is -4 to +
The coincidence determination result of the F (x _o , y _o ) pattern in the four pixels is sequentially output in synchronization with the clock.

Here, returning to FIG. 1 again, description will be made.

The OR gate 22-10 calculates the logical sum of the output values of the comparison / determination circuits 22-1 to 22-9, and the pattern corresponding to each position deviated from -4 pixel to +4 pixel as the misregistration allowable range in the y direction. When there is one, "1" is obtained, and when there is no, "0" is obtained, and this determination result at each position of -4 pixels to +4 pixels, which is an allowable range of misalignment in the x direction, is output in synchronization with the clock for 9 clock periods. In addition, shift register 22-1
Entered in 1.

When the determination result of this 9-clock period is input to the shift register 22-11, the output result indicates the X / Y direction −4 to
The presence or absence of the corresponding pattern of F (x _o , y _o ) within the range of +4 pixels is obtained. That is, as is apparent from the operation state shown in FIG. 10 corresponding to the concrete examples shown in FIGS. 5 (a) and 5 (b), "1" is placed on the shift register 22-11 or the OR gate 22-10.
As a result of the input, the judgment value "1" of pattern matching is obtained from the OR gate 22-12.

The above-described determination is sequentially performed for each inspected pattern sampled and input to the register 21 shown in FIG.
The inspection of the entire surface of the pattern to be inspected is executed while determining "1" if the corresponding pattern exists within the positional deviation permissible range on the standard pattern and "0" if not.

By the way, in the above-described pattern defect determination, the sampling interval of F (x _o , y _o ) cannot be set smaller than the positional deviation allowable range 2m + 1. Therefore, the window width n of F (x _o , y _o ).
If n <2m + 1, there will be a region that cannot be inspected.

In order to eliminate such a problem, window F
It is necessary to set the sampling interval of (x _o , y _o ) to <2m + 1. To achieve this object, the circuit configuration shown in FIG. 11 may be used.

Figure 11 shows the size of the cut window of F (x _o , y _o ) 5 ×
5 (that is, n = 5) and the positional deviation allowable value m is ± 5 pixels (comparison determination range 2m + 1 = 11 pixels), the sampling interval of F (x _o , y _o ) = 4 pixels Is realized.

In this case, shift register 18 'and shift memory 1
2'and 13 'each have a 5-bit length, a 10-stage configuration, and a 5-stage configuration. The difference is that the shift register group 19', the shift register 20 ', and the register 21' have a 13-bit length. Is. These 13 bits are shown (19 ', 11th
As shown in the figure), it is divided into 3 in 5 bit units in the state that some bits are overlapped, and the comparison judgment device 16A corresponding to the division.
It is designed so that the comparison and judgment processing is performed in parallel at ~ 16C.

Although the present invention is as described above, theoretically, the shift register groups 19 (Fig. 1) and 19 '(Fig. 11) and the shift registers 20 and 20' are not necessarily required. However, in the actual IC, the shift memory 12, 12 ', 13, 13'
The parallel output format cannot be adopted as the individual shift registers constituting the above because of the limitation of the number of input / output pins. Therefore, the parallel output format shift register groups 19 and 19 ′ are externally provided.
And shift registers 20, 20 'are provided.
Up to now, a large number of exclusive OR gate ICs have been required, but in the case of the present invention, the number is greatly reduced. Therefore, not only the total number of ICs,
The number of wirings between ICs will also be greatly reduced.

EFFECTS OF THE INVENTION According to the present invention, the positional deviation of ± m pixels in the horizontal and vertical directions is allowed, and the inspection window of size n × n is intermittently set at intervals of 1 pixel or more, and the inspection is performed. Since the comparison judgment between the binarized inspected pattern signal of the window and the corresponding binarized standard pattern signal is performed on the entire surface of the inspected pattern, the defect determination of the inspected pattern can be performed at high speed without performing the duplicate comparison inspection. In addition, the circuit configuration can be simplified in real time.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of an embodiment of a main part of a pattern defect judgment apparatus according to the present invention, FIG. 2 is a view for explaining an outline of the main part of FIG. 1, and FIG. The figure which shows the concrete structure for comparing an inspection cut-out pattern and a standard cut-out pattern, FIG. 4 is a figure which shows the structure of the shift register for arranging a comparison result two-dimensionally, FIG.
(a), (b) is a diagram for explaining the pattern cutting operation, (a) is a standard pattern, (b) is a pattern to be inspected,
The corresponding figures, and Figures 6 (a) and 6 (b) are Figure 5 respectively.
FIGS. 7 (a) and 7 (b) are diagrams for explaining the operation after the lapse of 5 clocks, and FIG. 7 is a diagram for explaining the state of the main part of FIG. 1 after the lapse of 5 clocks from the state of FIG. 8 and 9 are diagrams showing the internal state of the shift memory after the elapse of four scanning line periods from the output of the coincidence determination signal of FIG. 7, and FIG.
FIG. 10 is a diagram showing the internal state of the shift memory after (1H-1) clocks from the state shown in the figure, FIG. 10 is a diagram for explaining the connection relationship between the OR gate and the shift register, and FIG. 11 is that of FIG. FIG. 12 is a diagram showing another embodiment of the main part, FIG. 12 is an overall configuration diagram of an example of a conventional pattern inspection apparatus, and FIG.
FIG. 12 is a schematic configuration diagram of a main part of FIG. 12, and FIG. 14 is a diagram showing a specific circuit configuration for comparing an inspected cutout pattern with a standard cutout pattern. 12, 12 ', 13, 13' ... Shift memory (for pattern two-dimensional array), 18, 18 '... Shift register (for delay), 19, 1
9 '... Shift register group (for standard pattern cutting), 2
0, 20 '... Shift register (for inspected pattern cutout), 21, 21' ... Register (for inspected cutout pattern holding), 22, 22A to 22C ... Comparison determination device, 22-1 to 22-9
... Comparison judgment circuit, 22-1-1, 22-2-1, ..., 22-9
-1 ... Comparison circuit (for cutting pattern comparison), 22-1-
2, 22-2-2, ..., 22-9-2 ... Shift memory (for comparison result two-dimensional array), 22-1-3, 22-2-3 ,.
-9-3 ... AND gate (for comparison result cutout determination),
22-10, 22-12 ... OR gate, 22-11 ... shift register.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yutaka Hashimoto 1 Horiyamashita, Hadano City, Kanagawa Pref., Kanagawa Factory, Hiritsu Seisakusho Co., Ltd. (56) References JP 62-140009 (JP, A)

Claims (1)

[Claims] 1. An image pickup means for two-dimensionally scanning and picking up a pattern to be inspected to detect a pattern image signal to be inspected, and a pattern image signal to be inspected detected by the image pickup means to be a binarized pattern signal to be inspected. The binarizing means for converting, the binarized inspected pattern signal binarized by the binarizing means, and the binarized standard pattern signal generated in synchronization with the inspected pattern image signal are ± m. (M: integer greater than or equal to 2 predetermined to allow positional deviation in the horizontal and vertical directions, the same applies hereinafter) Comparison is performed in a state where relative positional deviation within pixels is allowed, and the pattern to be inspected due to mismatch In the pattern defect judging device for judging the defect of No. 2, the binary standard pattern signal is constituted by a delay circuit for delaying by m pixels and a shift register group having one horizontal scanning line width capacity, and delayed by the delay circuit. A first shift memory and outputs a binary reference pattern signal for binarizing the reference pattern signal is sequentially inputted (2m + 1) number of horizontal scan lines,
Binary standard pattern signals for (2m + 1) horizontal scanning lines output from the first shift memory are input and n (n: determined according to the size n × n of the inspection window) A first (2m + 1) register group in a parallel output format having a capacity of n pixels or more, which outputs a parallel output with an integer of 2 or more (the same applies hereinafter) and cuts it out;
A second shift memory for inputting the binarized pattern signal to be inspected output from the binarization circuit and sequentially outputting the binarized pattern signal to be inspected for the (m + 1) th horizontal scanning line, and the second shift memory. A second register of a parallel output type having a capacity of n pixels or more, which inputs a binary-coded inspected pattern signal of the (m + 1) th horizontal scanning line from the memory, outputs a parallel output at n pixels or more, and cuts out; The parallel output is stored at 1 pixel or more in the binarized inspected pattern signal of the (m + 1) th horizontal scanning line cut out to the second register.
(An integer of 1: 2 or more, the same applies below) A third register that holds each pixel clock cycle, and a third register that holds the pixel register for one pixel clock cycle and outputs in parallel every pixel clock cycle. The binarized inspected pattern signal of the (m + 1) th horizontal scanning line for each n pixel section and the first
And (2m + 1) comparison circuits that make a match or a mismatch with the binarized standard pattern signal for each n pixel section output in parallel from each of the (2m + 1) register groups of
A third (2) which is provided corresponding to the output of the (m + 1) comparison circuits and sequentially cuts out the coincidence and non-coincidence signals from each of the (2m + 1) comparison circuits over the m horizontal scanning lines.
The logical product of the coincidence signals over the n horizontal scanning lines sequentially cut out by each of the (m + 1) shift memories and the third (2m + 1) shift memories is calculated (2m +
1) The logical product signals of the AND signals of the AND circuits and the n horizontal scanning lines output from the (2m + 1) logical product circuits are ORed to obtain (2m + 1) horizontal scanning lines (vertical A first logical sum circuit that outputs a coincidence signal within a (positional deviation allowance) range, a cutout circuit that cuts out the coincidence signal output from the first logical sum circuit over (2m + 1) pixels, and the cutout circuit. A second logical sum circuit for taking the logical sum of the coincidence signals over the (2m + 1) pixels cut out over the (2m + 1) pixels and outputting the coincidence signal within the range of the (2m + 1) pixels (horizontal displacement tolerance) By providing a ± m pixel position shift in the horizontal and vertical directions, and by intermittently setting an inspection window of size n × n at intervals of 1 pixel or more, with a binarized inspected pattern signal of the inspection window. A pattern characterized by being configured to perform a comparison determination with a corresponding binarized standard pattern signal, and to perform a defect determination of a pattern to be inspected based on a mismatch signal output from the second OR circuit. Defect determination device.