JPH063541B2 - Pattern inspection equipment - Google Patents

Description

The present invention relates to a pattern inspection apparatus, and in particular, to inspect patterns such as a printed circuit board and a mask for manufacturing the same, or an integrated circuit wafer and a mask for manufacturing an integrated circuit at high speed. The present invention relates to a pattern inspection device.

[Conventional technology]

FIG. 1 is a block diagram showing an example of a pattern detection unit of a conventional pattern inspection apparatus.

This device can ignore the probability that defects of the same shape exist at the same location in the chip because of the fact that the mask for manufacturing integrated circuits is composed of repeating circuit patterns of the same shape called a chip pattern and the nature of pattern defects. Based on the fact that different chip patterns 1A, 1 on the mask 1
Defects are detected by comparing B with each other.

That is, the bright spots of the flying spot scanner 2 are irradiated onto the corresponding patterns of the chip patterns 1A and 1B on the mask 1 by the objective lenses 3 and 4, and the photoelectric detectors 5 and 5 are irradiated.
It is converted into an electric signal at 6 and the electric signals are compared with each other.

FIG. 2 shows a principle diagram of the defect detection.

The respective portions 7A and 7B in which the corresponding patterns of the chip patterns 1A and 1B are represented by solid broken lines cannot be completely overlapped due to an error of an optical system and a mechanical system.
Only x and Δy are compared with a superposition error.

When the chip patterns 1A and 1B are overlapped with each other in this way, if there is a non-coincident portion, it is detected as a defect, but there is a possibility that a non-defective portion may be erroneously determined as a defect due to the unavoidable error described above. is there.

In this conventional technique, the pseudo defects are removed by allowing the inconsistency of the maximum allowable values δ _x and δ _y of the unavoidable overlay errors Δx and Δy between the normal patterns, and the inconsistency exceeding this, for example, The device is devised so that the portion 8 of the chip pattern 7A can be detected.

The problem here is that this method cannot detect defects less than the overlay error in principle. In recent LSI masks, the minimum size of the fabrication pattern is 2
Since the size is as small as ˜1 μm, the defect size that must be detected is as small as 1 μm or less. Therefore, it is necessary to keep the overlay accuracy at 1 μm or less.
It is very difficult to request this precision for mechanical systems and optical systems.

In other conventional techniques, this point is improved, the features of patterns to be compared and collated are drawn, and then the feature patterns are compared with each other.

The principle will be described with reference to FIG. For example, when attention is paid to a pattern feature having a minute pattern element, the portions indicated by the minute pattern elements 8A and 9A are detected from the partial pattern 7A of the chip pattern 1A.
On the other hand, only the minute pattern element 9B is detected from the partial pattern 7B of the chip pattern 1B. Therefore, these detected characteristic pattern elements are compared. For the feature 9A detected from the partial pattern 7A, the feature 9B detected from the partial pattern 7B exists within the distance range of the overlay error. On the other hand, the feature 8A detected from the partial pattern 7A does not have a corresponding feature in the partial pattern 7B. In this way, by comparing the characteristic patterns with each other within the distance range equal to or greater than the overlay error, it is possible to detect a defect equal to or less than the overlay error.

This method can detect defects with an overlay error or less as compared with the comparison between the original patterns as described above,
Defect detection depends on what kind of characteristic pattern element is selected. That is, the shape dependency of defects is extremely high.

[Problems to be Solved by the Invention]

By the way, there are various shapes of defects, and in order to detect defects of any shape, a feature extractor is required for each shape, and when implemented by hardware, its scale becomes enormous. Cost will inevitably increase. With software, the inspection time becomes enormous and it is not practical. In the prior art, this problem was dealt with by large-scale hardware, and a defect shape with a low appearance probability was compromised as inevitable and undetectable.

An object of the present invention is to provide an economical pattern inspection apparatus capable of performing a reliable and high-speed pattern inspection while preventing the misjudgment while significantly improving the defect detection sensitivity to solve the above-mentioned problems of the conventional art. To provide.

[Means for Solving the Problems]

In order to achieve the above object, the present invention provides an image pickup means for picking up a pattern to be inspected to sequentially obtain image signals, a reference pattern data generation means for sequentially generating reference pattern data, and an image sequentially obtained from the image pickup means The signal and the reference pattern data sequentially generated from the reference pattern data generating means are compared with each other by displacement correction, and the comparing means detects sequentially as defect candidates by the difference, and the position of the defect candidate portion sequentially detected from the comparing means. The first storage means for temporarily storing the image signal of the inspection target pattern whose displacement has been corrected as a defect candidate image signal in the image memory, and the reference pattern data sequentially generated from the reference pattern data generating means, are sequentially processed by the comparison means. Temporarily stores in the image memory the reference pattern data for which the positional deviation correction has been performed for the detected defect candidate portion. Partial reference pattern data corresponding to the defect candidate image signal temporarily stored in the second storage means, the image memory of the first storage means, and the defect candidate portion temporarily stored in the image memory of the second storage means. And analyzing the characteristic pattern elements in detail by comparing the two with different criteria to exclude pseudo defects that are not harmful for practical use, and to analyze the remaining defect candidates as true defects. It is a pattern inspection apparatus characterized in that.

[Action]

In the present invention, as the first stage defect candidate detection, the image signal sequentially obtained from the image pickup means and the reference pattern data sequentially generated from the reference pattern data generating means are subjected to the positional deviation correction so that the defect is surely detected. The "first sieving" is performed by a sensitive comparative detection to detect a defect candidate, and the image signal of the inspection target pattern of the defect candidate portion and the partial reference pattern data corresponding to the defect candidate portion are temporarily stored in the image memory. Remember.

Next, a control / processing unit (for example, an electronic computer) for the image signal of the defect candidate portion of the inspection target pattern including the periphery of the defect candidate temporarily stored in the image memory and the partial reference pattern data corresponding to the defect candidate portion. ), Compare both, and perform a detailed analysis of characteristic pattern elements such as minute patterns to perform “second sieving” to exclude those that are not defects in a practical sense from defect candidates. To detect defects.

In this case, most of what is detected as a pseudo defect is
Since this is considered to be caused by the alignment error, if this is included in the defect candidates of the "first sieving", a huge amount of defect candidate processing must be performed, and the processing capacity of the electronic computer or the like cannot keep up. Therefore, the position correction is actively performed so that such a defect is not included in the defect candidates.

Further, the pattern data during the detailed analysis by the electronic computer or the like is stored in the buffer memory, so that the pattern data is prevented from being lost during this period so that no inspection is generated.

As described above, the defect inspection can be performed in real time (at the same time as pattern imaging / scanning).

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of an embodiment of the pattern inspection apparatus according to the present invention, which is for the case of performing a visual inspection of a photomask for manufacturing a semiconductor integrated circuit, for example.
FIG. 7 is an explanatory view of the two-dimensional pattern scanning, FIG. 5 is a block diagram of an embodiment of the defect candidate detection unit, FIG. 6 is a block diagram of an embodiment of the defect detection circuit, and FIG. Is the time chart.

Here, 11 is a mask to be inspected, 12A is an XY stage related to the scanning / imaging unit, 12B is the same mechanism control device,
12C is the same coordinate measuring device, 13A is the same illumination light source, 13
B is the same condenser lens, 13C is the same microscope, 14
A is the same image pickup device, 14B is the same A / D converter, 14C
Is the same timing circuit, 15 is a defect candidate detection unit, 16
Is a bit pattern generator related to the reference pattern data generation unit, 17 is the same memory interface, 18 is the same reference data memory, and 19 is a control / processing unit.

First, the mask 1 to be inspected mounted on the XY stage 12A
1 is transmitted and illuminated by the illumination light source 13A and the condenser lens 13B, and the pattern image on the mask 11 obtained at this time is magnified by the microscope 13C, and this pattern image (optical image)
Is detected by the image pickup device 14A and converted into an electric video signal.

On the other hand, as the reference pattern, the reference data recorded in the reference data memory (for example, magnetic tape device) 18 is generated by the bit pattern generator 16 via the memory interface 17. This and the video signal from the image pickup device 14A are compared in real time in the defect candidate determination unit 15 and a defect determination process is performed.

Since a known method can be used for the bit pattern generation method, the description thereof will be omitted.

Next, in order to facilitate the understanding of the whole, the two-dimensional pattern scanning of the entire mask 11 to be inspected will be described.

As shown in FIG. 4 (a), the mask 11 to be inspected generally has a large number of functional patterns 111 of a glass 110 (a chip (one integrated circuit also called a die)) repeatedly arranged in X and Y directions. Has been done.

XY stage 12A equipped with the mask 11 to be inspected
Are driven by the mechanism control device 12B based on the data set and input in advance, and are controlled to scan the entire surface of the mask 11.

The situation at this time is shown in FIG. 4 (b). Patterns 111A and 111B of the IC (integrated circuit) chip are patterns of the same shape repeated, and the image pickup device 14A scans this pattern in the X direction with a single inspection width (sensor width) to validate the mask pattern. When the end of the portion 112 is reached, the scanning line is moved by one scanning line in the Y direction, and then the X stage is again moved and scanned in the opposite direction, thereby repeating the two-dimensional pattern scanning of the entire surface of the mask. Here, A in FIG. 4 (b),
An effective portion as a chip is shown by B, and a dicing area is shown by C.

Next, a specific configuration of the defect candidate determination unit 15 will be described. Here, the following conditions are set in this pattern inspection apparatus.

(I) The accuracy of the XY stage on which the mask to be inspected is mounted and the manufacturing accuracy when the mask is baked are several microns or less in the entire mask area. That is, the pattern detection error that occurs while the imager scans one chip is 0.1 to 0.2.
Within μm.

(II) When a true defect is detected, it is not necessary to inspect a certain area around it.

(III) No inspection is required in the boundary area between chips, that is, in the dicing area.

The configuration operation of the defect candidate determination section 15 will be described based on FIG.

The detection pattern video signal obtained by converting the analog image pickup signal of the pattern of the master 11 detected by the image pickup device 14A into a digital amount by the A / D converter 14B is two-dimensionally variable in output position according to a command from the control / processing unit 19. At the same time as being input to the multiplexer 24 through the position correction circuit 20, the buffer memory 22 (# 1 to #m) is sequentially input.

The buffer memory 22 is a memory composed of a shift register for temporarily pooling image data within a certain period of time, and the image data extraction unit has a position shift correction function.

Each output from each buffer memory 22 with this position deviation correction function becomes an input to the multiplexer 24, and either the output from the position correction circuit 20 or the output from the buffer memory 22 is selected to be supplied to the defect detection circuit 28. In addition to the input V _D , it is also input to the analysis memory 26 to store the defect candidate image data, and the control / processing unit 19 can later analyze the contents.

On the other hand, the reference pattern signal from the bit pattern generator 16 is input to the multiplexer 25 through the position correction circuit 21, and is sequentially input to each buffer memory 23 (#
1 to #m).

Each buffer memory 23 has the same purpose as that of the buffer memory 20, and the output from the output section having the positional deviation correcting function serves as the input of the multiplexer 25 and the input of the buffer memory 23 of the next stage. Has become. The output V _R of the multiplexer 25, the defect detection circuit 2
8 and the analysis memory 27, and the contents of this memory are later read by the control / processing unit 19 so that the contents can be analyzed.

First, in an initial state, the position correction circuits 20 and 21 and the position shift correction function units of the buffer memories 22 and 23 are
Set all in the center of the correctable range. This is performed by a command from the control / processing unit 19.

In the initial state, the multiplexers 24 and 25 select the position correction circuits 20 and 21 respectively, and the defect detection circuit 28 is selected.
The detection pattern video signal and the reference pattern signal itself are input to.

The defect detection circuit 28 is capable of defect determination in real time (that is, at a speed at which image data is detected by the image pickup device 14A).

The detection function will be described with reference to FIG. The output signal V _D of the multiplexer 24 on the detected image signal side is image data having multivalued information and is represented by a digital amount by the A / D converter 14B.

On the other hand, the comparators 281, 282, 283 respectively use the three low, middle, high threshold values Th _L , Th _H , Th _H provided from the control / processing unit 19 to generate the binary image data V _L , V _{H.
I try} to get _M and V _H.

The relationship between these three threshold values and the detected image data is shown in FIG. Actually, it is digital multi-valued data for easy processing, but is shown as an analog waveform for easy understanding.

As shown in this figure, when the pattern becomes very small, the resolution of the optical system is insufficient, so that 100% contrast can be obtained even for a photomask which originally has a black and white binary pattern as a detected image signal. Disappear. Therefore, a plurality of threshold values are provided so that a minute pattern can be detected.

The binarized outputs V _L , V _M , V _H obtained here and the standard image data V _R are compared by the disagreement detectors 284, 285, 286. In this case, outputs such as D ₁ , D ₂ and D ₃ are obtained as non-coincidence outputs. In the non-coincidence output, there are a mixture of the one caused by the misalignment of the standard image data V _R and the detected image data V _D and the one caused by the true defect. The logical sum of these is the defect candidate detection signal D from the defect detection circuit 28. Of course, an error that cannot be avoided even if the alignment correction is performed, for example, a 1-bit quantization error, is a misalignment when the mismatch between the standard image data V _R and the detected image data V _D is within that range. Comparing with the comparator 281-
283 is set. That is, as the defect candidate detection signal D, only true defect signals except those including the above unavoidable alignment error are candidates. The dead band width of the comparators 281 to 283 for preventing the detection of the false defects due to the misalignment can be made extremely small by the function of the alignment circuit described later as compared with the above-mentioned conventional example.

Further, the above defect detection will be specifically described.

First, clipping of a local image will be described with reference to a block diagram of an embodiment of the local image clipping circuit of FIG.

As shown in FIG. 8 (a), a local image composed of, for example, 3 × 3 pixels is cut out from the inspection side. This circuit uses a serial input / serial output shift register 280A, 280B for storing image data of one scanning line of the image pickup device, and a serial input / parallel output shift register 280C for reading image data in parallel. I am configuring.

On the other hand, the model side uses a serial input serial output shift register 280D and a serial input parallel output shift register 280E to extract a local image corresponding to a pixel in the central portion of the inspection side 3 × 3 local image. Is configured.

A defect determination method having a ± 1 bit alignment margin will be described with reference to FIG.

The cutout pixel b ₂₂ on the model side is a of the 3 × 3 cutout pixel on the inspection side.
_The phase (position) corresponds to ₂₂ .

For b ₂₂ is "1", when all of a _21, a _22, a ₂₃ is "0", and the defect as a horizontal discrepancy is found. When b ₂₂ is “0”, a ₂₁ , a ₂₂ , a
_When all of ₂₃ are "1", it is regarded as a defect that a horizontal disagreement is found.

FIG. 9 is a block diagram of an embodiment of the mismatch detector, which is composed of a logic circuit.

This is an example of a circuit that detects a mismatch in the horizontal direction by allowing a positioning error of ± 1 bit. By applying this to the vertical and diagonal directions as well, the position of the ± 1 bit in each direction can be detected. When the deviation is allowed and there is a difference of 2 bits or more, the defect is detected as a mismatch.

The defect candidate signal D interrupts the control / processing unit 19 via the interrupt controller 29, and the control / processing unit 19 correspondingly inputs the image signal to the analysis memories 26 and 27. To stop. Then, the image data including the defect candidate image stored in the analysis memory 26 is compared with the standard image data stored in the analysis memory 27 to perform a detailed analysis. Pseudo defects due to improper alignment and binarization level are removed by this detailed analysis, and only true defects are registered and recorded in the memory of the control / processing unit 19 together with the position coordinates.

A specific method of detailed analysis will be described below.

FIG. 10 is an explanatory view of a typical pseudo defect due to a positional shift, and it is assumed that defect candidates are detected by the mismatch detector shown in FIGS. 8 and 9.

This defect candidate detector interrupts the control / processing unit 19 as a defect also in the case of FIG. 10 in order to make the determination based on the information of only the 3 × 3 minute area.

The control / processing unit 19 reads the contents of the analysis memories 26 and 27. The analysis memory 26 is a memory of the inspection side pattern and is a multi-valued memory, which can be binarized by software. Since each of the analysis memories 26 and 27 stores an area of 3 × 3 or more, it is possible to check the pattern situation around the detected defect candidate necessary for analysis.

FIG. 10 shows an example of examining peripheral 5 × 5 pixels of a defect candidate. The pattern on the model side in Figure (a) (shaded line segment)
Is moved in the X and Y directions to check the amount of mismatch. It is assumed that when the image is moved, the portion protruding from the 5 × 5 is ignored, and the pattern information of the surrounding area is preserved where the image newly enters the 5 × 5 local image area. Fig. 10
The relation between (a) and (b) in the figure is moved in the X direction, and the relationship between the number of non-matching pixels and the amount of movement is examined.

Here, the positive direction is the direction in which (b) is moved to the right in FIG. 10 with respect to (a).

Obviously from this table, (b) is 2 pixels more than (a) X
It can be seen that is shifted in the positive direction. Therefore, it is concluded that the defect candidate detected by the defect candidate determiner is actually a defect detected due to the occurrence of the displacement of 2 bits and is a pseudo defect that should not be a defect. . Therefore, the position shift is +2 bits without being registered in the storage area as a defect. Therefore, the buffer memory 22 with position correction (for example, # 1) is instructed to correct the position shift, and the multiplexer 24 is set to the buffer memory 22. Switch after (for example, # 2).

Although the above is for the positional deviation in the X direction, the same analysis method can be applied to the positional deviation in the Y direction and the positional deviation in the X and Y directions. In addition, as a more detailed analysis method, the area to be examined is set to 5 × 5 or more, or the method of giving the threshold value when the multivalued information is binary is changed,
Various methods can be finely processed by software. The above is summarized and the detailed analysis flow is shown in FIG.

If the result of the analysis shows that the defect is a defect candidate due to misalignment, the control / processing unit 19 corrects the amount of misalignment at that time by the misalignment correction unit provided in each of the buffer memories 22 and 23. To do.

FIG. 12 shows a block diagram of an embodiment of the positional deviation correction unit. It is assumed that the two-dimensional image detected by the imager 14A is composed of, for example, 128 × 128 pixels.
The shift register 30 has a length of 12 pixels which is the same as the horizontal pixels.
A required number of 8-bit ones are connected in series, and the multiplexer 31 selectively switches the images to delay the image in the vertical direction. For example, when it is assumed the positional deviation corrector exemplars side position correction circuit 21, by selecting the multiplexer 31 output y _3, model side of the reference (standard) video signal, to detect the video signal 3
It will be delayed in the y direction by the number of pixels. On the contrary, when the position correction circuit 20 is configured as shown in FIG. 12, the detected video signal is delayed from the reference video signal on the model side by three pixels.

By switching the multiplexer 31, it is possible to align the images in the vertical direction between the detected video signal and the reference video signal, that is, in the Y direction. In FIG. 12, the shift register 70 is shown as having 1 bit × 128, but in the position correction circuit 20 and the like, the number of bits of the multi-gradation video signal × 128.
It is natural to use the ones. Similarly, it is possible to correct the positional deviation in the X direction depending on which parallel output of the shift register 32 of serial input or parallel output is selected by the multiplexer 33.

The control / processing unit 19 selects the multiplexers 31 and 33.
It is performed according to the positional deviation correction amount calculated in.

The analysis in the control / processing unit 19 takes much time as compared with the scanning of the image data in the case of an ordinary computer.

The buffer memories 22 and 23 are for storing the image data during the analysis so as not to be lost, and are composed of shift registers having a capacity capable of storing the image data for at least the time required for the analysis.

As a result of analysis, when it is found that it is a pseudo defect due to displacement,
Based on a command from the control / processing unit 19, after position adjustment is performed by the position correction circuit 20 or 21, the multiplexers 24 and 25 are switched to input the defect detection circuit 28 to the buffer memory 22 (including the position deviation correction unit). ), The stored detection image data during the analysis period after the alignment is completed, and the standard image data similarly stored during the analysis period are used as input data. The function of the defect detection circuit 28 during the analysis period is stopped by the control / processing unit 19, and after the switching of the multiplexers 24 and 25 is completed, the function is restarted.

By using the image buffer memory as described above, it is possible to realize a defect determination circuit that prevents data loss during detailed analysis and eliminates uninspected. By using m stages of this image buffer memory, pseudo defects up to m times can be removed by detailed analysis without generating an uninspected area.

In the photomask inspection, the first condition (I) makes it possible to shift the position of one chip at the time of the inspection by using image buffers of at most several stages.

By the conditions (II) and (III), when a defect is detected or in the dicing area, the image input to the defect detection circuit 28 can be returned to the initial state. Therefore, the image buffer memory can inspect all chips as long as the number of stages is the maximum required for inspection in one chip. Further, the position correction circuits 20 and 21 can keep correction of the alignment error accumulated due to the error of the scanning mechanical system and the like.

Although the method of electronically performing the alignment has been described above, in the alignment, an even better result can be obtained by moving the image pickup device 14A in the X and Y directions instead of the above.

The detailed analysis in the control / processing unit 19 is performed by, for example, the analysis memory 2
6 is performed with the grayscale image data, the positional deviation correction amount is determined by sampling between pixels when the image data obtained by the image pickup device 14A is converted into a multi-tone quantization digital image by the A / D converter 14B. By the interpolation calculation of the data of
A value of 1 bit or less can be obtained.

FIG. 13 illustrates the outline of this interpolation calculation, in which the abscissa of the detector is the abscissa and the ordinate is the detection output data. The detector is, for example, a linear image sensor, in which a large number of sensors such as n, n + 1, ... Are arranged, and the detection output is also quantized as shown in FIG. Therefore, by performing linear interpolation or higher-order interpolation of the values of n, n + 1, ..., The positional relationship between the detection output and the pixel can be obtained more finely.

Therefore, more accurate alignment can be realized by moving the image pickup device 14A by the value to correct it. In the imager 14A, the actual pattern of the mask 11 is magnified by the microscope 13C.
When the magnification is set to 0, 0.1 μm on the mask 11 becomes 5 μm on the imaging unit 14A, which is a value that can be easily mechanically adjusted.

In the above-described embodiments, the standard pattern data generated from design data is used, but the same applies to an apparatus that detects defects by comparing two different chips in one mask. Clearly, a defect determiner can be used.

Further, in the embodiment, the position shift compensators are provided on both the detection side and the model side, but one is provided with only the delay shift register, and the positive and negative alignment extraction positions are determined only from the other. You may

〔The invention's effect〕

As described above in detail, according to the present invention, since the defect candidate determination is performed while performing the alignment during the inspection, the structure of the defect candidate determiner can be made extremely simple and the cost can be greatly reduced. After the defect candidate is detected, the defect candidate image signal temporarily stored in the image memory and the partial reference pattern data corresponding to the defect candidate are read out only for the portion detected as the defect candidate, and a plurality of different plurality of them are read out. By performing a detailed analysis of the characteristic pattern elements by comparing with a standard, it is possible to judge from a true defect or a defect that does not cause harm in actual harm, and a sharp defect candidate detection that was not practically used in the past because of fear of increasing false judgments It is possible to obtain a pattern inspecting device that can be used as a result, and as a result, the detection sensitivity is greatly improved, and erroneous determination is prevented to speed up the process. Can exhibits e.g. reliability of the pattern inspection of a mask or the like for semiconductor production increase, a remarkable effect on the speed and economy.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a pattern detection unit of an example of a conventional pattern inspection apparatus, FIG. 2 is a principle diagram of its defect detection, and FIG.
FIG. 4 is a block diagram of an embodiment of a pattern inspection apparatus according to the present invention, FIG. 4 is an explanatory view of the two-dimensional pattern scanning thereof,
FIG. 5 is a block diagram of an embodiment of the defect candidate detection unit,
FIG. 6 is a block diagram of an embodiment of the defect detection circuit,
FIG. 7 is a time chart thereof, FIG. 8 is a block diagram of an embodiment of the local image cutout circuit, FIG. 9 is a block diagram of an embodiment of the inconsistency detector, and FIG. Explanatory drawing of a typical pseudo defect due to displacement, FIG. 11 is a flow chart of defect analysis of the control / processing unit, and FIG. 12 is
FIG. 13 is a block diagram of an embodiment of the displacement correction unit of the image buffer memory of the defect candidate detection unit, and FIG. 13 is an explanatory diagram of the sampling interpolation calculation. 11 ... Mask, 12A ... XY stage, 12B ... Mechanism control device, 12C ... Coordinate measuring device, 13A ... Illumination light source, 13
B ... Condenser lens, 13C ... Microscope, 14A ... Imager, 14B ... A / D converter, 14C ... Timing generation circuit, 15 ... Defect candidate detection part, 16 ... Bit pattern generator, 17 ... Memory interface, 18 ... Standard Data memory, 19 ... Control / processing unit, 20, 21 ... Position correction circuit, 22, 23 ... Buffer memory, 24, 25 ... Multiplexer, 26, 27 ... Analysis memory, 28 ... Defect detection circuit, 29 ... Interrupt controller.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideaki Doi, Inventor Hideaki Doi, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd., Production Engineering Laboratory, Hitachi, Ltd. (72) Susumu Aiuchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa House number Production company Hitachi, Ltd. Production Technology Research Laboratory (72) Inventor Mineo Nomoto 292 Yoshida-cho, Totsuka-ku, Yokohama City, Kanagawa Prefecture

Claims (1)

[Claims] 1. An image pickup means for picking up a pattern to be inspected to sequentially obtain image signals, a reference pattern data generation means for sequentially generating reference pattern data, an image signal sequentially obtained from the image pickup means, and the reference pattern data generation. Comparing means for correcting the positional deviation of the reference pattern data sequentially generated by the means, and comparing the detected patterns as defect candidates sequentially, and an inspection target pattern for which the positional deviation of the defect candidate portions sequentially detected by the comparing means is corrected. Of the defect candidate portion sequentially detected by the comparing means, out of the first storage means for temporarily storing the image signal as the defect candidate image signal in the image memory and the reference pattern data sequentially generated by the reference pattern data generating means. Second storage means for temporarily storing in the image memory the reference pattern data for which the positional deviation has been corrected, The defect candidate image signal temporarily stored in the image memory of the first storage means and the partial reference pattern data corresponding to the defect candidate portion temporarily stored in the image memory of the second storage means are read out to obtain a plurality of different references. The pattern inspecting apparatus further comprises: an analyzing unit that performs detailed analysis on the characteristic pattern elements by performing comparison with each other to exclude pseudo defects that are not practically harmful and determine remaining defect candidates as true defects.