JPH04256056A - Computer system - Google Patents

Abstract

PURPOSE:To improve the throughput of a computer system in a direct access control system. CONSTITUTION:An auxiliary storage device 16 which is connected to a direct access controller 13 by a local bus 18 different from a system bus 17 is provided. A transfer information table 28 to which information on data which the direct access controller 13 transfers to the auxiliary storage device 16 is stored. Thus, transfer information by the direct access controller 134 can be read without the aid of the system bus 17. Thus, the system bus 17 is prevented from being occupied by the reading of transfer information and the use time of the system bus 17 by the processor 11 can be prolonged. Thus, the processing performance of the computer system can be improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system equipped with a direct access control device that directly transfers data separately from a processor.

0002

2. Description of the Related Art In conventional computer systems, there is a method in which data transfer between a main storage device and an input/output device is performed by a processor and a separate direct access control device. This method is called DMA (Direct
(Memory Access) method. FIG. 2 is a block diagram showing an example of the configuration of a conventional computer system. The illustrated system includes a processor 41, a main storage device 42, a direct access control device 43, input/output control units 44, 45, etc. connected to a system bus 46. The processor 41 takes out the program in the main memory 42 one instruction at a time, and processes data in the main memory 42 and performs various controls in accordance with the instructions. The main storage device 42 is composed of a RAM (random access memory) and the like, and temporarily stores programs and data.

The direct access control device 43 is internally equipped with registers, etc., receives instructions from the processor 41, and separately from the processor 41, controls data between the main storage device 42 and the input/output control units 44 and 45. Control transfers. Input/output control units 44 and 45 control input/output devices 47 and 48, respectively. The input/output devices 47 and 48 are various input/output devices such as a magnetic disk, a keyboard, a display, and a printer.

FIG. 3 is a diagram showing the contents of the transfer information table. The illustrated transfer information table includes information 51 for the second block, information 52 for the third block, information 53 for the fourth block, information 54 for the n-1 block, information 55 for the n-th block, and the like. Each of these pieces of information includes the memory start address, the number of transfers, and the like. The memory start address is the start address on the main storage device 42 of the data block transferred by the direct access control device 43. The number of transfers is the number of transfers until the transfer of the data block is completed. This transfer information table is stored in the main storage device 42 in the system of FIG. The start address of the transfer information table on the main storage device 42, chain mode, and other control modes are stored in the direct access control device 43.

Next, the operation of the above-mentioned system will be explained. That is, data transfer by the direct access control device 43 is performed between the main storage device 42 and the input/output device 47 or 48 according to the following procedures (1) to (9). (1) The processor 41 sets the memory start address for data transfer, the number of transfers, the chain mode, the start address of the transfer information table, and other control modes in the direct access control device 43 via the system bus 46. (2) The direct access control device 43 is connected to the system bus 4
Request the right to use 6. Bus rights are acquired by responding to permission to use. (3) The direct access control device 43 sends the memory address of the transfer information table and the control signal to the system bus 46, reads the memory start address of the second transfer block and the number of transfers, and reads the memory address of the transfer information table and the control signal to the system bus 46. Store in register.

(4) The input/output control unit 44 or 45 requests the direct access control device 43 to transfer data. (5) The direct access control device 43 is connected to the system bus 4
Request the right to use 6 and obtain the right to use the bus. (6) The direct access control device 43 sends the memory address and control signal to the system bus 46, and the main storage device 4
2 and the input/output device 47 or 48. (7) Until the number of transfers is reached, (4) , (5) ,
(6) Repeat the process.

(8) When the transfer of one block is completed, the bus right of the system bus 46 is acquired, and the memory start address and the number of transfers of the third transfer block are directly read into the register of the access control device 43 from the transfer information table. (9) The second block transfer starts, and the process described in (4) above begins.
, (5), (6), and (7) are repeated. Further, from the third block transfer onward, data transfer is performed for any number of blocks until the chain mode ends.

[0008]

[Problems to be Solved by the Invention] However, the above-mentioned conventional technology has the following problems. That is, in the system configured as described above, after setting the chain mode of the direct access control device 43, it takes a long time for the direct access control device 43 to acquire the system bus 46 and read the transfer information table. In other words, the direct access control device 43 occupies the system bus 46 for a long time. During this time, the processor 41 and other input/output devices 47 and 48 cannot use the system bus 46. Therefore, there has been a problem in that the processing power of the computer system is reduced. The present invention has been made with attention to the above points, and eliminates the problem of occupying the system bus for a long time when a direct access control device reads a transfer information table, thereby providing an excellent computer system with high processing performance. The purpose is to provide

[0009]

[Means for Solving the Problems] A computer system of the present invention includes a main storage device connected to a system bus;
In a computer system in which data transfer between input and output devices is performed by a processor and a separate direct access control device, a secondary storage device is provided which is connected to the direct access control device by a local bus separate from the system bus, and the secondary storage device The device is characterized in that a transfer information table storing information regarding data transferred by the direct access control device is stored in the device.

0010

In the computer system of the present invention, the direct access control device reads transfer information from a transfer information table stored in a sub-storage device connected to the system bus by a separate local bus. Therefore, this reading is performed without going through the system bus. As a result,
The system bus is no longer occupied by reading transfer information, and the time the processor uses the system bus can be extended accordingly. In this way, the processing capacity of the computer system can be improved.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the computer system of the present invention. The illustrated system includes a processor 11, a main storage device 12, a direct access control device 13, input/output control sections 14 and 15, etc. connected to a system bus 17. The processor 11 takes out the program in the main memory 12 one instruction at a time, and processes data in the main memory 12 and performs various controls in accordance with the instructions. The main storage device 12 is RAM (random memory).
access memory), etc., and temporarily stores programs and data.

Direct access control device 13 receives instructions from processor 11 and controls data transfer between main storage device 12 and input/output control sections 14 and 15 separately from processor 11. This direct access control device 13 is a DM
It includes an A controller 21, a determination circuit 22, and the like. The input/output control units 14 and 15 are input/output devices 19 and 2, respectively.
Controls data input/output of 0. Input/output device 19, 2
0 is various input/output devices such as a magnetic disk, a keyboard, a display, and a printer. The secondary storage device 16 is
It consists of a RAM, etc., and stores the transfer information table shown in FIG. 3 mentioned above. The local bus 18 is a bus that is provided separately from the system bus 17 and is connected between the direct access control device and the secondary storage device 16.

FIG. 4 is a block diagram showing the detailed configuration of the direct access control device according to the present invention. The illustrated device includes a DMA controller 21, a determination circuit 22, a system bus interface 23, a system bus extended address register 24, and a local bus interface 25.
, a local bus extended address register 26, a register write signal generation circuit 27, and the like. Based on the transfer information stored in the secondary storage device 16, the DMA controller 21 transfers the data in FIG.
Data is transferred between the main storage device 12 and the input/output device 14 or 15 shown in FIG.

The determination circuit 22 is a DM shown in FIG. 5, which will be described later.
The A address space is determined. The system bus interface 23 is an interface that connects the DMA control 21 and the system bus 17. The system bus extension address register 24 is a register for extending the address of the system bus 17. The local bus interface 25 has a DMA control 21 and
This is an interface for connecting with the local bus 18. The local bus extension address register 26 is a register for extending the address of the local bus 18. The register write signal generation circuit 27 generates set signals 67 and 68 that instruct data writing to the system bus extended address register 24 and the local bus extended address register 26.

FIG. 5 is a diagram showing the structure of a DMA address space according to the present invention. As shown in the figure, the DMA address space consists of 16 megabytes from "0" to "FFFFFF", and is divided into a first half 30 and a second half 31. The first half 30 of the DMA address space is “0” to “7FFF”
The first half 30 of this DMA address space consists of 8 megabytes of "FF".
It is assigned to... System bus memory space 80
, 81, . . . are memory spaces connected to the system bus 17. The second half 31 of the DMA address space is “8
The second half 31 of this DMA address space is allocated to local bus memory spaces 90, 91, . . . The local bus memory spaces 90, 91, . is a memory space connected to

Next, the operation of the above system will be explained. FIG. 6 is a time chart explaining the operation of the system of the present invention. In the figure, (a) to (p) correspond to buses or signal lines 61 to 76. (1) Issue a command to write "0" to the system bus extended address register 24 from the processor 11 via the system bus 17 and system bus interface 23. Then, the set signal 67 of the system bus extended address register 24 is enabled by the write signals of the address bus 64 and the control line 66, and "0" is set in the system bus extended address register 24 (
Time t1). Next, a command to write "0" to the local bus expansion register 26 is issued. Then, the set signal 68 of the local bus extended address register 26 becomes valid due to the write signals of the address bus 64 and the control line 66, and "0" is set in the local bus extended address register 26 (time t2).

(2) Transfer information is set from the processor 11 to the transfer information table 28 in the secondary storage device 16 via the system bus 17, system bus interface 23, and local bus interface 25 (time t3). (3) The processor 11 sets the memory start address, the number of transfers, the chain mode, the start address of the transfer information table, and other control information in the DMA controller 21 (time t4). (4) When the DMA controller 21 enters the transfer mode, it first sends the address A23 and addresses A22 to A1 to the address line 69 and the address bus 64, respectively, in order to read information for the second block transfer from the transfer information table. Also, a control signal is sent to the control line 66 (time t5).

(5) The value of A23 of the address line 69 is
The determination circuit 22 makes the signal line 71 valid (time t6). (6) As the signal line 71 becomes valid, the local bus interface 25 becomes valid, and the address bus 7
4 and control line 76 from the local bus interface 25 to read the contents of the transfer information table on the secondary storage device 16. At this time, A22 to A1 send out the address of the DMA control 21, and A27 to A23 send out the value of the local bus extended address register 26 (time t7). (7) Until you finish reading the contents of the transfer information table (
4) Repeat steps (5) and (6).

(8) Next, the input/output control unit 14 requests the DMA controller 21 to transfer data to the main storage device 12. The DMA controller 21 enters the transfer mode and sends addresses A23 to A1 and control signals to the address line 69, address bus 64, and control line 66 (time t8). (9) The value of address A23 on address line 69 is “0”.
”, and the determination circuit 22 makes the signal line 70 valid (time t9). (10) Since the signal line 70 has become valid, the system bus interface 23 requests the right to use the system bus 17.

(11) After acquiring the right to use the system bus 17, address and control signals are sent from the system bus interface 23 to the address bus 61 and control line 63. As a result, the main storage device 12
and the input/output control unit 14 via the data bus 62 (time t10). (12) The direct access control device 13 releases the bus right when one transfer is completed. (13) Then, the direct access control device 13 performs (8), (9), (10), (
11) Repeat steps (12).

(14) After the transfer of the first block is completed and before the start of transfer of the second block, the information on the third block transfer is DM'd from the transfer information table 28 of the secondary storage device 16.
The data is read into the A controller 21. In other words, (4) above
, (5) and (6) are repeated (time t11). In this way, block transfers are performed until the chain mode ends.

In the above embodiment, the system bus extended address register 24 shown in FIG. 4 has 5 bits. The value of this system bus extended address register 24 is DM
This corresponds to addresses A27 to A23 at the time of data transfer by A. When the value "0" of the system bus extended address register 24 is set to "1", the 8 megabyte space from "800000" to "FFFFFF" of the system bus memory space can be accessed. The maximum value of the system bus extended address register 24 is "1F", and data can be transferred by DMA up to 256 bytes of the system bus address space.

Similarly, the values of the local bus extended address register 26 shown in FIG. 4 correspond to the local address buses A27 to A23 during data transfer by DMA. Value of local bus extended address register 26 “0”
When set to “1”, “800” in the local bus memory space
Can access 8 megabyte space from "000" to "FFFFFF".Extended address register 26 for local bus
The maximum value of is "1F", and data transfer using DMA can be performed up to 256 bytes of the address space of the local bus.

[0024]

As explained above, according to the computer system of the present invention, the transfer information table is set in a secondary storage device that is not directly connected to the system bus, so that while the direct access control device is reading the transfer information table, Even processors and input/output devices can use the system bus. Additionally, by providing a circuit that determines the data transfer destination memory based on the address sent from the direct access control device, it is possible to have two or more buses and transfer data to each storage device connected to each bus. can. Further, by providing a register that serves as an upper address during data transfer, data can be transferred to a storage device having an address space larger than the address space of the direct access control device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of a computer system of the present invention.

FIG. 2 is a block diagram showing an example of the configuration of a conventional computer system.

FIG. 3 is a diagram showing the contents of a transfer information table.

FIG. 4 is a block diagram showing a detailed configuration of a direct access control device according to the present invention.

FIG. 5 is a diagram showing the configuration of a DMA address space according to the present invention.

FIG. 6 is a time chart explaining the operation of the system of the present invention.

[Explanation of symbols]

11 Processor 12 Main memory 13 Direct access control device 14, 15 Input/output control section 16. Secondary storage device 17 System bus 18 Local bus 19, 20 Input/output device 28 Transfer information table

Claims (1)

[Claims] 1. A computer system in which data transfer between a main storage device and an input/output device connected to a system bus is performed by a processor and a separate direct access control device, wherein the A computer system comprising: a secondary storage device connected to a direct access control device; and a transfer information table storing information regarding data to be transferred by the direct access control device is stored in the secondary storage device.